LXR qemu/include/hw/net/cadence

   1/*
   2 * QEMU Cadence GEM emulation
   3 *
   4 * Copyright (c) 2011 Xilinx, Inc.
   5 *
   6 * Permission is hereby granted, free of charge, to any person obtaining a copy
   7 * of this software and associated documentation files (the "Software"), to deal
   8 * in the Software without restriction, including without limitation the rights
   9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10 * copies of the Software, and to permit persons to whom the Software is
  11 * furnished to do so, subject to the following conditions:
  12 *
  13 * The above copyright notice and this permission notice shall be included in
  14 * all copies or substantial portions of the Software.
  15 *
  16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22 * THE SOFTWARE.
  23 */
  24
  25#ifndef CADENCE_GEM_H
  26#define CADENCE_GEM_H
  27#include "qom/object.h"
  28
  29#define TYPE_CADENCE_GEM "cadence_gem"
  30OBJECT_DECLARE_SIMPLE_TYPE(CadenceGEMState, CADENCE_GEM)
  31
  32#include "net/net.h"
  33#include "hw/sysbus.h"
  34#include "hw/mdio/mdio.h"
  35
  36#define CADENCE_GEM_MAXREG        (0x00000800 / 4) /* Last valid GEM address */
  37
  38/* Max number of words in a DMA descriptor.  */
  39#define DESC_MAX_NUM_WORDS              6
  40
  41#define MAX_PRIORITY_QUEUES             8
  42#define MAX_TYPE1_SCREENERS             16
  43#define MAX_TYPE2_SCREENERS             16
  44
  45#define MAX_JUMBO_FRAME_SIZE_MASK 0x3FFF
  46#define MAX_FRAME_SIZE MAX_JUMBO_FRAME_SIZE_MASK
  47
  48struct CadenceGEMState {
  49    /*< private >*/
  50    SysBusDevice parent_obj;
  51
  52    /*< public >*/
  53    MemTxAttrs *attr_r;
  54    MemTxAttrs *attr_w;
  55    MemoryRegion iomem;
  56    MemoryRegion *dma_mr;
  57    AddressSpace dma_as;
  58    NICState *nic;
  59    NICConf conf;
  60    qemu_irq irq[MAX_PRIORITY_QUEUES];
  61
  62    /* Static properties */
  63    uint8_t num_priority_queues;
  64    uint8_t num_type1_screeners;
  65    uint8_t num_type2_screeners;
  66    uint32_t revision;
  67    uint16_t jumbo_max_len;
  68
  69    /* GEM registers backing store */
  70    uint32_t regs[CADENCE_GEM_MAXREG];
  71    /* Mask of register bits which are write only */
  72    uint32_t regs_wo[CADENCE_GEM_MAXREG];
  73    /* Mask of register bits which are read only */
  74    uint32_t regs_ro[CADENCE_GEM_MAXREG];
  75    /* Mask of register bits which are clear on read */
  76    uint32_t regs_rtc[CADENCE_GEM_MAXREG];
  77    /* Mask of register bits which are write 1 to clear */
  78    uint32_t regs_w1c[CADENCE_GEM_MAXREG];
  79
  80    /* PHY address */
  81    uint8_t phy_addr;
  82    /* PHY registers backing store */
  83    uint16_t phy_regs[32];
  84
  85    uint8_t phy_loop; /* Are we in phy loopback? */
  86
  87    /* The current DMA descriptor pointers */
  88    uint32_t rx_desc_addr[MAX_PRIORITY_QUEUES];
  89    uint32_t tx_desc_addr[MAX_PRIORITY_QUEUES];
  90
  91    uint8_t can_rx_state; /* Debug only */
  92
  93    uint8_t tx_packet[MAX_FRAME_SIZE];
  94    uint8_t rx_packet[MAX_FRAME_SIZE];
  95    uint32_t rx_desc[MAX_PRIORITY_QUEUES][DESC_MAX_NUM_WORDS];
  96
  97    bool sar_active[4];
  98    MDIO *mdio;
  99};
 100
 101#endif
 102