LXR qemu/target/arm/cpu-qom.h

   1/*
   2 * QEMU ARM CPU
   3 *
   4 * Copyright (c) 2012 SUSE LINUX Products GmbH
   5 *
   6 * This program is free software; you can redistribute it and/or
   7 * modify it under the terms of the GNU General Public License
   8 * as published by the Free Software Foundation; either version 2
   9 * of the License, or (at your option) any later version.
  10 *
  11 * This program is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 * GNU General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU General Public License
  17 * along with this program; if not, see
  18 * <http://www.gnu.org/licenses/gpl-2.0.html>
  19 */
  20#ifndef QEMU_ARM_CPU_QOM_H
  21#define QEMU_ARM_CPU_QOM_H
  22
  23#include "hw/core/cpu.h"
  24#include "qom/object.h"
  25
  26struct arm_boot_info;
  27
  28#define TYPE_ARM_CPU "arm-cpu"
  29
  30OBJECT_DECLARE_TYPE(ARMCPU, ARMCPUClass,
  31                    ARM_CPU)
  32
  33#define ARM_CPU_PARENT_CLASS \
  34    object_class_get_parent(object_class_by_name(TYPE_ARM_CPU))
  35
  36#define TYPE_ARM_MAX_CPU "max-" TYPE_ARM_CPU
  37
  38typedef struct ARMCPUInfo {
  39    const char *name;
  40    void (*initfn)(Object *obj);
  41    void (*class_init)(ObjectClass *oc, void *data);
  42} ARMCPUInfo;
  43
  44void arm_cpu_register(const ARMCPUInfo *info);
  45void aarch64_cpu_register(const ARMCPUInfo *info);
  46
  47/**
  48 * ARMCPUClass:
  49 * @parent_realize: The parent class' realize handler.
  50 * @parent_reset: The parent class' reset handler.
  51 *
  52 * An ARM CPU model.
  53 */
  54struct ARMCPUClass {
  55    /*< private >*/
  56    CPUClass parent_class;
  57    /*< public >*/
  58
  59    const ARMCPUInfo *info;
  60    DeviceRealize parent_realize;
  61    DeviceReset parent_reset;
  62};
  63
  64
  65#define TYPE_AARCH64_CPU "aarch64-cpu"
  66typedef struct AArch64CPUClass AArch64CPUClass;
  67DECLARE_CLASS_CHECKERS(AArch64CPUClass, AARCH64_CPU,
  68                       TYPE_AARCH64_CPU)
  69
  70struct AArch64CPUClass {
  71    /*< private >*/
  72    ARMCPUClass parent_class;
  73    /*< public >*/
  74};
  75
  76void register_cp_regs_for_features(ARMCPU *cpu);
  77void init_cpreg_list(ARMCPU *cpu);
  78
  79/* Callback functions for the generic timer's timers. */
  80void arm_gt_ptimer_cb(void *opaque);
  81void arm_gt_vtimer_cb(void *opaque);
  82void arm_gt_htimer_cb(void *opaque);
  83void arm_gt_stimer_cb(void *opaque);
  84void arm_gt_hvtimer_cb(void *opaque);
  85
  86#define ARM_AFF0_SHIFT 0
  87#define ARM_AFF0_MASK  (0xFFULL << ARM_AFF0_SHIFT)
  88#define ARM_AFF1_SHIFT 8
  89#define ARM_AFF1_MASK  (0xFFULL << ARM_AFF1_SHIFT)
  90#define ARM_AFF2_SHIFT 16
  91#define ARM_AFF2_MASK  (0xFFULL << ARM_AFF2_SHIFT)
  92#define ARM_AFF3_SHIFT 32
  93#define ARM_AFF3_MASK  (0xFFULL << ARM_AFF3_SHIFT)
  94#define ARM_DEFAULT_CPUS_PER_CLUSTER 8
  95
  96#define ARM32_AFFINITY_MASK (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK)
  97#define ARM64_AFFINITY_MASK \
  98    (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK|ARM_AFF3_MASK)
  99#define ARM64_AFFINITY_INVALID (~ARM64_AFFINITY_MASK)
 100
 101#endif
 102