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27#include "qemu/osdep.h"
28#include "hw/sysbus.h"
29#include "hw/register.h"
30#include "qemu/bitops.h"
31#include "qemu/log.h"
32#include "migration/vmstate.h"
33#include "hw/irq.h"
34
35#ifndef XILINX_CPM5_SLCR_SECURE_ERR_DEBUG
36#define XILINX_CPM5_SLCR_SECURE_ERR_DEBUG 0
37#endif
38
39#define TYPE_XILINX_CPM5_SLCR_SECURE "xlnx.cpm5_slcr_secure"
40
41#define XILINX_CPM5_SLCR_SECURE(obj) \
42 OBJECT_CHECK(CPM5_SLCR_SECURE, (obj), TYPE_XILINX_CPM5_SLCR_SECURE)
43
44REG32(WPROTS, 0x0)
45 FIELD(WPROTS, ACTIVE, 0, 1)
46REG32(WPROTP, 0x4)
47 FIELD(WPROTP, ACTIVE, 0, 1)
48REG32(TZPROT, 0x8)
49 FIELD(TZPROT, ACTIVE, 0, 1)
50REG32(REG_CTRL, 0xc)
51 FIELD(REG_CTRL, SLVERR_ENABLE, 0, 1)
52REG32(IR_STATUS, 0x10)
53 FIELD(IR_STATUS, ADDR_DECODE_ERR, 0, 1)
54REG32(IR_MASK, 0x14)
55 FIELD(IR_MASK, ADDR_DECODE_ERR, 0, 1)
56REG32(IR_ENABLE, 0x18)
57 FIELD(IR_ENABLE, ADDR_DECODE_ERR, 0, 1)
58REG32(IR_DISABLE, 0x1c)
59 FIELD(IR_DISABLE, ADDR_DECODE_ERR, 0, 1)
60REG32(TZ_PCIE0, 0x100)
61 FIELD(TZ_PCIE0, ATTRIB_PCIE, 1, 1)
62 FIELD(TZ_PCIE0, CFG_MGMT_PCIE, 0, 1)
63REG32(TZ_PCIE1, 0x104)
64 FIELD(TZ_PCIE1, ATTRIB_PCIE, 1, 1)
65 FIELD(TZ_PCIE1, CFG_MGMT_PCIE, 0, 1)
66REG32(TZ_DMA0_0, 0x108)
67 FIELD(TZ_DMA0_0, ATTR_DMA_AXIBAR2PCIEBAR_SEC_5, 11, 1)
68 FIELD(TZ_DMA0_0, ATTR_DMA_AXIBAR2PCIEBAR_SEC_4, 10, 1)
69 FIELD(TZ_DMA0_0, ATTR_DMA_AXIBAR2PCIEBAR_SEC_3, 9, 1)
70 FIELD(TZ_DMA0_0, ATTR_DMA_AXIBAR2PCIEBAR_SEC_2, 8, 1)
71 FIELD(TZ_DMA0_0, ATTR_DMA_AXIBAR2PCIEBAR_SEC_1, 7, 1)
72 FIELD(TZ_DMA0_0, ATTR_DMA_AXIBAR2PCIEBAR_SEC_0, 6, 1)
73 FIELD(TZ_DMA0_0, ATTR_DMA_CH3_SEC, 5, 1)
74 FIELD(TZ_DMA0_0, ATTR_DMA_CH2_SEC, 4, 1)
75 FIELD(TZ_DMA0_0, ATTR_DMA_CH1_SEC, 3, 1)
76 FIELD(TZ_DMA0_0, ATTR_DMA_CH0_SEC, 2, 1)
77 FIELD(TZ_DMA0_0, ATTR_DMA_ENABLE_SECURE, 1, 1)
78 FIELD(TZ_DMA0_0, ATTRIB_DMA, 0, 1)
79REG32(TZ_DMA0_1, 0x10c)
80 FIELD(TZ_DMA0_1, ATTR_DMA_PCIEBAR2AXIBAR_SEC_VF_PF15, 31, 1)
81 FIELD(TZ_DMA0_1, ATTR_DMA_PCIEBAR2AXIBAR_SEC_VF_PF14, 30, 1)
82 FIELD(TZ_DMA0_1, ATTR_DMA_PCIEBAR2AXIBAR_SEC_VF_PF13, 29, 1)
83 FIELD(TZ_DMA0_1, ATTR_DMA_PCIEBAR2AXIBAR_SEC_VF_PF12, 28, 1)
84 FIELD(TZ_DMA0_1, ATTR_DMA_PCIEBAR2AXIBAR_SEC_VF_PF11, 27, 1)
85 FIELD(TZ_DMA0_1, ATTR_DMA_PCIEBAR2AXIBAR_SEC_VF_PF10, 26, 1)
86 FIELD(TZ_DMA0_1, ATTR_DMA_PCIEBAR2AXIBAR_SEC_VF_PF9, 25, 1)
87 FIELD(TZ_DMA0_1, ATTR_DMA_PCIEBAR2AXIBAR_SEC_VF_PF8, 24, 1)
88 FIELD(TZ_DMA0_1, ATTR_DMA_PCIEBAR2AXIBAR_SEC_VF_PF7, 23, 1)
89 FIELD(TZ_DMA0_1, ATTR_DMA_PCIEBAR2AXIBAR_SEC_VF_PF6, 22, 1)
90 FIELD(TZ_DMA0_1, ATTR_DMA_PCIEBAR2AXIBAR_SEC_VF_PF5, 21, 1)
91 FIELD(TZ_DMA0_1, ATTR_DMA_PCIEBAR2AXIBAR_SEC_VF_PF4, 20, 1)
92 FIELD(TZ_DMA0_1, ATTR_DMA_PCIEBAR2AXIBAR_SEC_VF_PF3, 19, 1)
93 FIELD(TZ_DMA0_1, ATTR_DMA_PCIEBAR2AXIBAR_SEC_VF_PF2, 18, 1)
94 FIELD(TZ_DMA0_1, ATTR_DMA_PCIEBAR2AXIBAR_SEC_VF_PF1, 17, 1)
95 FIELD(TZ_DMA0_1, ATTR_DMA_PCIEBAR2AXIBAR_SEC_VF_PF0, 16, 1)
96 FIELD(TZ_DMA0_1, ATTR_DMA_PCIEBAR2AXIBAR_SEC_PF15, 15, 1)
97 FIELD(TZ_DMA0_1, ATTR_DMA_PCIEBAR2AXIBAR_SEC_PF14, 14, 1)
98 FIELD(TZ_DMA0_1, ATTR_DMA_PCIEBAR2AXIBAR_SEC_PF13, 13, 1)
99 FIELD(TZ_DMA0_1, ATTR_DMA_PCIEBAR2AXIBAR_SEC_PF12, 12, 1)
100 FIELD(TZ_DMA0_1, ATTR_DMA_PCIEBAR2AXIBAR_SEC_PF11, 11, 1)
101 FIELD(TZ_DMA0_1, ATTR_DMA_PCIEBAR2AXIBAR_SEC_PF10, 10, 1)
102 FIELD(TZ_DMA0_1, ATTR_DMA_PCIEBAR2AXIBAR_SEC_PF9, 9, 1)
103 FIELD(TZ_DMA0_1, ATTR_DMA_PCIEBAR2AXIBAR_SEC_PF8, 8, 1)
104 FIELD(TZ_DMA0_1, ATTR_DMA_PCIEBAR2AXIBAR_SEC_PF7, 7, 1)
105 FIELD(TZ_DMA0_1, ATTR_DMA_PCIEBAR2AXIBAR_SEC_PF6, 6, 1)
106 FIELD(TZ_DMA0_1, ATTR_DMA_PCIEBAR2AXIBAR_SEC_PF5, 5, 1)
107 FIELD(TZ_DMA0_1, ATTR_DMA_PCIEBAR2AXIBAR_SEC_PF4, 4, 1)
108 FIELD(TZ_DMA0_1, ATTR_DMA_PCIEBAR2AXIBAR_SEC_PF3, 3, 1)
109 FIELD(TZ_DMA0_1, ATTR_DMA_PCIEBAR2AXIBAR_SEC_PF2, 2, 1)
110 FIELD(TZ_DMA0_1, ATTR_DMA_PCIEBAR2AXIBAR_SEC_PF1, 1, 1)
111 FIELD(TZ_DMA0_1, ATTR_DMA_PCIEBAR2AXIBAR_SEC_PF0, 0, 1)
112REG32(TZ_DMA0_2, 0x110)
113 FIELD(TZ_DMA0_2, ATTR_DMA_SEC_VF_PF15, 31, 1)
114 FIELD(TZ_DMA0_2, ATTR_DMA_SEC_VF_PF14, 30, 1)
115 FIELD(TZ_DMA0_2, ATTR_DMA_SEC_VF_PF13, 29, 1)
116 FIELD(TZ_DMA0_2, ATTR_DMA_SEC_VF_PF12, 28, 1)
117 FIELD(TZ_DMA0_2, ATTR_DMA_SEC_VF_PF11, 27, 1)
118 FIELD(TZ_DMA0_2, ATTR_DMA_SEC_VF_PF10, 26, 1)
119 FIELD(TZ_DMA0_2, ATTR_DMA_SEC_VF_PF9, 25, 1)
120 FIELD(TZ_DMA0_2, ATTR_DMA_SEC_VF_PF8, 24, 1)
121 FIELD(TZ_DMA0_2, ATTR_DMA_SEC_VF_PF7, 23, 1)
122 FIELD(TZ_DMA0_2, ATTR_DMA_SEC_VF_PF6, 22, 1)
123 FIELD(TZ_DMA0_2, ATTR_DMA_SEC_VF_PF5, 21, 1)
124 FIELD(TZ_DMA0_2, ATTR_DMA_SEC_VF_PF4, 20, 1)
125 FIELD(TZ_DMA0_2, ATTR_DMA_SEC_VF_PF3, 19, 1)
126 FIELD(TZ_DMA0_2, ATTR_DMA_SEC_VF_PF2, 18, 1)
127 FIELD(TZ_DMA0_2, ATTR_DMA_SEC_VF_PF1, 17, 1)
128 FIELD(TZ_DMA0_2, ATTR_DMA_SEC_VF_PF0, 16, 1)
129 FIELD(TZ_DMA0_2, ATTR_DMA_SEC_PF15, 15, 1)
130 FIELD(TZ_DMA0_2, ATTR_DMA_SEC_PF14, 14, 1)
131 FIELD(TZ_DMA0_2, ATTR_DMA_SEC_PF13, 13, 1)
132 FIELD(TZ_DMA0_2, ATTR_DMA_SEC_PF12, 12, 1)
133 FIELD(TZ_DMA0_2, ATTR_DMA_SEC_PF11, 11, 1)
134 FIELD(TZ_DMA0_2, ATTR_DMA_SEC_PF10, 10, 1)
135 FIELD(TZ_DMA0_2, ATTR_DMA_SEC_PF9, 9, 1)
136 FIELD(TZ_DMA0_2, ATTR_DMA_SEC_PF8, 8, 1)
137 FIELD(TZ_DMA0_2, ATTR_DMA_SEC_PF7, 7, 1)
138 FIELD(TZ_DMA0_2, ATTR_DMA_SEC_PF6, 6, 1)
139 FIELD(TZ_DMA0_2, ATTR_DMA_SEC_PF5, 5, 1)
140 FIELD(TZ_DMA0_2, ATTR_DMA_SEC_PF4, 4, 1)
141 FIELD(TZ_DMA0_2, ATTR_DMA_SEC_PF3, 3, 1)
142 FIELD(TZ_DMA0_2, ATTR_DMA_SEC_PF2, 2, 1)
143 FIELD(TZ_DMA0_2, ATTR_DMA_SEC_PF1, 1, 1)
144 FIELD(TZ_DMA0_2, ATTR_DMA_SEC_PF0, 0, 1)
145REG32(TZ_DMA1_0, 0x114)
146 FIELD(TZ_DMA1_0, ATTR_DMA_AXIBAR2PCIEBAR_SEC_5, 11, 1)
147 FIELD(TZ_DMA1_0, ATTR_DMA_AXIBAR2PCIEBAR_SEC_4, 10, 1)
148 FIELD(TZ_DMA1_0, ATTR_DMA_AXIBAR2PCIEBAR_SEC_3, 9, 1)
149 FIELD(TZ_DMA1_0, ATTR_DMA_AXIBAR2PCIEBAR_SEC_2, 8, 1)
150 FIELD(TZ_DMA1_0, ATTR_DMA_AXIBAR2PCIEBAR_SEC_1, 7, 1)
151 FIELD(TZ_DMA1_0, ATTR_DMA_AXIBAR2PCIEBAR_SEC_0, 6, 1)
152 FIELD(TZ_DMA1_0, ATTR_DMA_CH3_SEC, 5, 1)
153 FIELD(TZ_DMA1_0, ATTR_DMA_CH2_SEC, 4, 1)
154 FIELD(TZ_DMA1_0, ATTR_DMA_CH1_SEC, 3, 1)
155 FIELD(TZ_DMA1_0, ATTR_DMA_CH0_SEC, 2, 1)
156 FIELD(TZ_DMA1_0, ATTR_DMA_ENABLE_SECURE, 1, 1)
157 FIELD(TZ_DMA1_0, ATTRIB_DMA, 0, 1)
158REG32(TZ_DMA1_1, 0x118)
159 FIELD(TZ_DMA1_1, ATTR_DMA_PCIEBAR2AXIBAR_SEC_VF_PF15, 31, 1)
160 FIELD(TZ_DMA1_1, ATTR_DMA_PCIEBAR2AXIBAR_SEC_VF_PF14, 30, 1)
161 FIELD(TZ_DMA1_1, ATTR_DMA_PCIEBAR2AXIBAR_SEC_VF_PF13, 29, 1)
162 FIELD(TZ_DMA1_1, ATTR_DMA_PCIEBAR2AXIBAR_SEC_VF_PF12, 28, 1)
163 FIELD(TZ_DMA1_1, ATTR_DMA_PCIEBAR2AXIBAR_SEC_VF_PF11, 27, 1)
164 FIELD(TZ_DMA1_1, ATTR_DMA_PCIEBAR2AXIBAR_SEC_VF_PF10, 26, 1)
165 FIELD(TZ_DMA1_1, ATTR_DMA_PCIEBAR2AXIBAR_SEC_VF_PF9, 25, 1)
166 FIELD(TZ_DMA1_1, ATTR_DMA_PCIEBAR2AXIBAR_SEC_VF_PF8, 24, 1)
167 FIELD(TZ_DMA1_1, ATTR_DMA_PCIEBAR2AXIBAR_SEC_VF_PF7, 23, 1)
168 FIELD(TZ_DMA1_1, ATTR_DMA_PCIEBAR2AXIBAR_SEC_VF_PF6, 22, 1)
169 FIELD(TZ_DMA1_1, ATTR_DMA_PCIEBAR2AXIBAR_SEC_VF_PF5, 21, 1)
170 FIELD(TZ_DMA1_1, ATTR_DMA_PCIEBAR2AXIBAR_SEC_VF_PF4, 20, 1)
171 FIELD(TZ_DMA1_1, ATTR_DMA_PCIEBAR2AXIBAR_SEC_VF_PF3, 19, 1)
172 FIELD(TZ_DMA1_1, ATTR_DMA_PCIEBAR2AXIBAR_SEC_VF_PF2, 18, 1)
173 FIELD(TZ_DMA1_1, ATTR_DMA_PCIEBAR2AXIBAR_SEC_VF_PF1, 17, 1)
174 FIELD(TZ_DMA1_1, ATTR_DMA_PCIEBAR2AXIBAR_SEC_VF_PF0, 16, 1)
175 FIELD(TZ_DMA1_1, ATTR_DMA_PCIEBAR2AXIBAR_SEC_PF15, 15, 1)
176 FIELD(TZ_DMA1_1, ATTR_DMA_PCIEBAR2AXIBAR_SEC_PF14, 14, 1)
177 FIELD(TZ_DMA1_1, ATTR_DMA_PCIEBAR2AXIBAR_SEC_PF13, 13, 1)
178 FIELD(TZ_DMA1_1, ATTR_DMA_PCIEBAR2AXIBAR_SEC_PF12, 12, 1)
179 FIELD(TZ_DMA1_1, ATTR_DMA_PCIEBAR2AXIBAR_SEC_PF11, 11, 1)
180 FIELD(TZ_DMA1_1, ATTR_DMA_PCIEBAR2AXIBAR_SEC_PF10, 10, 1)
181 FIELD(TZ_DMA1_1, ATTR_DMA_PCIEBAR2AXIBAR_SEC_PF9, 9, 1)
182 FIELD(TZ_DMA1_1, ATTR_DMA_PCIEBAR2AXIBAR_SEC_PF8, 8, 1)
183 FIELD(TZ_DMA1_1, ATTR_DMA_PCIEBAR2AXIBAR_SEC_PF7, 7, 1)
184 FIELD(TZ_DMA1_1, ATTR_DMA_PCIEBAR2AXIBAR_SEC_PF6, 6, 1)
185 FIELD(TZ_DMA1_1, ATTR_DMA_PCIEBAR2AXIBAR_SEC_PF5, 5, 1)
186 FIELD(TZ_DMA1_1, ATTR_DMA_PCIEBAR2AXIBAR_SEC_PF4, 4, 1)
187 FIELD(TZ_DMA1_1, ATTR_DMA_PCIEBAR2AXIBAR_SEC_PF3, 3, 1)
188 FIELD(TZ_DMA1_1, ATTR_DMA_PCIEBAR2AXIBAR_SEC_PF2, 2, 1)
189 FIELD(TZ_DMA1_1, ATTR_DMA_PCIEBAR2AXIBAR_SEC_PF1, 1, 1)
190 FIELD(TZ_DMA1_1, ATTR_DMA_PCIEBAR2AXIBAR_SEC_PF0, 0, 1)
191REG32(TZ_DMA1_2, 0x11c)
192 FIELD(TZ_DMA1_2, ATTR_DMA_SEC_VF_PF15, 31, 1)
193 FIELD(TZ_DMA1_2, ATTR_DMA_SEC_VF_PF14, 30, 1)
194 FIELD(TZ_DMA1_2, ATTR_DMA_SEC_VF_PF13, 29, 1)
195 FIELD(TZ_DMA1_2, ATTR_DMA_SEC_VF_PF12, 28, 1)
196 FIELD(TZ_DMA1_2, ATTR_DMA_SEC_VF_PF11, 27, 1)
197 FIELD(TZ_DMA1_2, ATTR_DMA_SEC_VF_PF10, 26, 1)
198 FIELD(TZ_DMA1_2, ATTR_DMA_SEC_VF_PF9, 25, 1)
199 FIELD(TZ_DMA1_2, ATTR_DMA_SEC_VF_PF8, 24, 1)
200 FIELD(TZ_DMA1_2, ATTR_DMA_SEC_VF_PF7, 23, 1)
201 FIELD(TZ_DMA1_2, ATTR_DMA_SEC_VF_PF6, 22, 1)
202 FIELD(TZ_DMA1_2, ATTR_DMA_SEC_VF_PF5, 21, 1)
203 FIELD(TZ_DMA1_2, ATTR_DMA_SEC_VF_PF4, 20, 1)
204 FIELD(TZ_DMA1_2, ATTR_DMA_SEC_VF_PF3, 19, 1)
205 FIELD(TZ_DMA1_2, ATTR_DMA_SEC_VF_PF2, 18, 1)
206 FIELD(TZ_DMA1_2, ATTR_DMA_SEC_VF_PF1, 17, 1)
207 FIELD(TZ_DMA1_2, ATTR_DMA_SEC_VF_PF0, 16, 1)
208 FIELD(TZ_DMA1_2, ATTR_DMA_SEC_PF15, 15, 1)
209 FIELD(TZ_DMA1_2, ATTR_DMA_SEC_PF14, 14, 1)
210 FIELD(TZ_DMA1_2, ATTR_DMA_SEC_PF13, 13, 1)
211 FIELD(TZ_DMA1_2, ATTR_DMA_SEC_PF12, 12, 1)
212 FIELD(TZ_DMA1_2, ATTR_DMA_SEC_PF11, 11, 1)
213 FIELD(TZ_DMA1_2, ATTR_DMA_SEC_PF10, 10, 1)
214 FIELD(TZ_DMA1_2, ATTR_DMA_SEC_PF9, 9, 1)
215 FIELD(TZ_DMA1_2, ATTR_DMA_SEC_PF8, 8, 1)
216 FIELD(TZ_DMA1_2, ATTR_DMA_SEC_PF7, 7, 1)
217 FIELD(TZ_DMA1_2, ATTR_DMA_SEC_PF6, 6, 1)
218 FIELD(TZ_DMA1_2, ATTR_DMA_SEC_PF5, 5, 1)
219 FIELD(TZ_DMA1_2, ATTR_DMA_SEC_PF4, 4, 1)
220 FIELD(TZ_DMA1_2, ATTR_DMA_SEC_PF3, 3, 1)
221 FIELD(TZ_DMA1_2, ATTR_DMA_SEC_PF2, 2, 1)
222 FIELD(TZ_DMA1_2, ATTR_DMA_SEC_PF1, 1, 1)
223 FIELD(TZ_DMA1_2, ATTR_DMA_SEC_PF0, 0, 1)
224REG32(TZ_CPI0, 0x120)
225 FIELD(TZ_CPI0, PORT_CFG, 1, 1)
226 FIELD(TZ_CPI0, PORT_EN, 0, 1)
227REG32(TZ_CPI1, 0x124)
228 FIELD(TZ_CPI1, PORT_CFG, 1, 1)
229 FIELD(TZ_CPI1, PORT_EN, 0, 1)
230REG32(TZ_CRX, 0x128)
231 FIELD(TZ_CRX, CFG, 0, 1)
232REG32(TZ_SLCR, 0x12c)
233 FIELD(TZ_SLCR, CFG, 0, 1)
234REG32(TZ_ADDRREMAP, 0x130)
235 FIELD(TZ_ADDRREMAP, CFG, 0, 1)
236REG32(TZ_MCAP0, 0x140)
237 FIELD(TZ_MCAP0, OVERRIDE_VAL, 1, 1)
238 FIELD(TZ_MCAP0, OVERRIDE_EN, 0, 1)
239REG32(TZ_MCAP1, 0x144)
240 FIELD(TZ_MCAP1, OVERRIDE_VAL, 1, 1)
241 FIELD(TZ_MCAP1, OVERRIDE_EN, 0, 1)
242REG32(PCIE0_SMID_EN, 0x200)
243 FIELD(PCIE0_SMID_EN, SELECT_ENABLE, 10, 10)
244 FIELD(PCIE0_SMID_EN, BASE, 0, 10)
245REG32(PCIE0_SMID_CFG0, 0x204)
246 FIELD(PCIE0_SMID_CFG0, BDF_BIT_SEL_7, 28, 4)
247 FIELD(PCIE0_SMID_CFG0, BDF_BIT_SEL_6, 24, 4)
248 FIELD(PCIE0_SMID_CFG0, BDF_BIT_SEL_5, 20, 4)
249 FIELD(PCIE0_SMID_CFG0, BDF_BIT_SEL_4, 16, 4)
250 FIELD(PCIE0_SMID_CFG0, BDF_BIT_SEL_3, 12, 4)
251 FIELD(PCIE0_SMID_CFG0, BDF_BIT_SEL_2, 8, 4)
252 FIELD(PCIE0_SMID_CFG0, BDF_BIT_SEL_1, 4, 4)
253 FIELD(PCIE0_SMID_CFG0, BDF_BIT_SEL_0, 0, 4)
254REG32(PCIE0_SMID_CFG1, 0x208)
255 FIELD(PCIE0_SMID_CFG1, BDF_BIT_SEL_9, 4, 4)
256 FIELD(PCIE0_SMID_CFG1, BDF_BIT_SEL_8, 0, 4)
257REG32(PCIE1_SMID_EN, 0x20c)
258 FIELD(PCIE1_SMID_EN, SELECT_ENABLE, 10, 10)
259 FIELD(PCIE1_SMID_EN, BASE, 0, 10)
260REG32(PCIE1_SMID_CFG0, 0x210)
261 FIELD(PCIE1_SMID_CFG0, BDF_BIT_SEL_7, 28, 4)
262 FIELD(PCIE1_SMID_CFG0, BDF_BIT_SEL_6, 24, 4)
263 FIELD(PCIE1_SMID_CFG0, BDF_BIT_SEL_5, 20, 4)
264 FIELD(PCIE1_SMID_CFG0, BDF_BIT_SEL_4, 16, 4)
265 FIELD(PCIE1_SMID_CFG0, BDF_BIT_SEL_3, 12, 4)
266 FIELD(PCIE1_SMID_CFG0, BDF_BIT_SEL_2, 8, 4)
267 FIELD(PCIE1_SMID_CFG0, BDF_BIT_SEL_1, 4, 4)
268 FIELD(PCIE1_SMID_CFG0, BDF_BIT_SEL_0, 0, 4)
269REG32(PCIE1_SMID_CFG1, 0x214)
270 FIELD(PCIE1_SMID_CFG1, BDF_BIT_SEL_9, 4, 4)
271 FIELD(PCIE1_SMID_CFG1, BDF_BIT_SEL_8, 0, 4)
272REG32(PCIE0_FUNC_NUM, 0x218)
273 FIELD(PCIE0_FUNC_NUM, EN, 24, 1)
274 FIELD(PCIE0_FUNC_NUM, DBG, 12, 12)
275 FIELD(PCIE0_FUNC_NUM, PS, 0, 12)
276REG32(PCIE1_FUNC_NUM, 0x21c)
277 FIELD(PCIE1_FUNC_NUM, EN, 24, 1)
278 FIELD(PCIE1_FUNC_NUM, DBG, 12, 12)
279 FIELD(PCIE1_FUNC_NUM, PS, 0, 12)
280REG32(CMN_SMID, 0x220)
281 FIELD(CMN_SMID, BASE, 0, 10)
282REG32(OD_MBIST_TRIGGER, 0x420)
283 FIELD(OD_MBIST_TRIGGER, CPM5_INT_WRAP_BOT, 18, 1)
284 FIELD(OD_MBIST_TRIGGER, CPM5_CMN_HNF_1, 17, 1)
285 FIELD(OD_MBIST_TRIGGER, CPM5_CMN_HNF_0, 16, 1)
286 FIELD(OD_MBIST_TRIGGER, CPM5_CMN_CXRH_1, 15, 1)
287 FIELD(OD_MBIST_TRIGGER, CPM5_CMN_CXRH_0, 14, 1)
288 FIELD(OD_MBIST_TRIGGER, CPM5_PCIE_PSB1_1, 13, 1)
289 FIELD(OD_MBIST_TRIGGER, CPM5_PCIE_PSB1_0, 12, 1)
290 FIELD(OD_MBIST_TRIGGER, CPM5_PCIE_1, 11, 1)
291 FIELD(OD_MBIST_TRIGGER, CPM5_PCIE_PSB0_1, 10, 1)
292 FIELD(OD_MBIST_TRIGGER, CPM5_PCIE_PSB0_0, 9, 1)
293 FIELD(OD_MBIST_TRIGGER, CPM5_PCIE_0, 8, 1)
294 FIELD(OD_MBIST_TRIGGER, CPM5_DMA1_2, 7, 1)
295 FIELD(OD_MBIST_TRIGGER, CPM5_DMA1_1, 6, 1)
296 FIELD(OD_MBIST_TRIGGER, CPM5_DMA1_0, 5, 1)
297 FIELD(OD_MBIST_TRIGGER, CPM5_DMA0_2, 4, 1)
298 FIELD(OD_MBIST_TRIGGER, CPM5_DMA0_1, 3, 1)
299 FIELD(OD_MBIST_TRIGGER, CPM5_DMA0_0, 2, 1)
300 FIELD(OD_MBIST_TRIGGER, CPM5_L2_1, 1, 1)
301 FIELD(OD_MBIST_TRIGGER, CPM5_L2_0, 0, 1)
302REG32(OD_MBIST_DONE, 0x42c)
303 FIELD(OD_MBIST_DONE, CPM5_INT_WRAP_BOT, 18, 1)
304 FIELD(OD_MBIST_DONE, CPM5_CMN_HNF_1, 17, 1)
305 FIELD(OD_MBIST_DONE, CPM5_CMN_HNF_0, 16, 1)
306 FIELD(OD_MBIST_DONE, CPM5_CMN_CXRH_1, 15, 1)
307 FIELD(OD_MBIST_DONE, CPM5_CMN_CXRH_0, 14, 1)
308 FIELD(OD_MBIST_DONE, CPM5_PCIE_PSB1_1, 13, 1)
309 FIELD(OD_MBIST_DONE, CPM5_PCIE_PSB1_0, 12, 1)
310 FIELD(OD_MBIST_DONE, CPM5_PCIE_1, 11, 1)
311 FIELD(OD_MBIST_DONE, CPM5_PCIE_PSB0_1, 10, 1)
312 FIELD(OD_MBIST_DONE, CPM5_PCIE_PSB0_0, 9, 1)
313 FIELD(OD_MBIST_DONE, CPM5_PCIE_0, 8, 1)
314 FIELD(OD_MBIST_DONE, CPM5_DMA1_2, 7, 1)
315 FIELD(OD_MBIST_DONE, CPM5_DMA1_1, 6, 1)
316 FIELD(OD_MBIST_DONE, CPM5_DMA1_0, 5, 1)
317 FIELD(OD_MBIST_DONE, CPM5_DMA0_2, 4, 1)
318 FIELD(OD_MBIST_DONE, CPM5_DMA0_1, 3, 1)
319 FIELD(OD_MBIST_DONE, CPM5_DMA0_0, 2, 1)
320 FIELD(OD_MBIST_DONE, CPM5_L2_1, 1, 1)
321 FIELD(OD_MBIST_DONE, CPM5_L2_0, 0, 1)
322REG32(OD_MBIST_PASSOUT, 0x430)
323 FIELD(OD_MBIST_PASSOUT, CPM5_INT_WRAP_BOT, 18, 1)
324 FIELD(OD_MBIST_PASSOUT, CPM5_CMN_HNF_1, 17, 1)
325 FIELD(OD_MBIST_PASSOUT, CPM5_CMN_HNF_0, 16, 1)
326 FIELD(OD_MBIST_PASSOUT, CPM5_CMN_CXRH_1, 15, 1)
327 FIELD(OD_MBIST_PASSOUT, CPM5_CMN_CXRH_0, 14, 1)
328 FIELD(OD_MBIST_PASSOUT, CPM5_PCIE_PSB1_1, 13, 1)
329 FIELD(OD_MBIST_PASSOUT, CPM5_PCIE_PSB1_0, 12, 1)
330 FIELD(OD_MBIST_PASSOUT, CPM5_PCIE_1, 11, 1)
331 FIELD(OD_MBIST_PASSOUT, CPM5_PCIE_PSB0_1, 10, 1)
332 FIELD(OD_MBIST_PASSOUT, CPM5_PCIE_PSB0_0, 9, 1)
333 FIELD(OD_MBIST_PASSOUT, CPM5_PCIE_0, 8, 1)
334 FIELD(OD_MBIST_PASSOUT, CPM5_DMA1_2, 7, 1)
335 FIELD(OD_MBIST_PASSOUT, CPM5_DMA1_1, 6, 1)
336 FIELD(OD_MBIST_PASSOUT, CPM5_DMA1_0, 5, 1)
337 FIELD(OD_MBIST_PASSOUT, CPM5_DMA0_2, 4, 1)
338 FIELD(OD_MBIST_PASSOUT, CPM5_DMA0_1, 3, 1)
339 FIELD(OD_MBIST_PASSOUT, CPM5_DMA0_0, 2, 1)
340 FIELD(OD_MBIST_PASSOUT, CPM5_L2_1, 1, 1)
341 FIELD(OD_MBIST_PASSOUT, CPM5_L2_0, 0, 1)
342
343#define CPM5_SLCR_SECURE_R_MAX (R_OD_MBIST_PASSOUT + 1)
344
345typedef struct CPM5_SLCR_SECURE {
346 SysBusDevice parent_obj;
347 MemoryRegion iomem;
348 qemu_irq irq_ir;
349
350 uint32_t regs[CPM5_SLCR_SECURE_R_MAX];
351 RegisterInfo regs_info[CPM5_SLCR_SECURE_R_MAX];
352} CPM5_SLCR_SECURE;
353
354static void ir_update_irq(CPM5_SLCR_SECURE *s)
355{
356 bool pending = s->regs[R_IR_STATUS] & ~s->regs[R_IR_MASK];
357 qemu_set_irq(s->irq_ir, pending);
358}
359
360static void ir_status_postw(RegisterInfo *reg, uint64_t val64)
361{
362 CPM5_SLCR_SECURE *s = XILINX_CPM5_SLCR_SECURE(reg->opaque);
363 ir_update_irq(s);
364}
365
366static uint64_t ir_enable_prew(RegisterInfo *reg, uint64_t val64)
367{
368 CPM5_SLCR_SECURE *s = XILINX_CPM5_SLCR_SECURE(reg->opaque);
369 uint32_t val = val64;
370
371 s->regs[R_IR_MASK] &= ~val;
372 ir_update_irq(s);
373 return 0;
374}
375
376static uint64_t ir_disable_prew(RegisterInfo *reg, uint64_t val64)
377{
378 CPM5_SLCR_SECURE *s = XILINX_CPM5_SLCR_SECURE(reg->opaque);
379 uint32_t val = val64;
380
381 s->regs[R_IR_MASK] |= val;
382 ir_update_irq(s);
383 return 0;
384}
385
386static void od_mbist_trigger_postw(RegisterInfo *reg, uint64_t val64)
387{
388 CPM5_SLCR_SECURE *s = XILINX_CPM5_SLCR_SECURE(reg->opaque);
389 uint32_t val = val64;
390
391 s->regs[R_OD_MBIST_DONE] |= val;
392 s->regs[R_OD_MBIST_PASSOUT] |= val;
393}
394
395static const RegisterAccessInfo cpm5_slcr_secure_regs_info[] = {
396 { .name = "WPROTS", .addr = A_WPROTS,
397 .reset = 0x1,
398 },{ .name = "WPROTP", .addr = A_WPROTP,
399 .reset = 0x1,
400 },{ .name = "TZPROT", .addr = A_TZPROT,
401 },{ .name = "REG_CTRL", .addr = A_REG_CTRL,
402 .rsvd = 0xfffffffe,
403 .ro = 0xfffffffe,
404 },{ .name = "IR_STATUS", .addr = A_IR_STATUS,
405 .rsvd = 0xfffffffe,
406 .ro = 0xfffffffe,
407 .w1c = 0x1,
408 .post_write = ir_status_postw,
409 },{ .name = "IR_MASK", .addr = A_IR_MASK,
410 .reset = 0x1,
411 .rsvd = 0xfffffffe,
412 .ro = 0xffffffff,
413 },{ .name = "IR_ENABLE", .addr = A_IR_ENABLE,
414 .rsvd = 0xfffffffe,
415 .ro = 0xfffffffe,
416 .pre_write = ir_enable_prew,
417 },{ .name = "IR_DISABLE", .addr = A_IR_DISABLE,
418 .rsvd = 0xfffffffe,
419 .ro = 0xfffffffe,
420 .pre_write = ir_disable_prew,
421 },{ .name = "TZ_PCIE0", .addr = A_TZ_PCIE0,
422 .reset = 0x3,
423 .rsvd = 0xfffffffc,
424 .ro = 0xfffffffc,
425 },{ .name = "TZ_PCIE1", .addr = A_TZ_PCIE1,
426 .reset = 0x3,
427 .rsvd = 0xfffffffc,
428 .ro = 0xfffffffc,
429 },{ .name = "TZ_DMA0_0", .addr = A_TZ_DMA0_0,
430 .reset = 0xfff,
431 .rsvd = 0xfffff000,
432 .ro = 0xfffff000,
433 },{ .name = "TZ_DMA0_1", .addr = A_TZ_DMA0_1,
434 .reset = 0xffffffff,
435 },{ .name = "TZ_DMA0_2", .addr = A_TZ_DMA0_2,
436 .reset = 0xffffffff,
437 },{ .name = "TZ_DMA1_0", .addr = A_TZ_DMA1_0,
438 .reset = 0xfff,
439 .rsvd = 0xfffff000,
440 .ro = 0xfffff000,
441 },{ .name = "TZ_DMA1_1", .addr = A_TZ_DMA1_1,
442 .reset = 0xffffffff,
443 },{ .name = "TZ_DMA1_2", .addr = A_TZ_DMA1_2,
444 .reset = 0xffffffff,
445 },{ .name = "TZ_CPI0", .addr = A_TZ_CPI0,
446 .reset = 0x3,
447 .rsvd = 0xfffffffc,
448 .ro = 0xfffffffc,
449 },{ .name = "TZ_CPI1", .addr = A_TZ_CPI1,
450 .reset = 0x3,
451 .rsvd = 0xfffffffc,
452 .ro = 0xfffffffc,
453 },{ .name = "TZ_CRX", .addr = A_TZ_CRX,
454 .reset = 0x1,
455 .rsvd = 0xfffffffe,
456 .ro = 0xfffffffe,
457 },{ .name = "TZ_SLCR", .addr = A_TZ_SLCR,
458 .reset = 0x1,
459 .rsvd = 0xfffffffe,
460 .ro = 0xfffffffe,
461 },{ .name = "TZ_ADDRREMAP", .addr = A_TZ_ADDRREMAP,
462 .reset = 0x1,
463 .rsvd = 0xfffffffe,
464 .ro = 0xfffffffe,
465 },{ .name = "TZ_MCAP0", .addr = A_TZ_MCAP0,
466 .reset = 0x3,
467 .rsvd = 0xfffffffc,
468 .ro = 0xfffffffc,
469 },{ .name = "TZ_MCAP1", .addr = A_TZ_MCAP1,
470 .reset = 0x3,
471 .rsvd = 0xfffffffc,
472 .ro = 0xfffffffc,
473 },{ .name = "PCIE0_SMID_EN", .addr = A_PCIE0_SMID_EN,
474 .reset = 0xffc00,
475 .rsvd = 0xfff00000,
476 .ro = 0xfff00000,
477 },{ .name = "PCIE0_SMID_CFG0", .addr = A_PCIE0_SMID_CFG0,
478 .reset = 0x76543210,
479 },{ .name = "PCIE0_SMID_CFG1", .addr = A_PCIE0_SMID_CFG1,
480 .reset = 0x98,
481 .rsvd = 0xffffff00,
482 .ro = 0xffffff00,
483 },{ .name = "PCIE1_SMID_EN", .addr = A_PCIE1_SMID_EN,
484 .reset = 0xffc00,
485 .rsvd = 0xfff00000,
486 .ro = 0xfff00000,
487 },{ .name = "PCIE1_SMID_CFG0", .addr = A_PCIE1_SMID_CFG0,
488 .reset = 0x76543210,
489 },{ .name = "PCIE1_SMID_CFG1", .addr = A_PCIE1_SMID_CFG1,
490 .reset = 0x98,
491 .rsvd = 0xffffff00,
492 .ro = 0xffffff00,
493 },{ .name = "PCIE0_FUNC_NUM", .addr = A_PCIE0_FUNC_NUM,
494 .rsvd = 0xfe000000,
495 .ro = 0xfe000000,
496 },{ .name = "PCIE1_FUNC_NUM", .addr = A_PCIE1_FUNC_NUM,
497 .rsvd = 0xfe000000,
498 .ro = 0xfe000000,
499 },{ .name = "CMN_SMID", .addr = A_CMN_SMID,
500 },{ .name = "OD_MBIST_TRIGGER", .addr = A_OD_MBIST_TRIGGER,
501 .rsvd = 0xfff80000,
502 .ro = 0xfff80000,
503 .post_write = od_mbist_trigger_postw,
504 },{ .name = "OD_MBIST_DONE", .addr = A_OD_MBIST_DONE,
505 .rsvd = 0xfff80000,
506 .ro = 0xffffffff,
507 },{ .name = "OD_MBIST_PASSOUT", .addr = A_OD_MBIST_PASSOUT,
508 .rsvd = 0xfff80000,
509 .ro = 0xffffffff,
510 }
511};
512
513static void cpm5_slcr_secure_reset_enter(Object *obj, ResetType type)
514{
515 CPM5_SLCR_SECURE *s = XILINX_CPM5_SLCR_SECURE(obj);
516 unsigned int i;
517
518 for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
519 register_reset(&s->regs_info[i]);
520 }
521}
522
523static void cpm5_slcr_secure_reset_hold(Object *obj)
524{
525 CPM5_SLCR_SECURE *s = XILINX_CPM5_SLCR_SECURE(obj);
526
527 ir_update_irq(s);
528}
529
530static const MemoryRegionOps cpm5_slcr_secure_ops = {
531 .read = register_read_memory,
532 .write = register_write_memory,
533 .endianness = DEVICE_LITTLE_ENDIAN,
534 .valid = {
535 .min_access_size = 4,
536 .max_access_size = 4,
537 },
538};
539
540static void cpm5_slcr_secure_realize(DeviceState *dev, Error **errp)
541{
542
543}
544
545static void cpm5_slcr_secure_init(Object *obj)
546{
547 CPM5_SLCR_SECURE *s = XILINX_CPM5_SLCR_SECURE(obj);
548 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
549 RegisterInfoArray *reg_array;
550
551 memory_region_init(&s->iomem, obj, TYPE_XILINX_CPM5_SLCR_SECURE, CPM5_SLCR_SECURE_R_MAX * 4);
552 reg_array =
553 register_init_block32(DEVICE(obj), cpm5_slcr_secure_regs_info,
554 ARRAY_SIZE(cpm5_slcr_secure_regs_info),
555 s->regs_info, s->regs,
556 &cpm5_slcr_secure_ops,
557 XILINX_CPM5_SLCR_SECURE_ERR_DEBUG,
558 CPM5_SLCR_SECURE_R_MAX * 4);
559 memory_region_add_subregion(&s->iomem,
560 0x0,
561 ®_array->mem);
562 sysbus_init_mmio(sbd, &s->iomem);
563 sysbus_init_irq(sbd, &s->irq_ir);
564}
565
566static const VMStateDescription vmstate_cpm5_slcr_secure = {
567 .name = TYPE_XILINX_CPM5_SLCR_SECURE,
568 .version_id = 1,
569 .minimum_version_id = 1,
570 .fields = (VMStateField[]) {
571 VMSTATE_UINT32_ARRAY(regs, CPM5_SLCR_SECURE, CPM5_SLCR_SECURE_R_MAX),
572 VMSTATE_END_OF_LIST(),
573 }
574};
575
576static void cpm5_slcr_secure_class_init(ObjectClass *klass, void *data)
577{
578 ResettableClass *rc = RESETTABLE_CLASS(klass);
579 DeviceClass *dc = DEVICE_CLASS(klass);
580
581 dc->realize = cpm5_slcr_secure_realize;
582 dc->vmsd = &vmstate_cpm5_slcr_secure;
583 rc->phases.enter = cpm5_slcr_secure_reset_enter;
584 rc->phases.hold = cpm5_slcr_secure_reset_hold;
585}
586
587static const TypeInfo cpm5_slcr_secure_info = {
588 .name = TYPE_XILINX_CPM5_SLCR_SECURE,
589 .parent = TYPE_SYS_BUS_DEVICE,
590 .instance_size = sizeof(CPM5_SLCR_SECURE),
591 .class_init = cpm5_slcr_secure_class_init,
592 .instance_init = cpm5_slcr_secure_init,
593};
594
595static void cpm5_slcr_secure_register_types(void)
596{
597 type_register_static(&cpm5_slcr_secure_info);
598}
599
600type_init(cpm5_slcr_secure_register_types)
601
