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27#include "qemu/osdep.h"
28#include "hw/sysbus.h"
29#include "hw/register.h"
30#include "qemu/bitops.h"
31#include "qemu/log.h"
32#include "migration/vmstate.h"
33#include "hw/irq.h"
34#include "hw/qdev-properties.h"
35
36#ifndef XILINX_PSX_RPU_CLUSTER_ERR_DEBUG
37#define XILINX_PSX_RPU_CLUSTER_ERR_DEBUG 0
38#endif
39
40#define TYPE_XILINX_PSX_RPU_CLUSTER "xlnx.psx_rpu_cluster_2.0"
41
42#define XILINX_PSX_RPU_CLUSTER(obj) \
43 OBJECT_CHECK(PSX_RPU_CLUSTER, (obj), TYPE_XILINX_PSX_RPU_CLUSTER)
44
45REG32(CLUSTER_CFG, 0x0)
46 FIELD(CLUSTER_CFG, RAMPROTEN, 12, 1)
47 FIELD(CLUSTER_CFG, CLUSTERUTID_BIT1, 9, 1)
48 FIELD(CLUSTER_CFG, CLUSTERUTID_BIT0, 8, 1)
49 FIELD(CLUSTER_CFG, SLSPLIT, 0, 1)
50REG32(CLUSTER_AXIS, 0x10)
51 FIELD(CLUSTER_AXIS, TCM_BASE, 24, 8)
52REG32(CLUSTER_PERIPH, 0x14)
53 FIELD(CLUSTER_PERIPH, BASE, 21, 11)
54REG32(CLUSTER_LLPP, 0x1c)
55 FIELD(CLUSTER_LLPP, BASE, 12, 20)
56 FIELD(CLUSTER_LLPP, SIZE, 0, 4)
57REG32(CLUSTER_DCLSCOMPIN_LO, 0x30)
58 FIELD(CLUSTER_DCLSCOMPIN_LO, COMPIN, 0, 28)
59REG32(CLUSTER_DCLSCOMPIN_HI, 0x38)
60 FIELD(CLUSTER_DCLSCOMPIN_HI, COMPIN, 4, 6)
61REG32(CLUSTER_INTR_0, 0x40)
62REG32(CLUSTER_INTR_1, 0x44)
63REG32(CLUSTER_INTR_2, 0x48)
64REG32(CLUSTER_INTR_3, 0x4c)
65REG32(CLUSTER_INTR_4, 0x50)
66REG32(CLUSTER_INTR_MASK_0, 0x54)
67REG32(CLUSTER_INTR_MASK_1, 0x58)
68REG32(CLUSTER_INTR_MASK_2, 0x5c)
69REG32(CLUSTER_INTR_MASK_3, 0x60)
70REG32(CLUSTER_INTR_MASK_4, 0x64)
71REG32(CLUSTER_CCF_VAL, 0x68)
72 FIELD(CLUSTER_CCF_VAL, TEST_MBIST_MODE, 7, 1)
73 FIELD(CLUSTER_CCF_VAL, TEST_SCAN_MODE_LP, 6, 1)
74 FIELD(CLUSTER_CCF_VAL, TEST_SCAN_MODE, 5, 1)
75 FIELD(CLUSTER_CCF_VAL, ISO, 4, 1)
76 FIELD(CLUSTER_CCF_VAL, PGE, 3, 1)
77 FIELD(CLUSTER_CCF_VAL, R50_DBG_RST, 2, 1)
78 FIELD(CLUSTER_CCF_VAL, R50_RST, 1, 1)
79 FIELD(CLUSTER_CCF_VAL, PGE_RST, 0, 1)
80REG32(CLUSTER_CCF_MASK, 0x6c)
81 FIELD(CLUSTER_CCF_MASK, TEST_MBIST_MODE, 7, 1)
82 FIELD(CLUSTER_CCF_MASK, TEST_SCAN_MODE_LP, 6, 1)
83 FIELD(CLUSTER_CCF_MASK, TEST_SCAN_MODE, 5, 1)
84 FIELD(CLUSTER_CCF_MASK, ISO, 4, 1)
85 FIELD(CLUSTER_CCF_MASK, PGE, 3, 1)
86 FIELD(CLUSTER_CCF_MASK, R50_DBG_RST, 2, 1)
87 FIELD(CLUSTER_CCF_MASK, R50_RST, 1, 1)
88 FIELD(CLUSTER_CCF_MASK, PGE_RST, 0, 1)
89REG32(CLUSTER_SAFETY_CHK, 0x70)
90REG32(CLUSTER_DCLSCOMPOUT_LO_STATUS, 0x80)
91 FIELD(CLUSTER_DCLSCOMPOUT_LO_STATUS, VAL_27, 27, 1)
92 FIELD(CLUSTER_DCLSCOMPOUT_LO_STATUS, VAL_26, 26, 1)
93 FIELD(CLUSTER_DCLSCOMPOUT_LO_STATUS, VAL_25, 25, 1)
94 FIELD(CLUSTER_DCLSCOMPOUT_LO_STATUS, VAL_24, 24, 1)
95 FIELD(CLUSTER_DCLSCOMPOUT_LO_STATUS, VAL_23, 23, 1)
96 FIELD(CLUSTER_DCLSCOMPOUT_LO_STATUS, VAL_22, 22, 1)
97 FIELD(CLUSTER_DCLSCOMPOUT_LO_STATUS, VAL_21, 21, 1)
98 FIELD(CLUSTER_DCLSCOMPOUT_LO_STATUS, VAL_20, 20, 1)
99 FIELD(CLUSTER_DCLSCOMPOUT_LO_STATUS, VAL_19, 19, 1)
100 FIELD(CLUSTER_DCLSCOMPOUT_LO_STATUS, VAL_18, 18, 1)
101 FIELD(CLUSTER_DCLSCOMPOUT_LO_STATUS, VAL_17, 17, 1)
102 FIELD(CLUSTER_DCLSCOMPOUT_LO_STATUS, VAL_16, 16, 1)
103 FIELD(CLUSTER_DCLSCOMPOUT_LO_STATUS, VAL_15, 15, 1)
104 FIELD(CLUSTER_DCLSCOMPOUT_LO_STATUS, VAL_14, 14, 1)
105 FIELD(CLUSTER_DCLSCOMPOUT_LO_STATUS, VAL_13, 13, 1)
106 FIELD(CLUSTER_DCLSCOMPOUT_LO_STATUS, VAL_12, 12, 1)
107 FIELD(CLUSTER_DCLSCOMPOUT_LO_STATUS, VAL_11, 11, 1)
108 FIELD(CLUSTER_DCLSCOMPOUT_LO_STATUS, VAL_10, 10, 1)
109 FIELD(CLUSTER_DCLSCOMPOUT_LO_STATUS, VAL_9, 9, 1)
110 FIELD(CLUSTER_DCLSCOMPOUT_LO_STATUS, VAL_8, 8, 1)
111 FIELD(CLUSTER_DCLSCOMPOUT_LO_STATUS, VAL_7, 7, 1)
112 FIELD(CLUSTER_DCLSCOMPOUT_LO_STATUS, VAL_6, 6, 1)
113 FIELD(CLUSTER_DCLSCOMPOUT_LO_STATUS, VAL_5, 5, 1)
114 FIELD(CLUSTER_DCLSCOMPOUT_LO_STATUS, VAL_4, 4, 1)
115 FIELD(CLUSTER_DCLSCOMPOUT_LO_STATUS, VAL_3, 3, 1)
116 FIELD(CLUSTER_DCLSCOMPOUT_LO_STATUS, VAL_2, 2, 1)
117 FIELD(CLUSTER_DCLSCOMPOUT_LO_STATUS, VAL_1, 1, 1)
118 FIELD(CLUSTER_DCLSCOMPOUT_LO_STATUS, VAL_0, 0, 1)
119REG32(CLUSTER_DCLSCOMPOUT_LO_MASK, 0x84)
120 FIELD(CLUSTER_DCLSCOMPOUT_LO_MASK, VAL_27, 27, 1)
121 FIELD(CLUSTER_DCLSCOMPOUT_LO_MASK, VAL_26, 26, 1)
122 FIELD(CLUSTER_DCLSCOMPOUT_LO_MASK, VAL_25, 25, 1)
123 FIELD(CLUSTER_DCLSCOMPOUT_LO_MASK, VAL_24, 24, 1)
124 FIELD(CLUSTER_DCLSCOMPOUT_LO_MASK, VAL_23, 23, 1)
125 FIELD(CLUSTER_DCLSCOMPOUT_LO_MASK, VAL_22, 22, 1)
126 FIELD(CLUSTER_DCLSCOMPOUT_LO_MASK, VAL_21, 21, 1)
127 FIELD(CLUSTER_DCLSCOMPOUT_LO_MASK, VAL_20, 20, 1)
128 FIELD(CLUSTER_DCLSCOMPOUT_LO_MASK, VAL_19, 19, 1)
129 FIELD(CLUSTER_DCLSCOMPOUT_LO_MASK, VAL_18, 18, 1)
130 FIELD(CLUSTER_DCLSCOMPOUT_LO_MASK, VAL_17, 17, 1)
131 FIELD(CLUSTER_DCLSCOMPOUT_LO_MASK, VAL_16, 16, 1)
132 FIELD(CLUSTER_DCLSCOMPOUT_LO_MASK, VAL_15, 15, 1)
133 FIELD(CLUSTER_DCLSCOMPOUT_LO_MASK, VAL_14, 14, 1)
134 FIELD(CLUSTER_DCLSCOMPOUT_LO_MASK, VAL_13, 13, 1)
135 FIELD(CLUSTER_DCLSCOMPOUT_LO_MASK, VAL_12, 12, 1)
136 FIELD(CLUSTER_DCLSCOMPOUT_LO_MASK, VAL_11, 11, 1)
137 FIELD(CLUSTER_DCLSCOMPOUT_LO_MASK, VAL_10, 10, 1)
138 FIELD(CLUSTER_DCLSCOMPOUT_LO_MASK, VAL_9, 9, 1)
139 FIELD(CLUSTER_DCLSCOMPOUT_LO_MASK, VAL_8, 8, 1)
140 FIELD(CLUSTER_DCLSCOMPOUT_LO_MASK, VAL_7, 7, 1)
141 FIELD(CLUSTER_DCLSCOMPOUT_LO_MASK, VAL_6, 6, 1)
142 FIELD(CLUSTER_DCLSCOMPOUT_LO_MASK, VAL_5, 5, 1)
143 FIELD(CLUSTER_DCLSCOMPOUT_LO_MASK, VAL_4, 4, 1)
144 FIELD(CLUSTER_DCLSCOMPOUT_LO_MASK, VAL_3, 3, 1)
145 FIELD(CLUSTER_DCLSCOMPOUT_LO_MASK, VAL_2, 2, 1)
146 FIELD(CLUSTER_DCLSCOMPOUT_LO_MASK, VAL_1, 1, 1)
147 FIELD(CLUSTER_DCLSCOMPOUT_LO_MASK, VAL_0, 0, 1)
148REG32(CLUSTER_DCLSCOMPOUT_LO_EN, 0x88)
149 FIELD(CLUSTER_DCLSCOMPOUT_LO_EN, VAL_27, 27, 1)
150 FIELD(CLUSTER_DCLSCOMPOUT_LO_EN, VAL_26, 26, 1)
151 FIELD(CLUSTER_DCLSCOMPOUT_LO_EN, VAL_25, 25, 1)
152 FIELD(CLUSTER_DCLSCOMPOUT_LO_EN, VAL_24, 24, 1)
153 FIELD(CLUSTER_DCLSCOMPOUT_LO_EN, VAL_23, 23, 1)
154 FIELD(CLUSTER_DCLSCOMPOUT_LO_EN, VAL_22, 22, 1)
155 FIELD(CLUSTER_DCLSCOMPOUT_LO_EN, VAL_21, 21, 1)
156 FIELD(CLUSTER_DCLSCOMPOUT_LO_EN, VAL_20, 20, 1)
157 FIELD(CLUSTER_DCLSCOMPOUT_LO_EN, VAL_19, 19, 1)
158 FIELD(CLUSTER_DCLSCOMPOUT_LO_EN, VAL_18, 18, 1)
159 FIELD(CLUSTER_DCLSCOMPOUT_LO_EN, VAL_17, 17, 1)
160 FIELD(CLUSTER_DCLSCOMPOUT_LO_EN, VAL_16, 16, 1)
161 FIELD(CLUSTER_DCLSCOMPOUT_LO_EN, VAL_15, 15, 1)
162 FIELD(CLUSTER_DCLSCOMPOUT_LO_EN, VAL_14, 14, 1)
163 FIELD(CLUSTER_DCLSCOMPOUT_LO_EN, VAL_13, 13, 1)
164 FIELD(CLUSTER_DCLSCOMPOUT_LO_EN, VAL_12, 12, 1)
165 FIELD(CLUSTER_DCLSCOMPOUT_LO_EN, VAL_11, 11, 1)
166 FIELD(CLUSTER_DCLSCOMPOUT_LO_EN, VAL_10, 10, 1)
167 FIELD(CLUSTER_DCLSCOMPOUT_LO_EN, VAL_9, 9, 1)
168 FIELD(CLUSTER_DCLSCOMPOUT_LO_EN, VAL_8, 8, 1)
169 FIELD(CLUSTER_DCLSCOMPOUT_LO_EN, VAL_7, 7, 1)
170 FIELD(CLUSTER_DCLSCOMPOUT_LO_EN, VAL_6, 6, 1)
171 FIELD(CLUSTER_DCLSCOMPOUT_LO_EN, VAL_5, 5, 1)
172 FIELD(CLUSTER_DCLSCOMPOUT_LO_EN, VAL_4, 4, 1)
173 FIELD(CLUSTER_DCLSCOMPOUT_LO_EN, VAL_3, 3, 1)
174 FIELD(CLUSTER_DCLSCOMPOUT_LO_EN, VAL_2, 2, 1)
175 FIELD(CLUSTER_DCLSCOMPOUT_LO_EN, VAL_1, 1, 1)
176 FIELD(CLUSTER_DCLSCOMPOUT_LO_EN, VAL_0, 0, 1)
177REG32(CLUSTER_DCLSCOMPOUT_LO_DIS, 0x8c)
178 FIELD(CLUSTER_DCLSCOMPOUT_LO_DIS, VAL_27, 27, 1)
179 FIELD(CLUSTER_DCLSCOMPOUT_LO_DIS, VAL_26, 26, 1)
180 FIELD(CLUSTER_DCLSCOMPOUT_LO_DIS, VAL_25, 25, 1)
181 FIELD(CLUSTER_DCLSCOMPOUT_LO_DIS, VAL_24, 24, 1)
182 FIELD(CLUSTER_DCLSCOMPOUT_LO_DIS, VAL_23, 23, 1)
183 FIELD(CLUSTER_DCLSCOMPOUT_LO_DIS, VAL_22, 22, 1)
184 FIELD(CLUSTER_DCLSCOMPOUT_LO_DIS, VAL_21, 21, 1)
185 FIELD(CLUSTER_DCLSCOMPOUT_LO_DIS, VAL_20, 20, 1)
186 FIELD(CLUSTER_DCLSCOMPOUT_LO_DIS, VAL_19, 19, 1)
187 FIELD(CLUSTER_DCLSCOMPOUT_LO_DIS, VAL_18, 18, 1)
188 FIELD(CLUSTER_DCLSCOMPOUT_LO_DIS, VAL_17, 17, 1)
189 FIELD(CLUSTER_DCLSCOMPOUT_LO_DIS, VAL_16, 16, 1)
190 FIELD(CLUSTER_DCLSCOMPOUT_LO_DIS, VAL_15, 15, 1)
191 FIELD(CLUSTER_DCLSCOMPOUT_LO_DIS, VAL_14, 14, 1)
192 FIELD(CLUSTER_DCLSCOMPOUT_LO_DIS, VAL_13, 13, 1)
193 FIELD(CLUSTER_DCLSCOMPOUT_LO_DIS, VAL_12, 12, 1)
194 FIELD(CLUSTER_DCLSCOMPOUT_LO_DIS, VAL_11, 11, 1)
195 FIELD(CLUSTER_DCLSCOMPOUT_LO_DIS, VAL_10, 10, 1)
196 FIELD(CLUSTER_DCLSCOMPOUT_LO_DIS, VAL_9, 9, 1)
197 FIELD(CLUSTER_DCLSCOMPOUT_LO_DIS, VAL_8, 8, 1)
198 FIELD(CLUSTER_DCLSCOMPOUT_LO_DIS, VAL_7, 7, 1)
199 FIELD(CLUSTER_DCLSCOMPOUT_LO_DIS, VAL_6, 6, 1)
200 FIELD(CLUSTER_DCLSCOMPOUT_LO_DIS, VAL_5, 5, 1)
201 FIELD(CLUSTER_DCLSCOMPOUT_LO_DIS, VAL_4, 4, 1)
202 FIELD(CLUSTER_DCLSCOMPOUT_LO_DIS, VAL_3, 3, 1)
203 FIELD(CLUSTER_DCLSCOMPOUT_LO_DIS, VAL_2, 2, 1)
204 FIELD(CLUSTER_DCLSCOMPOUT_LO_DIS, VAL_1, 1, 1)
205 FIELD(CLUSTER_DCLSCOMPOUT_LO_DIS, VAL_0, 0, 1)
206REG32(CLUSTER_DCLSCOMPOUT_LO_TRIGG, 0x90)
207 FIELD(CLUSTER_DCLSCOMPOUT_LO_TRIGG, VAL_27, 27, 1)
208 FIELD(CLUSTER_DCLSCOMPOUT_LO_TRIGG, VAL_26, 26, 1)
209 FIELD(CLUSTER_DCLSCOMPOUT_LO_TRIGG, VAL_25, 25, 1)
210 FIELD(CLUSTER_DCLSCOMPOUT_LO_TRIGG, VAL_24, 24, 1)
211 FIELD(CLUSTER_DCLSCOMPOUT_LO_TRIGG, VAL_23, 23, 1)
212 FIELD(CLUSTER_DCLSCOMPOUT_LO_TRIGG, VAL_22, 22, 1)
213 FIELD(CLUSTER_DCLSCOMPOUT_LO_TRIGG, VAL_21, 21, 1)
214 FIELD(CLUSTER_DCLSCOMPOUT_LO_TRIGG, VAL_20, 20, 1)
215 FIELD(CLUSTER_DCLSCOMPOUT_LO_TRIGG, VAL_19, 19, 1)
216 FIELD(CLUSTER_DCLSCOMPOUT_LO_TRIGG, VAL_18, 18, 1)
217 FIELD(CLUSTER_DCLSCOMPOUT_LO_TRIGG, VAL_17, 17, 1)
218 FIELD(CLUSTER_DCLSCOMPOUT_LO_TRIGG, VAL_16, 16, 1)
219 FIELD(CLUSTER_DCLSCOMPOUT_LO_TRIGG, VAL_15, 15, 1)
220 FIELD(CLUSTER_DCLSCOMPOUT_LO_TRIGG, VAL_14, 14, 1)
221 FIELD(CLUSTER_DCLSCOMPOUT_LO_TRIGG, VAL_13, 13, 1)
222 FIELD(CLUSTER_DCLSCOMPOUT_LO_TRIGG, VAL_12, 12, 1)
223 FIELD(CLUSTER_DCLSCOMPOUT_LO_TRIGG, VAL_11, 11, 1)
224 FIELD(CLUSTER_DCLSCOMPOUT_LO_TRIGG, VAL_10, 10, 1)
225 FIELD(CLUSTER_DCLSCOMPOUT_LO_TRIGG, VAL_9, 9, 1)
226 FIELD(CLUSTER_DCLSCOMPOUT_LO_TRIGG, VAL_8, 8, 1)
227 FIELD(CLUSTER_DCLSCOMPOUT_LO_TRIGG, VAL_7, 7, 1)
228 FIELD(CLUSTER_DCLSCOMPOUT_LO_TRIGG, VAL_6, 6, 1)
229 FIELD(CLUSTER_DCLSCOMPOUT_LO_TRIGG, VAL_5, 5, 1)
230 FIELD(CLUSTER_DCLSCOMPOUT_LO_TRIGG, VAL_4, 4, 1)
231 FIELD(CLUSTER_DCLSCOMPOUT_LO_TRIGG, VAL_3, 3, 1)
232 FIELD(CLUSTER_DCLSCOMPOUT_LO_TRIGG, VAL_2, 2, 1)
233 FIELD(CLUSTER_DCLSCOMPOUT_LO_TRIGG, VAL_1, 1, 1)
234 FIELD(CLUSTER_DCLSCOMPOUT_LO_TRIGG, VAL_0, 0, 1)
235REG32(CLUSTER_DCLSCOMPOUT_HI_STATUS, 0x94)
236 FIELD(CLUSTER_DCLSCOMPOUT_HI_STATUS, VAL_89, 9, 1)
237 FIELD(CLUSTER_DCLSCOMPOUT_HI_STATUS, VAL_88, 8, 1)
238 FIELD(CLUSTER_DCLSCOMPOUT_HI_STATUS, VAL_87, 7, 1)
239 FIELD(CLUSTER_DCLSCOMPOUT_HI_STATUS, VAL_86, 6, 1)
240 FIELD(CLUSTER_DCLSCOMPOUT_HI_STATUS, VAL_85, 5, 1)
241 FIELD(CLUSTER_DCLSCOMPOUT_HI_STATUS, VAL_84, 4, 1)
242REG32(CLUSTER_DCLSCOMPOUT_HI_MASK, 0x98)
243 FIELD(CLUSTER_DCLSCOMPOUT_HI_MASK, VAL_89, 9, 1)
244 FIELD(CLUSTER_DCLSCOMPOUT_HI_MASK, VAL_88, 8, 1)
245 FIELD(CLUSTER_DCLSCOMPOUT_HI_MASK, VAL_87, 7, 1)
246 FIELD(CLUSTER_DCLSCOMPOUT_HI_MASK, VAL_86, 6, 1)
247 FIELD(CLUSTER_DCLSCOMPOUT_HI_MASK, VAL_85, 5, 1)
248 FIELD(CLUSTER_DCLSCOMPOUT_HI_MASK, VAL_84, 4, 1)
249REG32(CLUSTER_DCLSCOMPOUT_HI_EN, 0x9c)
250 FIELD(CLUSTER_DCLSCOMPOUT_HI_EN, VAL_89, 9, 1)
251 FIELD(CLUSTER_DCLSCOMPOUT_HI_EN, VAL_88, 8, 1)
252 FIELD(CLUSTER_DCLSCOMPOUT_HI_EN, VAL_87, 7, 1)
253 FIELD(CLUSTER_DCLSCOMPOUT_HI_EN, VAL_86, 6, 1)
254 FIELD(CLUSTER_DCLSCOMPOUT_HI_EN, VAL_85, 5, 1)
255 FIELD(CLUSTER_DCLSCOMPOUT_HI_EN, VAL_84, 4, 1)
256REG32(CLUSTER_DCLSCOMPOUT_HI_DIS, 0xa0)
257 FIELD(CLUSTER_DCLSCOMPOUT_HI_DIS, VAL_89, 9, 1)
258 FIELD(CLUSTER_DCLSCOMPOUT_HI_DIS, VAL_88, 8, 1)
259 FIELD(CLUSTER_DCLSCOMPOUT_HI_DIS, VAL_87, 7, 1)
260 FIELD(CLUSTER_DCLSCOMPOUT_HI_DIS, VAL_86, 6, 1)
261 FIELD(CLUSTER_DCLSCOMPOUT_HI_DIS, VAL_85, 5, 1)
262 FIELD(CLUSTER_DCLSCOMPOUT_HI_DIS, VAL_84, 4, 1)
263REG32(CLUSTER_DCLSCOMPOUT_HI_TRIGG, 0xa4)
264 FIELD(CLUSTER_DCLSCOMPOUT_HI_TRIGG, VAL_89, 9, 1)
265 FIELD(CLUSTER_DCLSCOMPOUT_HI_TRIGG, VAL_88, 8, 1)
266 FIELD(CLUSTER_DCLSCOMPOUT_HI_TRIGG, VAL_87, 7, 1)
267 FIELD(CLUSTER_DCLSCOMPOUT_HI_TRIGG, VAL_86, 6, 1)
268 FIELD(CLUSTER_DCLSCOMPOUT_HI_TRIGG, VAL_85, 5, 1)
269 FIELD(CLUSTER_DCLSCOMPOUT_HI_TRIGG, VAL_84, 4, 1)
270REG32(CLUSTER_MPID, 0xa8)
271 FIELD(CLUSTER_MPID, AFF2_MSB, 17, 7)
272 FIELD(CLUSTER_MPID, AFF2_BIT0, 16, 1)
273 FIELD(CLUSTER_MPID, AFF1_MSB, 9, 7)
274 FIELD(CLUSTER_MPID, AFF1_BIT0, 8, 1)
275REG32(RPU_CLUSTER_ISR, 0xb0)
276 FIELD(RPU_CLUSTER_ISR, CLUSTER_REG_PAR_MON_ERR1, 1, 1)
277 FIELD(RPU_CLUSTER_ISR, CLUSTER_REG_PAR_MON_ERR0, 0, 1)
278REG32(RPU_CLUSTER_IMR, 0xb4)
279 FIELD(RPU_CLUSTER_IMR, CLUSTER_REG_PAR_MON_ERR1, 1, 1)
280 FIELD(RPU_CLUSTER_IMR, CLUSTER_REG_PAR_MON_ERR0, 0, 1)
281REG32(RPU_CLUSTER_IEN, 0xb8)
282 FIELD(RPU_CLUSTER_IEN, CLUSTER_REG_PAR_MON_ERR1, 1, 1)
283 FIELD(RPU_CLUSTER_IEN, CLUSTER_REG_PAR_MON_ERR0, 0, 1)
284REG32(RPU_CLUSTER_IDS, 0xbc)
285 FIELD(RPU_CLUSTER_IDS, CLUSTER_REG_PAR_MON_ERR1, 1, 1)
286 FIELD(RPU_CLUSTER_IDS, CLUSTER_REG_PAR_MON_ERR0, 0, 1)
287REG32(RPU_CLUSTER_PAR_MON, 0xc0)
288 FIELD(RPU_CLUSTER_PAR_MON, CLUSTER_PAR_MON_EN, 0, 1)
289REG32(CLUSTER_INTR_5, 0xc4)
290REG32(CLUSTER_INTR_6, 0xc8)
291REG32(CLUSTER_INTR_7, 0xcc)
292REG32(CLUSTER_INTR_MASK_5, 0xd0)
293REG32(CLUSTER_INTR_MASK_6, 0xd4)
294REG32(CLUSTER_INTR_MASK_7, 0xd8)
295
296#define PSX_RPU_CLUSTER_R_MAX (R_CLUSTER_INTR_MASK_7 + 1)
297
298typedef struct PSX_RPU_CLUSTER {
299 SysBusDevice parent_obj;
300 MemoryRegion iomem;
301 qemu_irq irq_cluster_dclscompout_hi;
302 qemu_irq irq_cluster_dclscompout_lo;
303 qemu_irq irq_rpu_cluster_imr;
304 qemu_irq slsplit;
305 uint32_t axis_base;
306 MemoryRegion *tcm_mr;
307
308 uint32_t regs[PSX_RPU_CLUSTER_R_MAX];
309 RegisterInfo regs_info[PSX_RPU_CLUSTER_R_MAX];
310} PSX_RPU_CLUSTER;
311
312#define PROPAGATE_GPIO(reg, f, irq) { \
313 bool val = ARRAY_FIELD_EX32(s->regs, reg, f); \
314 qemu_set_irq(irq, val); \
315}
316
317static void cluster_dclscompout_hi_update_irq(PSX_RPU_CLUSTER *s)
318{
319 bool pending = s->regs[R_CLUSTER_DCLSCOMPOUT_HI_STATUS] &
320 ~s->regs[R_CLUSTER_DCLSCOMPOUT_HI_MASK];
321 qemu_set_irq(s->irq_cluster_dclscompout_hi, pending);
322}
323
324static void cluster_dclscompout_hi_status_postw(RegisterInfo *reg,
325 uint64_t val64)
326{
327 PSX_RPU_CLUSTER *s = XILINX_PSX_RPU_CLUSTER(reg->opaque);
328 cluster_dclscompout_hi_update_irq(s);
329}
330
331static uint64_t cluster_dclscompout_hi_en_prew(RegisterInfo *reg,
332 uint64_t val64)
333{
334 PSX_RPU_CLUSTER *s = XILINX_PSX_RPU_CLUSTER(reg->opaque);
335 uint32_t val = val64;
336
337 s->regs[R_CLUSTER_DCLSCOMPOUT_HI_MASK] &= ~val;
338 cluster_dclscompout_hi_update_irq(s);
339 return 0;
340}
341
342static uint64_t cluster_dclscompout_hi_dis_prew(RegisterInfo *reg,
343 uint64_t val64)
344{
345 PSX_RPU_CLUSTER *s = XILINX_PSX_RPU_CLUSTER(reg->opaque);
346 uint32_t val = val64;
347
348 s->regs[R_CLUSTER_DCLSCOMPOUT_HI_MASK] |= val;
349 cluster_dclscompout_hi_update_irq(s);
350 return 0;
351}
352
353static uint64_t cluster_dclscompout_hi_trigg_prew(RegisterInfo *reg,
354 uint64_t val64)
355{
356 PSX_RPU_CLUSTER *s = XILINX_PSX_RPU_CLUSTER(reg->opaque);
357 uint32_t val = val64;
358
359 s->regs[R_CLUSTER_DCLSCOMPOUT_HI_STATUS] |= val;
360 cluster_dclscompout_hi_update_irq(s);
361 return 0;
362}
363
364static void cluster_dclscompout_lo_update_irq(PSX_RPU_CLUSTER *s)
365{
366 bool pending = s->regs[R_CLUSTER_DCLSCOMPOUT_LO_STATUS] &
367 ~s->regs[R_CLUSTER_DCLSCOMPOUT_LO_MASK];
368 qemu_set_irq(s->irq_cluster_dclscompout_lo, pending);
369}
370
371static void cluster_dclscompout_lo_status_postw(RegisterInfo *reg,
372 uint64_t val64)
373{
374 PSX_RPU_CLUSTER *s = XILINX_PSX_RPU_CLUSTER(reg->opaque);
375 cluster_dclscompout_lo_update_irq(s);
376}
377
378static uint64_t cluster_dclscompout_lo_en_prew(RegisterInfo *reg,
379 uint64_t val64)
380{
381 PSX_RPU_CLUSTER *s = XILINX_PSX_RPU_CLUSTER(reg->opaque);
382 uint32_t val = val64;
383
384 s->regs[R_CLUSTER_DCLSCOMPOUT_LO_MASK] &= ~val;
385 cluster_dclscompout_lo_update_irq(s);
386 return 0;
387}
388
389static uint64_t cluster_dclscompout_lo_dis_prew(RegisterInfo *reg,
390 uint64_t val64)
391{
392 PSX_RPU_CLUSTER *s = XILINX_PSX_RPU_CLUSTER(reg->opaque);
393 uint32_t val = val64;
394
395 s->regs[R_CLUSTER_DCLSCOMPOUT_LO_MASK] |= val;
396 cluster_dclscompout_lo_update_irq(s);
397 return 0;
398}
399
400static uint64_t cluster_dclscompout_lo_trigg_prew(RegisterInfo *reg,
401 uint64_t val64)
402{
403 PSX_RPU_CLUSTER *s = XILINX_PSX_RPU_CLUSTER(reg->opaque);
404 uint32_t val = val64;
405
406 s->regs[R_CLUSTER_DCLSCOMPOUT_LO_STATUS] |= val;
407 cluster_dclscompout_lo_update_irq(s);
408 return 0;
409}
410
411static void rpu_cluster_imr_update_irq(PSX_RPU_CLUSTER *s)
412{
413 bool pending = s->regs[R_RPU_CLUSTER_ISR] & ~s->regs[R_RPU_CLUSTER_IMR];
414 qemu_set_irq(s->irq_rpu_cluster_imr, pending);
415}
416
417static void rpu_cluster_isr_postw(RegisterInfo *reg, uint64_t val64)
418{
419 PSX_RPU_CLUSTER *s = XILINX_PSX_RPU_CLUSTER(reg->opaque);
420 rpu_cluster_imr_update_irq(s);
421}
422
423static uint64_t rpu_cluster_ien_prew(RegisterInfo *reg, uint64_t val64)
424{
425 PSX_RPU_CLUSTER *s = XILINX_PSX_RPU_CLUSTER(reg->opaque);
426 uint32_t val = val64;
427
428 s->regs[R_RPU_CLUSTER_IMR] &= ~val;
429 rpu_cluster_imr_update_irq(s);
430 return 0;
431}
432
433static uint64_t rpu_cluster_ids_prew(RegisterInfo *reg, uint64_t val64)
434{
435 PSX_RPU_CLUSTER *s = XILINX_PSX_RPU_CLUSTER(reg->opaque);
436 uint32_t val = val64;
437
438 s->regs[R_RPU_CLUSTER_IMR] |= val;
439 rpu_cluster_imr_update_irq(s);
440 return 0;
441}
442
443static void cluster_cfg_postw(RegisterInfo *reg, uint64_t val64)
444{
445 PSX_RPU_CLUSTER *s = XILINX_PSX_RPU_CLUSTER(reg->opaque);
446
447 PROPAGATE_GPIO(CLUSTER_CFG, SLSPLIT, s->slsplit);
448}
449
450static void cluster_axis_postw(RegisterInfo *reg, uint64_t val64)
451{
452 PSX_RPU_CLUSTER *s = XILINX_PSX_RPU_CLUSTER(reg->opaque);
453 uint32_t val = val64;
454 uint32_t addr;
455 MemoryRegionSection section;
456
457 if (!s->tcm_mr) {
458 return;
459 }
460
461 section = memory_region_find(s->tcm_mr, 0, 0x400000);
462 addr = section.offset_within_address_space;
463 addr &= 0xFFFFFF;
464 addr |= val & R_CLUSTER_AXIS_TCM_BASE_MASK;
465 memory_region_set_address(s->tcm_mr, addr);
466 memory_region_unref(section.mr);
467}
468
469static const RegisterAccessInfo psx_rpu_cluster_regs_info[] = {
470 { .name = "CLUSTER_CFG", .addr = A_CLUSTER_CFG,
471 .rsvd = 0xffffecfe,
472 .ro = 0x100,
473 .post_write = cluster_cfg_postw,
474 },{ .name = "CLUSTER_AXIS", .addr = A_CLUSTER_AXIS,
475 .rsvd = 0xffffff,
476 .post_write = cluster_axis_postw,
477 },{ .name = "CLUSTER_PERIPH", .addr = A_CLUSTER_PERIPH,
478 .reset = 0xe2000000,
479 .rsvd = 0x1fffff,
480 },{ .name = "CLUSTER_LLPP", .addr = A_CLUSTER_LLPP,
481 .reset = 0x8000000d,
482 .rsvd = 0xff0,
483 },{ .name = "CLUSTER_DCLSCOMPIN_LO", .addr = A_CLUSTER_DCLSCOMPIN_LO,
484 .rsvd = 0xf0000000,
485 },{ .name = "CLUSTER_DCLSCOMPIN_HI", .addr = A_CLUSTER_DCLSCOMPIN_HI,
486 .rsvd = 0xfffffc0f,
487 },{ .name = "CLUSTER_INTR_0", .addr = A_CLUSTER_INTR_0,
488 },{ .name = "CLUSTER_INTR_1", .addr = A_CLUSTER_INTR_1,
489 },{ .name = "CLUSTER_INTR_2", .addr = A_CLUSTER_INTR_2,
490 },{ .name = "CLUSTER_INTR_3", .addr = A_CLUSTER_INTR_3,
491 },{ .name = "CLUSTER_INTR_4", .addr = A_CLUSTER_INTR_4,
492 },{ .name = "CLUSTER_INTR_MASK_0", .addr = A_CLUSTER_INTR_MASK_0,
493 },{ .name = "CLUSTER_INTR_MASK_1", .addr = A_CLUSTER_INTR_MASK_1,
494 },{ .name = "CLUSTER_INTR_MASK_2", .addr = A_CLUSTER_INTR_MASK_2,
495 },{ .name = "CLUSTER_INTR_MASK_3", .addr = A_CLUSTER_INTR_MASK_3,
496 },{ .name = "CLUSTER_INTR_MASK_4", .addr = A_CLUSTER_INTR_MASK_4,
497 },{ .name = "CLUSTER_CCF_VAL", .addr = A_CLUSTER_CCF_VAL,
498 .reset = 0x7,
499 .rsvd = 0xffffff00,
500 },{ .name = "CLUSTER_CCF_MASK", .addr = A_CLUSTER_CCF_MASK,
501 .rsvd = 0xffffff00,
502 },{ .name = "CLUSTER_SAFETY_CHK", .addr = A_CLUSTER_SAFETY_CHK,
503 },{ .name = "CLUSTER_DCLSCOMPOUT_LO_STATUS",
504 .addr = A_CLUSTER_DCLSCOMPOUT_LO_STATUS,
505 .rsvd = 0xf0000000,
506 .w1c = 0xfffffff,
507 .post_write = cluster_dclscompout_lo_status_postw,
508 },{ .name = "CLUSTER_DCLSCOMPOUT_LO_MASK",
509 .addr = A_CLUSTER_DCLSCOMPOUT_LO_MASK,
510 .reset = 0xfffffff,
511 .rsvd = 0xf0000000,
512 .ro = 0xfffffff,
513 },{ .name = "CLUSTER_DCLSCOMPOUT_LO_EN",
514 .addr = A_CLUSTER_DCLSCOMPOUT_LO_EN,
515 .rsvd = 0xf0000000,
516 .pre_write = cluster_dclscompout_lo_en_prew,
517 },{ .name = "CLUSTER_DCLSCOMPOUT_LO_DIS",
518 .addr = A_CLUSTER_DCLSCOMPOUT_LO_DIS,
519 .rsvd = 0xf0000000,
520 .pre_write = cluster_dclscompout_lo_dis_prew,
521 },{ .name = "CLUSTER_DCLSCOMPOUT_LO_TRIGG",
522 .addr = A_CLUSTER_DCLSCOMPOUT_LO_TRIGG,
523 .rsvd = 0xf0000000,
524 .pre_write = cluster_dclscompout_lo_trigg_prew,
525 },{ .name = "CLUSTER_DCLSCOMPOUT_HI_STATUS",
526 .addr = A_CLUSTER_DCLSCOMPOUT_HI_STATUS,
527 .rsvd = 0xfffffc0f,
528 .w1c = 0x3f0,
529 .post_write = cluster_dclscompout_hi_status_postw,
530 },{ .name = "CLUSTER_DCLSCOMPOUT_HI_MASK",
531 .addr = A_CLUSTER_DCLSCOMPOUT_HI_MASK,
532 .reset = 0x3f0,
533 .rsvd = 0xfffffc0f,
534 .ro = 0x3f0,
535 },{ .name = "CLUSTER_DCLSCOMPOUT_HI_EN",
536 .addr = A_CLUSTER_DCLSCOMPOUT_HI_EN,
537 .rsvd = 0xfffffc0f,
538 .pre_write = cluster_dclscompout_hi_en_prew,
539 },{ .name = "CLUSTER_DCLSCOMPOUT_HI_DIS",
540 .addr = A_CLUSTER_DCLSCOMPOUT_HI_DIS,
541 .rsvd = 0xfffffc0f,
542 .pre_write = cluster_dclscompout_hi_dis_prew,
543 },{ .name = "CLUSTER_DCLSCOMPOUT_HI_TRIGG",
544 .addr = A_CLUSTER_DCLSCOMPOUT_HI_TRIGG,
545 .rsvd = 0xfffffc0f,
546 .pre_write = cluster_dclscompout_hi_trigg_prew,
547 },{ .name = "CLUSTER_MPID", .addr = A_CLUSTER_MPID,
548 .rsvd = 0xff0000ff,
549 .ro = 0x10100,
550 },{ .name = "RPU_CLUSTER_ISR", .addr = A_RPU_CLUSTER_ISR,
551 .rsvd = 0xfffffffc,
552 .w1c = 0x3,
553 .post_write = rpu_cluster_isr_postw,
554 },{ .name = "RPU_CLUSTER_IMR", .addr = A_RPU_CLUSTER_IMR,
555 .reset = 0x3,
556 .rsvd = 0xfffffffc,
557 .ro = 0x3,
558 },{ .name = "RPU_CLUSTER_IEN", .addr = A_RPU_CLUSTER_IEN,
559 .rsvd = 0xfffffffc,
560 .pre_write = rpu_cluster_ien_prew,
561 },{ .name = "RPU_CLUSTER_IDS", .addr = A_RPU_CLUSTER_IDS,
562 .rsvd = 0xfffffffc,
563 .pre_write = rpu_cluster_ids_prew,
564 },{ .name = "RPU_CLUSTER_PAR_MON", .addr = A_RPU_CLUSTER_PAR_MON,
565 .rsvd = 0xfffffffe,
566 },{ .name = "CLUSTER_INTR_5", .addr = A_CLUSTER_INTR_5,
567 },{ .name = "CLUSTER_INTR_6", .addr = A_CLUSTER_INTR_6,
568 },{ .name = "CLUSTER_INTR_7", .addr = A_CLUSTER_INTR_7,
569 },{ .name = "CLUSTER_INTR_MASK_5", .addr = A_CLUSTER_INTR_MASK_5,
570 },{ .name = "CLUSTER_INTR_MASK_6", .addr = A_CLUSTER_INTR_MASK_6,
571 },{ .name = "CLUSTER_INTR_MASK_7", .addr = A_CLUSTER_INTR_MASK_7,
572 }
573};
574
575static void psx_rpu_cluster_reset_enter(Object *obj, ResetType type)
576{
577 PSX_RPU_CLUSTER *s = XILINX_PSX_RPU_CLUSTER(obj);
578 unsigned int i;
579
580 for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
581 switch (i) {
582 case R_CLUSTER_AXIS:
583 continue;
584 default:
585 register_reset(&s->regs_info[i]);
586 };
587 }
588 s->regs[R_CLUSTER_AXIS] = s->axis_base &
589 R_CLUSTER_AXIS_TCM_BASE_MASK;
590}
591
592static void psx_rpu_cluster_reset_hold(Object *obj)
593{
594 PSX_RPU_CLUSTER *s = XILINX_PSX_RPU_CLUSTER(obj);
595
596 cluster_dclscompout_hi_update_irq(s);
597 cluster_dclscompout_lo_update_irq(s);
598 rpu_cluster_imr_update_irq(s);
599}
600
601static const MemoryRegionOps psx_rpu_cluster_ops = {
602 .read = register_read_memory,
603 .write = register_write_memory,
604 .endianness = DEVICE_LITTLE_ENDIAN,
605 .valid = {
606 .min_access_size = 4,
607 .max_access_size = 4,
608 },
609};
610
611static void psx_rpu_cluster_init(Object *obj)
612{
613 PSX_RPU_CLUSTER *s = XILINX_PSX_RPU_CLUSTER(obj);
614 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
615 RegisterInfoArray *reg_array;
616
617 memory_region_init(&s->iomem, obj, TYPE_XILINX_PSX_RPU_CLUSTER,
618 PSX_RPU_CLUSTER_R_MAX * 4);
619 reg_array =
620 register_init_block32(DEVICE(obj), psx_rpu_cluster_regs_info,
621 ARRAY_SIZE(psx_rpu_cluster_regs_info),
622 s->regs_info, s->regs,
623 &psx_rpu_cluster_ops,
624 XILINX_PSX_RPU_CLUSTER_ERR_DEBUG,
625 PSX_RPU_CLUSTER_R_MAX * 4);
626 memory_region_add_subregion(&s->iomem,
627 0x0,
628 ®_array->mem);
629 sysbus_init_mmio(sbd, &s->iomem);
630 sysbus_init_irq(sbd, &s->irq_cluster_dclscompout_hi);
631 sysbus_init_irq(sbd, &s->irq_cluster_dclscompout_lo);
632 sysbus_init_irq(sbd, &s->irq_rpu_cluster_imr);
633 qdev_init_gpio_out(DEVICE(obj), &s->slsplit, 1);
634 object_property_add_link(obj, "tcm-mr", TYPE_MEMORY_REGION,
635 (Object **)&s->tcm_mr,
636 qdev_prop_allow_set_link_before_realize,
637 OBJ_PROP_LINK_STRONG);
638}
639
640static const VMStateDescription vmstate_psx_rpu_cluster = {
641 .name = TYPE_XILINX_PSX_RPU_CLUSTER,
642 .version_id = 1,
643 .minimum_version_id = 1,
644 .fields = (VMStateField[]) {
645 VMSTATE_UINT32_ARRAY(regs, PSX_RPU_CLUSTER, PSX_RPU_CLUSTER_R_MAX),
646 VMSTATE_END_OF_LIST(),
647 }
648};
649
650static Property psx_rpu_cluster_prop[] = {
651 DEFINE_PROP_UINT32("axis-base", PSX_RPU_CLUSTER, axis_base,
652 0xFF000000),
653 DEFINE_PROP_END_OF_LIST(),
654};
655
656static void psx_rpu_cluster_class_init(ObjectClass *klass, void *data)
657{
658 ResettableClass *rc = RESETTABLE_CLASS(klass);
659 DeviceClass *dc = DEVICE_CLASS(klass);
660
661 dc->vmsd = &vmstate_psx_rpu_cluster;
662 rc->phases.enter = psx_rpu_cluster_reset_enter;
663 rc->phases.hold = psx_rpu_cluster_reset_hold;
664 device_class_set_props(dc, psx_rpu_cluster_prop);
665}
666
667static const TypeInfo psx_rpu_cluster_info = {
668 .name = TYPE_XILINX_PSX_RPU_CLUSTER,
669 .parent = TYPE_SYS_BUS_DEVICE,
670 .instance_size = sizeof(PSX_RPU_CLUSTER),
671 .class_init = psx_rpu_cluster_class_init,
672 .instance_init = psx_rpu_cluster_init,
673};
674
675static void psx_rpu_cluster_register_types(void)
676{
677 type_register_static(&psx_rpu_cluster_info);
678}
679
680type_init(psx_rpu_cluster_register_types)
681
