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29#include "qemu/osdep.h"
30#include "hw/sysbus.h"
31#include "hw/register.h"
32#include "qemu/bitops.h"
33#include "qemu/log.h"
34#include "migration/vmstate.h"
35#include "hw/qdev-properties.h"
36
37#include "hw/fdt_generic_util.h"
38
39#ifndef XILINX_PSM_GLOBAL_REG_ERR_DEBUG
40#define XILINX_PSM_GLOBAL_REG_ERR_DEBUG 0
41#endif
42
43#define TYPE_XILINX_PSM_GLOBAL_REG "xlnx.psm-global-reg"
44
45#define XILINX_PSM_GLOBAL_REG(obj) \
46 OBJECT_CHECK(PSM_GLOBAL_REG, (obj), TYPE_XILINX_PSM_GLOBAL_REG)
47
48REG32(GLOBAL_CNTRL, 0x0)
49 FIELD(GLOBAL_CNTRL, MB_CLK_EN_FORCE, 18, 1)
50 FIELD(GLOBAL_CNTRL, MB_DBG_WAKE, 17, 1)
51 FIELD(GLOBAL_CNTRL, MB_SLEEP, 16, 1)
52 FIELD(GLOBAL_CNTRL, WRITE_QOS, 12, 4)
53 FIELD(GLOBAL_CNTRL, READ_QOS, 8, 4)
54 FIELD(GLOBAL_CNTRL, FW_IS_PRESENT, 4, 1)
55 FIELD(GLOBAL_CNTRL, SLVERR_ENABLE, 1, 1)
56REG32(APU_PWR_STATUS_INIT, 0x8)
57 FIELD(APU_PWR_STATUS_INIT, ACPU1, 1, 1)
58 FIELD(APU_PWR_STATUS_INIT, ACPU0, 0, 1)
59REG32(ADDR_ERROR_STATUS, 0x10)
60 FIELD(ADDR_ERROR_STATUS, STATUS, 0, 1)
61REG32(ADDR_ERROR_INT_MASK, 0x14)
62 FIELD(ADDR_ERROR_INT_MASK, MASK, 0, 1)
63REG32(ADDR_ERROR_INT_EN, 0x18)
64 FIELD(ADDR_ERROR_INT_EN, ENABLE, 0, 1)
65REG32(ADDR_ERROR_INT_DIS, 0x1c)
66 FIELD(ADDR_ERROR_INT_DIS, DISABLE, 0, 1)
67REG32(PS_SW_ERR, 0x20)
68 FIELD(PS_SW_ERR, NCR_FLAG, 31, 1)
69 FIELD(PS_SW_ERR, CR_FLAG, 30, 1)
70 FIELD(PS_SW_ERR, DATA, 0, 30)
71REG32(PSM_BOOT_SERV_ERR, 0x24)
72 FIELD(PSM_BOOT_SERV_ERR, NCR_FLAG, 31, 1)
73 FIELD(PSM_BOOT_SERV_ERR, CR_FLAG, 30, 1)
74 FIELD(PSM_BOOT_SERV_ERR, DATA, 0, 30)
75REG32(GLOBAL_GEN_STORAGE0, 0x30)
76REG32(GLOBAL_GEN_STORAGE1, 0x34)
77REG32(GLOBAL_GEN_STORAGE2, 0x38)
78REG32(GLOBAL_GEN_STORAGE3, 0x3c)
79REG32(GLOBAL_GEN_STORAGE4, 0x40)
80REG32(GLOBAL_GEN_STORAGE5, 0x44)
81REG32(GLOBAL_GEN_STORAGE6, 0x48)
82REG32(GLOBAL_GEN_STORAGE7, 0x4c)
83REG32(PERS_GLOB_GEN_STORAGE0, 0x50)
84REG32(PERS_GLOB_GEN_STORAGE1, 0x54)
85REG32(PERS_GLOB_GEN_STORAGE2, 0x58)
86REG32(PERS_GLOB_GEN_STORAGE3, 0x5c)
87REG32(PERS_GLOB_GEN_STORAGE4, 0x60)
88REG32(PERS_GLOB_GEN_STORAGE5, 0x64)
89REG32(PERS_GLOB_GEN_STORAGE6, 0x68)
90REG32(PERS_GLOB_GEN_STORAGE7, 0x6c)
91REG32(PWR_STATE, 0x100)
92 FIELD(PWR_STATE, FP, 22, 1)
93 FIELD(PWR_STATE, GEM0, 21, 1)
94 FIELD(PWR_STATE, GEM1, 20, 1)
95 FIELD(PWR_STATE, OCM_BANK3, 19, 1)
96 FIELD(PWR_STATE, OCM_BANK2, 18, 1)
97 FIELD(PWR_STATE, OCM_BANK1, 17, 1)
98 FIELD(PWR_STATE, OCM_BANK0, 16, 1)
99 FIELD(PWR_STATE, TCM1B, 15, 1)
100 FIELD(PWR_STATE, TCM1A, 14, 1)
101 FIELD(PWR_STATE, TCM0B, 13, 1)
102 FIELD(PWR_STATE, TCM0A, 12, 1)
103 FIELD(PWR_STATE, R5_1, 11, 1)
104 FIELD(PWR_STATE, R5_0, 10, 1)
105 FIELD(PWR_STATE, L2_BANK0, 7, 1)
106 FIELD(PWR_STATE, ACPU1, 1, 1)
107 FIELD(PWR_STATE, ACPU0, 0, 1)
108REG32(AUX_PWR_STATE, 0x104)
109 FIELD(AUX_PWR_STATE, ACPU1_EMULATION, 29, 1)
110 FIELD(AUX_PWR_STATE, ACPU0_EMULATION, 28, 1)
111 FIELD(AUX_PWR_STATE, RPU_EMULATION, 27, 1)
112 FIELD(AUX_PWR_STATE, OCM_BANK3, 19, 1)
113 FIELD(AUX_PWR_STATE, OCM_BANK2, 18, 1)
114 FIELD(AUX_PWR_STATE, OCM_BANK1, 17, 1)
115 FIELD(AUX_PWR_STATE, OCM_BANK0, 16, 1)
116 FIELD(AUX_PWR_STATE, TCM1B, 15, 1)
117 FIELD(AUX_PWR_STATE, TCM1A, 14, 1)
118 FIELD(AUX_PWR_STATE, TCM0B, 13, 1)
119 FIELD(AUX_PWR_STATE, TCM0A, 12, 1)
120 FIELD(AUX_PWR_STATE, L2_BANK0, 7, 1)
121REG32(REQ_PWRUP_STATUS, 0x110)
122 FIELD(REQ_PWRUP_STATUS, FP, 22, 1)
123 FIELD(REQ_PWRUP_STATUS, GEM0, 21, 1)
124 FIELD(REQ_PWRUP_STATUS, GEM1, 20, 1)
125 FIELD(REQ_PWRUP_STATUS, OCM_BANK3, 19, 1)
126 FIELD(REQ_PWRUP_STATUS, OCM_BANK2, 18, 1)
127 FIELD(REQ_PWRUP_STATUS, OCM_BANK1, 17, 1)
128 FIELD(REQ_PWRUP_STATUS, OCM_BANK0, 16, 1)
129 FIELD(REQ_PWRUP_STATUS, TCM1B, 15, 1)
130 FIELD(REQ_PWRUP_STATUS, TCM1A, 14, 1)
131 FIELD(REQ_PWRUP_STATUS, TCM0B, 13, 1)
132 FIELD(REQ_PWRUP_STATUS, TCM0A, 12, 1)
133 FIELD(REQ_PWRUP_STATUS, RPU, 10, 1)
134 FIELD(REQ_PWRUP_STATUS, L2_BANK0, 7, 1)
135 FIELD(REQ_PWRUP_STATUS, ACPU1, 1, 1)
136 FIELD(REQ_PWRUP_STATUS, ACPU0, 0, 1)
137REG32(REQ_PWRUP_INT_MASK, 0x114)
138 FIELD(REQ_PWRUP_INT_MASK, FP, 22, 1)
139 FIELD(REQ_PWRUP_INT_MASK, GEM0, 21, 1)
140 FIELD(REQ_PWRUP_INT_MASK, GEM1, 20, 1)
141 FIELD(REQ_PWRUP_INT_MASK, OCM_BANK3, 19, 1)
142 FIELD(REQ_PWRUP_INT_MASK, OCM_BANK2, 18, 1)
143 FIELD(REQ_PWRUP_INT_MASK, OCM_BANK1, 17, 1)
144 FIELD(REQ_PWRUP_INT_MASK, OCM_BANK0, 16, 1)
145 FIELD(REQ_PWRUP_INT_MASK, TCM1B, 15, 1)
146 FIELD(REQ_PWRUP_INT_MASK, TCM1A, 14, 1)
147 FIELD(REQ_PWRUP_INT_MASK, TCM0B, 13, 1)
148 FIELD(REQ_PWRUP_INT_MASK, TCM0A, 12, 1)
149 FIELD(REQ_PWRUP_INT_MASK, RPU, 10, 1)
150 FIELD(REQ_PWRUP_INT_MASK, L2_BANK0, 7, 1)
151 FIELD(REQ_PWRUP_INT_MASK, ACPU1, 1, 1)
152 FIELD(REQ_PWRUP_INT_MASK, ACPU0, 0, 1)
153REG32(REQ_PWRUP_INT_EN, 0x118)
154 FIELD(REQ_PWRUP_INT_EN, FP, 22, 1)
155 FIELD(REQ_PWRUP_INT_EN, GEM0, 21, 1)
156 FIELD(REQ_PWRUP_INT_EN, GEM1, 20, 1)
157 FIELD(REQ_PWRUP_INT_EN, OCM_BANK3, 19, 1)
158 FIELD(REQ_PWRUP_INT_EN, OCM_BANK2, 18, 1)
159 FIELD(REQ_PWRUP_INT_EN, OCM_BANK1, 17, 1)
160 FIELD(REQ_PWRUP_INT_EN, OCM_BANK0, 16, 1)
161 FIELD(REQ_PWRUP_INT_EN, TCM1B, 15, 1)
162 FIELD(REQ_PWRUP_INT_EN, TCM1A, 14, 1)
163 FIELD(REQ_PWRUP_INT_EN, TCM0B, 13, 1)
164 FIELD(REQ_PWRUP_INT_EN, TCM0A, 12, 1)
165 FIELD(REQ_PWRUP_INT_EN, RPU, 10, 1)
166 FIELD(REQ_PWRUP_INT_EN, L2_BANK0, 7, 1)
167 FIELD(REQ_PWRUP_INT_EN, ACPU1, 1, 1)
168 FIELD(REQ_PWRUP_INT_EN, ACPU0, 0, 1)
169REG32(REQ_PWRUP_INT_DIS, 0x11c)
170 FIELD(REQ_PWRUP_INT_DIS, FP, 22, 1)
171 FIELD(REQ_PWRUP_INT_DIS, GEM0, 21, 1)
172 FIELD(REQ_PWRUP_INT_DIS, GEM1, 20, 1)
173 FIELD(REQ_PWRUP_INT_DIS, OCM_BANK3, 19, 1)
174 FIELD(REQ_PWRUP_INT_DIS, OCM_BANK2, 18, 1)
175 FIELD(REQ_PWRUP_INT_DIS, OCM_BANK1, 17, 1)
176 FIELD(REQ_PWRUP_INT_DIS, OCM_BANK0, 16, 1)
177 FIELD(REQ_PWRUP_INT_DIS, TCM1B, 15, 1)
178 FIELD(REQ_PWRUP_INT_DIS, TCM1A, 14, 1)
179 FIELD(REQ_PWRUP_INT_DIS, TCM0B, 13, 1)
180 FIELD(REQ_PWRUP_INT_DIS, TCM0A, 12, 1)
181 FIELD(REQ_PWRUP_INT_DIS, RPU, 10, 1)
182 FIELD(REQ_PWRUP_INT_DIS, L2_BANK0, 7, 1)
183 FIELD(REQ_PWRUP_INT_DIS, ACPU1, 1, 1)
184 FIELD(REQ_PWRUP_INT_DIS, ACPU0, 0, 1)
185REG32(REQ_PWRUP_TRIG, 0x120)
186 FIELD(REQ_PWRUP_TRIG, FP, 22, 1)
187 FIELD(REQ_PWRUP_TRIG, GEM0, 21, 1)
188 FIELD(REQ_PWRUP_TRIG, GEM1, 20, 1)
189 FIELD(REQ_PWRUP_TRIG, OCM_BANK3, 19, 1)
190 FIELD(REQ_PWRUP_TRIG, OCM_BANK2, 18, 1)
191 FIELD(REQ_PWRUP_TRIG, OCM_BANK1, 17, 1)
192 FIELD(REQ_PWRUP_TRIG, OCM_BANK0, 16, 1)
193 FIELD(REQ_PWRUP_TRIG, TCM1B, 15, 1)
194 FIELD(REQ_PWRUP_TRIG, TCM1A, 14, 1)
195 FIELD(REQ_PWRUP_TRIG, TCM0B, 13, 1)
196 FIELD(REQ_PWRUP_TRIG, TCM0A, 12, 1)
197 FIELD(REQ_PWRUP_TRIG, RPU, 10, 1)
198 FIELD(REQ_PWRUP_TRIG, L2_BANK0, 7, 1)
199 FIELD(REQ_PWRUP_TRIG, ACPU1, 1, 1)
200 FIELD(REQ_PWRUP_TRIG, ACPU0, 0, 1)
201REG32(REQ_PWRDWN_STATUS, 0x210)
202 FIELD(REQ_PWRDWN_STATUS, FP, 22, 1)
203 FIELD(REQ_PWRDWN_STATUS, GEM0, 21, 1)
204 FIELD(REQ_PWRDWN_STATUS, GEM1, 20, 1)
205 FIELD(REQ_PWRDWN_STATUS, OCM_BANK3, 19, 1)
206 FIELD(REQ_PWRDWN_STATUS, OCM_BANK2, 18, 1)
207 FIELD(REQ_PWRDWN_STATUS, OCM_BANK1, 17, 1)
208 FIELD(REQ_PWRDWN_STATUS, OCM_BANK0, 16, 1)
209 FIELD(REQ_PWRDWN_STATUS, TCM1B, 15, 1)
210 FIELD(REQ_PWRDWN_STATUS, TCM1A, 14, 1)
211 FIELD(REQ_PWRDWN_STATUS, TCM0B, 13, 1)
212 FIELD(REQ_PWRDWN_STATUS, TCM0A, 12, 1)
213 FIELD(REQ_PWRDWN_STATUS, RPU, 10, 1)
214 FIELD(REQ_PWRDWN_STATUS, L2_BANK0, 7, 1)
215 FIELD(REQ_PWRDWN_STATUS, ACPU1, 1, 1)
216 FIELD(REQ_PWRDWN_STATUS, ACPU0, 0, 1)
217REG32(REQ_PWRDWN_INT_MASK, 0x214)
218 FIELD(REQ_PWRDWN_INT_MASK, FP, 22, 1)
219 FIELD(REQ_PWRDWN_INT_MASK, GEM0, 21, 1)
220 FIELD(REQ_PWRDWN_INT_MASK, GEM1, 20, 1)
221 FIELD(REQ_PWRDWN_INT_MASK, OCM_BANK3, 19, 1)
222 FIELD(REQ_PWRDWN_INT_MASK, OCM_BANK2, 18, 1)
223 FIELD(REQ_PWRDWN_INT_MASK, OCM_BANK1, 17, 1)
224 FIELD(REQ_PWRDWN_INT_MASK, OCM_BANK0, 16, 1)
225 FIELD(REQ_PWRDWN_INT_MASK, TCM1B, 15, 1)
226 FIELD(REQ_PWRDWN_INT_MASK, TCM1A, 14, 1)
227 FIELD(REQ_PWRDWN_INT_MASK, TCM0B, 13, 1)
228 FIELD(REQ_PWRDWN_INT_MASK, TCM0A, 12, 1)
229 FIELD(REQ_PWRDWN_INT_MASK, RPU, 10, 1)
230 FIELD(REQ_PWRDWN_INT_MASK, L2_BANK0, 7, 1)
231 FIELD(REQ_PWRDWN_INT_MASK, ACPU1, 1, 1)
232 FIELD(REQ_PWRDWN_INT_MASK, ACPU0, 0, 1)
233REG32(REQ_PWRDWN_INT_EN, 0x218)
234 FIELD(REQ_PWRDWN_INT_EN, FP, 22, 1)
235 FIELD(REQ_PWRDWN_INT_EN, GEM0, 21, 1)
236 FIELD(REQ_PWRDWN_INT_EN, GEM1, 20, 1)
237 FIELD(REQ_PWRDWN_INT_EN, OCM_BANK3, 19, 1)
238 FIELD(REQ_PWRDWN_INT_EN, OCM_BANK2, 18, 1)
239 FIELD(REQ_PWRDWN_INT_EN, OCM_BANK1, 17, 1)
240 FIELD(REQ_PWRDWN_INT_EN, OCM_BANK0, 16, 1)
241 FIELD(REQ_PWRDWN_INT_EN, TCM1B, 15, 1)
242 FIELD(REQ_PWRDWN_INT_EN, TCM1A, 14, 1)
243 FIELD(REQ_PWRDWN_INT_EN, TCM0B, 13, 1)
244 FIELD(REQ_PWRDWN_INT_EN, TCM0A, 12, 1)
245 FIELD(REQ_PWRDWN_INT_EN, RPU, 10, 1)
246 FIELD(REQ_PWRDWN_INT_EN, L2_BANK0, 7, 1)
247 FIELD(REQ_PWRDWN_INT_EN, ACPU1, 1, 1)
248 FIELD(REQ_PWRDWN_INT_EN, ACPU0, 0, 1)
249REG32(REQ_PWRDWN_INT_DIS, 0x21c)
250 FIELD(REQ_PWRDWN_INT_DIS, FP, 22, 1)
251 FIELD(REQ_PWRDWN_INT_DIS, GEM0, 21, 1)
252 FIELD(REQ_PWRDWN_INT_DIS, GEM1, 20, 1)
253 FIELD(REQ_PWRDWN_INT_DIS, OCM_BANK3, 19, 1)
254 FIELD(REQ_PWRDWN_INT_DIS, OCM_BANK2, 18, 1)
255 FIELD(REQ_PWRDWN_INT_DIS, OCM_BANK1, 17, 1)
256 FIELD(REQ_PWRDWN_INT_DIS, OCM_BANK0, 16, 1)
257 FIELD(REQ_PWRDWN_INT_DIS, TCM1B, 15, 1)
258 FIELD(REQ_PWRDWN_INT_DIS, TCM1A, 14, 1)
259 FIELD(REQ_PWRDWN_INT_DIS, TCM0B, 13, 1)
260 FIELD(REQ_PWRDWN_INT_DIS, TCM0A, 12, 1)
261 FIELD(REQ_PWRDWN_INT_DIS, RPU, 10, 1)
262 FIELD(REQ_PWRDWN_INT_DIS, L2_BANK0, 7, 1)
263 FIELD(REQ_PWRDWN_INT_DIS, ACPU1, 1, 1)
264 FIELD(REQ_PWRDWN_INT_DIS, ACPU0, 0, 1)
265REG32(REQ_PWRDWN_TRIG, 0x220)
266 FIELD(REQ_PWRDWN_TRIG, FP, 22, 1)
267 FIELD(REQ_PWRDWN_TRIG, GEM0, 21, 1)
268 FIELD(REQ_PWRDWN_TRIG, GEM1, 20, 1)
269 FIELD(REQ_PWRDWN_TRIG, OCM_BANK3, 19, 1)
270 FIELD(REQ_PWRDWN_TRIG, OCM_BANK2, 18, 1)
271 FIELD(REQ_PWRDWN_TRIG, OCM_BANK1, 17, 1)
272 FIELD(REQ_PWRDWN_TRIG, OCM_BANK0, 16, 1)
273 FIELD(REQ_PWRDWN_TRIG, TCM1B, 15, 1)
274 FIELD(REQ_PWRDWN_TRIG, TCM1A, 14, 1)
275 FIELD(REQ_PWRDWN_TRIG, TCM0B, 13, 1)
276 FIELD(REQ_PWRDWN_TRIG, TCM0A, 12, 1)
277 FIELD(REQ_PWRDWN_TRIG, RPU, 10, 1)
278 FIELD(REQ_PWRDWN_TRIG, L2_BANK0, 7, 1)
279 FIELD(REQ_PWRDWN_TRIG, ACPU1, 1, 1)
280 FIELD(REQ_PWRDWN_TRIG, ACPU0, 0, 1)
281REG32(REQ_ISO_STATUS, 0x310)
282 FIELD(REQ_ISO_STATUS, FP, 0, 1)
283REG32(REQ_ISO_INT_MASK, 0x314)
284 FIELD(REQ_ISO_INT_MASK, FP, 0, 1)
285REG32(REQ_ISO_INT_EN, 0x318)
286 FIELD(REQ_ISO_INT_EN, FP, 0, 1)
287REG32(REQ_ISO_INT_DIS, 0x31c)
288 FIELD(REQ_ISO_INT_DIS, FP, 0, 1)
289REG32(REQ_ISO_TRIG, 0x320)
290 FIELD(REQ_ISO_TRIG, FP, 0, 1)
291REG32(REQ_SWRST_STATUS, 0x410)
292 FIELD(REQ_SWRST_STATUS, FP, 30, 1)
293 FIELD(REQ_SWRST_STATUS, LP, 29, 1)
294 FIELD(REQ_SWRST_STATUS, PS_ONLY, 28, 1)
295 FIELD(REQ_SWRST_STATUS, IOU, 27, 1)
296 FIELD(REQ_SWRST_STATUS, USB0, 24, 1)
297 FIELD(REQ_SWRST_STATUS, GEM1, 21, 1)
298 FIELD(REQ_SWRST_STATUS, GEM0, 20, 1)
299 FIELD(REQ_SWRST_STATUS, LS_R5, 18, 1)
300 FIELD(REQ_SWRST_STATUS, APU, 4, 1)
301 FIELD(REQ_SWRST_STATUS, ACPU1, 1, 1)
302 FIELD(REQ_SWRST_STATUS, ACPU0, 0, 1)
303REG32(REQ_SWRST_INT_MASK, 0x414)
304 FIELD(REQ_SWRST_INT_MASK, FP, 30, 1)
305 FIELD(REQ_SWRST_INT_MASK, LP, 29, 1)
306 FIELD(REQ_SWRST_INT_MASK, PS_ONLY, 28, 1)
307 FIELD(REQ_SWRST_INT_MASK, IOU, 27, 1)
308 FIELD(REQ_SWRST_INT_MASK, USB0, 24, 1)
309 FIELD(REQ_SWRST_INT_MASK, GEM1, 21, 1)
310 FIELD(REQ_SWRST_INT_MASK, GEM0, 20, 1)
311 FIELD(REQ_SWRST_INT_MASK, LS_R5, 18, 1)
312 FIELD(REQ_SWRST_INT_MASK, APU, 4, 1)
313 FIELD(REQ_SWRST_INT_MASK, ACPU1, 1, 1)
314 FIELD(REQ_SWRST_INT_MASK, ACPU0, 0, 1)
315REG32(REQ_SWRST_INT_EN, 0x418)
316 FIELD(REQ_SWRST_INT_EN, FP, 30, 1)
317 FIELD(REQ_SWRST_INT_EN, LP, 29, 1)
318 FIELD(REQ_SWRST_INT_EN, PS_ONLY, 28, 1)
319 FIELD(REQ_SWRST_INT_EN, IOU, 27, 1)
320 FIELD(REQ_SWRST_INT_EN, USB0, 24, 1)
321 FIELD(REQ_SWRST_INT_EN, GEM1, 21, 1)
322 FIELD(REQ_SWRST_INT_EN, GEM0, 20, 1)
323 FIELD(REQ_SWRST_INT_EN, LS_R5, 18, 1)
324 FIELD(REQ_SWRST_INT_EN, APU, 4, 1)
325 FIELD(REQ_SWRST_INT_EN, ACPU1, 1, 1)
326 FIELD(REQ_SWRST_INT_EN, ACPU0, 0, 1)
327REG32(REQ_SWRST_INT_DIS, 0x41c)
328 FIELD(REQ_SWRST_INT_DIS, FP, 30, 1)
329 FIELD(REQ_SWRST_INT_DIS, LP, 29, 1)
330 FIELD(REQ_SWRST_INT_DIS, PS_ONLY, 28, 1)
331 FIELD(REQ_SWRST_INT_DIS, IOU, 27, 1)
332 FIELD(REQ_SWRST_INT_DIS, USB0, 24, 1)
333 FIELD(REQ_SWRST_INT_DIS, GEM1, 21, 1)
334 FIELD(REQ_SWRST_INT_DIS, GEM0, 20, 1)
335 FIELD(REQ_SWRST_INT_DIS, LS_R5, 18, 1)
336 FIELD(REQ_SWRST_INT_DIS, APU, 4, 1)
337 FIELD(REQ_SWRST_INT_DIS, ACPU1, 1, 1)
338 FIELD(REQ_SWRST_INT_DIS, ACPU0, 0, 1)
339REG32(REQ_SWRST_TRIG, 0x420)
340 FIELD(REQ_SWRST_TRIG, FP, 30, 1)
341 FIELD(REQ_SWRST_TRIG, LP, 29, 1)
342 FIELD(REQ_SWRST_TRIG, PS_ONLY, 28, 1)
343 FIELD(REQ_SWRST_TRIG, IOU, 27, 1)
344 FIELD(REQ_SWRST_TRIG, USB0, 24, 1)
345 FIELD(REQ_SWRST_TRIG, GEM1, 21, 1)
346 FIELD(REQ_SWRST_TRIG, GEM0, 20, 1)
347 FIELD(REQ_SWRST_TRIG, LS_R5, 18, 1)
348 FIELD(REQ_SWRST_TRIG, APU, 4, 1)
349 FIELD(REQ_SWRST_TRIG, ACPU1, 1, 1)
350 FIELD(REQ_SWRST_TRIG, ACPU0, 0, 1)
351REG32(REQ_AUX_STATUS, 0x510)
352 FIELD(REQ_AUX_STATUS, SERV_REQ_10, 17, 1)
353 FIELD(REQ_AUX_STATUS, SERV_REQ_9, 16, 1)
354 FIELD(REQ_AUX_STATUS, SERV_REQ_8, 13, 1)
355 FIELD(REQ_AUX_STATUS, SERV_REQ_7, 12, 1)
356 FIELD(REQ_AUX_STATUS, SERV_REQ_6, 10, 1)
357 FIELD(REQ_AUX_STATUS, SERV_REQ_5, 7, 1)
358 FIELD(REQ_AUX_STATUS, SERV_REQ_4, 6, 1)
359 FIELD(REQ_AUX_STATUS, SERV_REQ_3, 3, 1)
360 FIELD(REQ_AUX_STATUS, SERV_REQ_2, 2, 1)
361 FIELD(REQ_AUX_STATUS, SERV_REQ_1, 1, 1)
362 FIELD(REQ_AUX_STATUS, SERV_REQ_0, 0, 1)
363REG32(REQ_AUX_INT_MASK, 0x514)
364 FIELD(REQ_AUX_INT_MASK, SERV_REQ_10, 17, 1)
365 FIELD(REQ_AUX_INT_MASK, SERV_REQ_9, 16, 1)
366 FIELD(REQ_AUX_INT_MASK, SERV_REQ_8, 13, 1)
367 FIELD(REQ_AUX_INT_MASK, SERV_REQ_7, 12, 1)
368 FIELD(REQ_AUX_INT_MASK, SERV_REQ_6, 10, 1)
369 FIELD(REQ_AUX_INT_MASK, SERV_REQ_5, 7, 1)
370 FIELD(REQ_AUX_INT_MASK, SERV_REQ_4, 6, 1)
371 FIELD(REQ_AUX_INT_MASK, SERV_REQ_3, 3, 1)
372 FIELD(REQ_AUX_INT_MASK, SERV_REQ_2, 2, 1)
373 FIELD(REQ_AUX_INT_MASK, SERV_REQ_1, 1, 1)
374 FIELD(REQ_AUX_INT_MASK, SERV_REQ_0, 0, 1)
375REG32(REQ_AUX_INT_EN, 0x518)
376 FIELD(REQ_AUX_INT_EN, SERV_REQ_10, 17, 1)
377 FIELD(REQ_AUX_INT_EN, SERV_REQ_9, 16, 1)
378 FIELD(REQ_AUX_INT_EN, SERV_REQ_8, 13, 1)
379 FIELD(REQ_AUX_INT_EN, SERV_REQ_7, 12, 1)
380 FIELD(REQ_AUX_INT_EN, SERV_REQ_6, 10, 1)
381 FIELD(REQ_AUX_INT_EN, SERV_REQ_5, 7, 1)
382 FIELD(REQ_AUX_INT_EN, SERV_REQ_4, 6, 1)
383 FIELD(REQ_AUX_INT_EN, SERV_REQ_3, 3, 1)
384 FIELD(REQ_AUX_INT_EN, SERV_REQ_2, 2, 1)
385 FIELD(REQ_AUX_INT_EN, SERV_REQ_1, 1, 1)
386 FIELD(REQ_AUX_INT_EN, SERV_REQ_0, 0, 1)
387REG32(REQ_AUX_INT_DIS, 0x51c)
388 FIELD(REQ_AUX_INT_DIS, SERV_REQ_10, 17, 1)
389 FIELD(REQ_AUX_INT_DIS, SERV_REQ_9, 16, 1)
390 FIELD(REQ_AUX_INT_DIS, SERV_REQ_8, 13, 1)
391 FIELD(REQ_AUX_INT_DIS, SERV_REQ_7, 12, 1)
392 FIELD(REQ_AUX_INT_DIS, SERV_REQ_6, 10, 1)
393 FIELD(REQ_AUX_INT_DIS, SERV_REQ_5, 7, 1)
394 FIELD(REQ_AUX_INT_DIS, SERV_REQ_4, 6, 1)
395 FIELD(REQ_AUX_INT_DIS, SERV_REQ_3, 3, 1)
396 FIELD(REQ_AUX_INT_DIS, SERV_REQ_2, 2, 1)
397 FIELD(REQ_AUX_INT_DIS, SERV_REQ_1, 1, 1)
398 FIELD(REQ_AUX_INT_DIS, SERV_REQ_0, 0, 1)
399REG32(REQ_AUX_TRIG, 0x520)
400 FIELD(REQ_AUX_TRIG, SERV_REQ_10, 17, 1)
401 FIELD(REQ_AUX_TRIG, SERV_REQ_9, 16, 1)
402 FIELD(REQ_AUX_TRIG, SERV_REQ_8, 13, 1)
403 FIELD(REQ_AUX_TRIG, SERV_REQ_7, 12, 1)
404 FIELD(REQ_AUX_TRIG, SERV_REQ_6, 10, 1)
405 FIELD(REQ_AUX_TRIG, SERV_REQ_5, 7, 1)
406 FIELD(REQ_AUX_TRIG, SERV_REQ_4, 6, 1)
407 FIELD(REQ_AUX_TRIG, SERV_REQ_3, 3, 1)
408 FIELD(REQ_AUX_TRIG, SERV_REQ_2, 2, 1)
409 FIELD(REQ_AUX_TRIG, SERV_REQ_1, 1, 1)
410 FIELD(REQ_AUX_TRIG, SERV_REQ_0, 0, 1)
411REG32(MB_FATAL, 0x52c)
412 FIELD(MB_FATAL, CPU3, 2, 1)
413 FIELD(MB_FATAL, CPU2, 1, 1)
414 FIELD(MB_FATAL, CPU1, 0, 1)
415REG32(MB1_FAULT_STATUS, 0x530)
416 FIELD(MB1_FAULT_STATUS, CPU3, 14, 1)
417 FIELD(MB1_FAULT_STATUS, CPU2, 13, 1)
418 FIELD(MB1_FAULT_STATUS, CPU1, 12, 1)
419 FIELD(MB1_FAULT_STATUS, FT_STATE, 10, 2)
420 FIELD(MB1_FAULT_STATUS, WDT_EXP, 9, 1)
421 FIELD(MB1_FAULT_STATUS, UNCORR_ERR, 8, 1)
422 FIELD(MB1_FAULT_STATUS, VOTER_ERR, 7, 1)
423 FIELD(MB1_FAULT_STATUS, FTL_MISMATCH, 4, 3)
424 FIELD(MB1_FAULT_STATUS, LS_RECOVER, 3, 1)
425 FIELD(MB1_FAULT_STATUS, LS_MISMATCH, 0, 3)
426REG32(MB2_FAULT_STATUS, 0x534)
427 FIELD(MB2_FAULT_STATUS, CPU3, 14, 1)
428 FIELD(MB2_FAULT_STATUS, CPU2, 13, 1)
429 FIELD(MB2_FAULT_STATUS, CPU1, 12, 1)
430 FIELD(MB2_FAULT_STATUS, FT_STATE, 10, 2)
431 FIELD(MB2_FAULT_STATUS, WDT_EXP, 9, 1)
432 FIELD(MB2_FAULT_STATUS, UNCORR_ERR, 8, 1)
433 FIELD(MB2_FAULT_STATUS, VOTER_ERR, 7, 1)
434 FIELD(MB2_FAULT_STATUS, FTL_MISMATCH, 4, 3)
435 FIELD(MB2_FAULT_STATUS, LS_RECOVER, 3, 1)
436 FIELD(MB2_FAULT_STATUS, LS_MISMATCH, 0, 3)
437REG32(MB3_FAULT_STATUS, 0x538)
438 FIELD(MB3_FAULT_STATUS, CPU3, 14, 1)
439 FIELD(MB3_FAULT_STATUS, CPU2, 13, 1)
440 FIELD(MB3_FAULT_STATUS, CPU1, 12, 1)
441 FIELD(MB3_FAULT_STATUS, FT_STATE, 10, 2)
442 FIELD(MB3_FAULT_STATUS, WDT_EXP, 9, 1)
443 FIELD(MB3_FAULT_STATUS, UNCORR_ERR, 8, 1)
444 FIELD(MB3_FAULT_STATUS, VOTER_ERR, 7, 1)
445 FIELD(MB3_FAULT_STATUS, FTL_MISMATCH, 4, 3)
446 FIELD(MB3_FAULT_STATUS, LS_RECOVER, 3, 1)
447 FIELD(MB3_FAULT_STATUS, LS_MISMATCH, 0, 3)
448REG32(PSM_DEBUG_CTRL, 0x540)
449 FIELD(PSM_DEBUG_CTRL, EN, 0, 1)
450REG32(WAKEUP_IRQ_STATUS, 0x700)
451 FIELD(WAKEUP_IRQ_STATUS, INTFPD, 27, 1)
452 FIELD(WAKEUP_IRQ_STATUS, INTLPD, 26, 1)
453 FIELD(WAKEUP_IRQ_STATUS, FPD_DBG, 25, 1)
454 FIELD(WAKEUP_IRQ_STATUS, R5S_DBG, 24, 1)
455 FIELD(WAKEUP_IRQ_STATUS, ACPU1_DBG, 21, 1)
456 FIELD(WAKEUP_IRQ_STATUS, ACPU0_DBG, 20, 1)
457 FIELD(WAKEUP_IRQ_STATUS, ACPU1_CORESIGHT, 17, 1)
458 FIELD(WAKEUP_IRQ_STATUS, ACPU0_CORESIGHT, 16, 1)
459 FIELD(WAKEUP_IRQ_STATUS, MIO5, 15, 1)
460 FIELD(WAKEUP_IRQ_STATUS, MIO4, 14, 1)
461 FIELD(WAKEUP_IRQ_STATUS, MIO3, 13, 1)
462 FIELD(WAKEUP_IRQ_STATUS, MIO2, 12, 1)
463 FIELD(WAKEUP_IRQ_STATUS, MIO1, 11, 1)
464 FIELD(WAKEUP_IRQ_STATUS, MIO0, 10, 1)
465 FIELD(WAKEUP_IRQ_STATUS, USB0, 6, 1)
466 FIELD(WAKEUP_IRQ_STATUS, R51, 5, 1)
467 FIELD(WAKEUP_IRQ_STATUS, R50, 4, 1)
468 FIELD(WAKEUP_IRQ_STATUS, ACPU1, 1, 1)
469 FIELD(WAKEUP_IRQ_STATUS, ACPU0, 0, 1)
470REG32(WAKEUP_IRQ_MASK, 0x704)
471 FIELD(WAKEUP_IRQ_MASK, INTFPD, 27, 1)
472 FIELD(WAKEUP_IRQ_MASK, INTLPD, 26, 1)
473 FIELD(WAKEUP_IRQ_MASK, FPD_DBG, 25, 1)
474 FIELD(WAKEUP_IRQ_MASK, R5S_DBG, 24, 1)
475 FIELD(WAKEUP_IRQ_MASK, ACPU1_DBG, 21, 1)
476 FIELD(WAKEUP_IRQ_MASK, ACPU0_DBG, 20, 1)
477 FIELD(WAKEUP_IRQ_MASK, ACPU1_CORESIGHT, 17, 1)
478 FIELD(WAKEUP_IRQ_MASK, ACPU0_CORESIGHT, 16, 1)
479 FIELD(WAKEUP_IRQ_MASK, MIO5, 15, 1)
480 FIELD(WAKEUP_IRQ_MASK, MIO4, 14, 1)
481 FIELD(WAKEUP_IRQ_MASK, MIO3, 13, 1)
482 FIELD(WAKEUP_IRQ_MASK, MIO2, 12, 1)
483 FIELD(WAKEUP_IRQ_MASK, MIO1, 11, 1)
484 FIELD(WAKEUP_IRQ_MASK, MIO0, 10, 1)
485 FIELD(WAKEUP_IRQ_MASK, USB0, 6, 1)
486 FIELD(WAKEUP_IRQ_MASK, R51, 5, 1)
487 FIELD(WAKEUP_IRQ_MASK, R50, 4, 1)
488 FIELD(WAKEUP_IRQ_MASK, ACPU1, 1, 1)
489 FIELD(WAKEUP_IRQ_MASK, ACPU0, 0, 1)
490REG32(WAKEUP_IRQ_EN, 0x708)
491 FIELD(WAKEUP_IRQ_EN, INTFPD, 27, 1)
492 FIELD(WAKEUP_IRQ_EN, INTLPD, 26, 1)
493 FIELD(WAKEUP_IRQ_EN, FPD_DBG, 25, 1)
494 FIELD(WAKEUP_IRQ_EN, R5S_DBG, 24, 1)
495 FIELD(WAKEUP_IRQ_EN, ACPU1_DBG, 21, 1)
496 FIELD(WAKEUP_IRQ_EN, ACPU0_DBG, 20, 1)
497 FIELD(WAKEUP_IRQ_EN, ACPU1_CORESIGHT, 17, 1)
498 FIELD(WAKEUP_IRQ_EN, ACPU0_CORESIGHT, 16, 1)
499 FIELD(WAKEUP_IRQ_EN, MIO5, 15, 1)
500 FIELD(WAKEUP_IRQ_EN, MIO4, 14, 1)
501 FIELD(WAKEUP_IRQ_EN, MIO3, 13, 1)
502 FIELD(WAKEUP_IRQ_EN, MIO2, 12, 1)
503 FIELD(WAKEUP_IRQ_EN, MIO1, 11, 1)
504 FIELD(WAKEUP_IRQ_EN, MIO0, 10, 1)
505 FIELD(WAKEUP_IRQ_EN, USB0, 6, 1)
506 FIELD(WAKEUP_IRQ_EN, R51, 5, 1)
507 FIELD(WAKEUP_IRQ_EN, R50, 4, 1)
508 FIELD(WAKEUP_IRQ_EN, ACPU1, 1, 1)
509 FIELD(WAKEUP_IRQ_EN, ACPU0, 0, 1)
510REG32(WAKEUP_IRQ_DIS, 0x70c)
511 FIELD(WAKEUP_IRQ_DIS, INTFPD, 27, 1)
512 FIELD(WAKEUP_IRQ_DIS, INTLPD, 26, 1)
513 FIELD(WAKEUP_IRQ_DIS, FPD_DBG, 25, 1)
514 FIELD(WAKEUP_IRQ_DIS, R5S_DBG, 24, 1)
515 FIELD(WAKEUP_IRQ_DIS, ACPU1_DBG, 21, 1)
516 FIELD(WAKEUP_IRQ_DIS, ACPU0_DBG, 20, 1)
517 FIELD(WAKEUP_IRQ_DIS, ACPU1_CORESIGHT, 17, 1)
518 FIELD(WAKEUP_IRQ_DIS, ACPU0_CORESIGHT, 16, 1)
519 FIELD(WAKEUP_IRQ_DIS, MIO5, 15, 1)
520 FIELD(WAKEUP_IRQ_DIS, MIO4, 14, 1)
521 FIELD(WAKEUP_IRQ_DIS, MIO3, 13, 1)
522 FIELD(WAKEUP_IRQ_DIS, MIO2, 12, 1)
523 FIELD(WAKEUP_IRQ_DIS, MIO1, 11, 1)
524 FIELD(WAKEUP_IRQ_DIS, MIO0, 10, 1)
525 FIELD(WAKEUP_IRQ_DIS, USB0, 6, 1)
526 FIELD(WAKEUP_IRQ_DIS, R51, 5, 1)
527 FIELD(WAKEUP_IRQ_DIS, R50, 4, 1)
528 FIELD(WAKEUP_IRQ_DIS, ACPU1, 1, 1)
529 FIELD(WAKEUP_IRQ_DIS, ACPU0, 0, 1)
530REG32(WAKEUP_IRQ_TRIG, 0x710)
531 FIELD(WAKEUP_IRQ_TRIG, INTFPD, 27, 1)
532 FIELD(WAKEUP_IRQ_TRIG, INTLPD, 26, 1)
533 FIELD(WAKEUP_IRQ_TRIG, FPD_DBG, 25, 1)
534 FIELD(WAKEUP_IRQ_TRIG, R5S_DBG, 24, 1)
535 FIELD(WAKEUP_IRQ_TRIG, ACPU1_DBG, 21, 1)
536 FIELD(WAKEUP_IRQ_TRIG, ACPU0_DBG, 20, 1)
537 FIELD(WAKEUP_IRQ_TRIG, ACPU1_CORESIGHT, 17, 1)
538 FIELD(WAKEUP_IRQ_TRIG, ACPU0_CORESIGHT, 16, 1)
539 FIELD(WAKEUP_IRQ_TRIG, MIO5, 15, 1)
540 FIELD(WAKEUP_IRQ_TRIG, MIO4, 14, 1)
541 FIELD(WAKEUP_IRQ_TRIG, MIO3, 13, 1)
542 FIELD(WAKEUP_IRQ_TRIG, MIO2, 12, 1)
543 FIELD(WAKEUP_IRQ_TRIG, MIO1, 11, 1)
544 FIELD(WAKEUP_IRQ_TRIG, MIO0, 10, 1)
545 FIELD(WAKEUP_IRQ_TRIG, USB0, 6, 1)
546 FIELD(WAKEUP_IRQ_TRIG, R51, 5, 1)
547 FIELD(WAKEUP_IRQ_TRIG, R50, 4, 1)
548 FIELD(WAKEUP_IRQ_TRIG, ACPU1, 1, 1)
549 FIELD(WAKEUP_IRQ_TRIG, ACPU0, 0, 1)
550REG32(PWR_CTRL_IRQ_STATUS, 0x714)
551 FIELD(PWR_CTRL_IRQ_STATUS, FPD_SUPPLY, 24, 1)
552 FIELD(PWR_CTRL_IRQ_STATUS, APU1_DBG_RST, 21, 1)
553 FIELD(PWR_CTRL_IRQ_STATUS, APU0_DBG_RST, 20, 1)
554 FIELD(PWR_CTRL_IRQ_STATUS, APU1_RST, 17, 1)
555 FIELD(PWR_CTRL_IRQ_STATUS, APU0_RST, 16, 1)
556 FIELD(PWR_CTRL_IRQ_STATUS, RPU0_DBG, 8, 1)
557 FIELD(PWR_CTRL_IRQ_STATUS, R51, 5, 1)
558 FIELD(PWR_CTRL_IRQ_STATUS, R50, 4, 1)
559 FIELD(PWR_CTRL_IRQ_STATUS, ACPU1, 1, 1)
560 FIELD(PWR_CTRL_IRQ_STATUS, ACPU0, 0, 1)
561REG32(PWR_CTRL_IRQ_MASK, 0x718)
562 FIELD(PWR_CTRL_IRQ_MASK, FPD_SUPPLY, 24, 1)
563 FIELD(PWR_CTRL_IRQ_MASK, APU1_DBG_RST, 21, 1)
564 FIELD(PWR_CTRL_IRQ_MASK, APU0_DBG_RST, 20, 1)
565 FIELD(PWR_CTRL_IRQ_MASK, APU1_RST, 17, 1)
566 FIELD(PWR_CTRL_IRQ_MASK, APU0_RST, 16, 1)
567 FIELD(PWR_CTRL_IRQ_MASK, RPU0_DBG, 8, 1)
568 FIELD(PWR_CTRL_IRQ_MASK, R51, 5, 1)
569 FIELD(PWR_CTRL_IRQ_MASK, R50, 4, 1)
570 FIELD(PWR_CTRL_IRQ_MASK, ACPU1, 1, 1)
571 FIELD(PWR_CTRL_IRQ_MASK, ACPU0, 0, 1)
572REG32(PWR_CTRL_IRQ_EN, 0x71c)
573 FIELD(PWR_CTRL_IRQ_EN, FPD_SUPPLY, 24, 1)
574 FIELD(PWR_CTRL_IRQ_EN, APU1_DBG_RST, 21, 1)
575 FIELD(PWR_CTRL_IRQ_EN, APU0_DBG_RST, 20, 1)
576 FIELD(PWR_CTRL_IRQ_EN, APU1_RST, 17, 1)
577 FIELD(PWR_CTRL_IRQ_EN, APU0_RST, 16, 1)
578 FIELD(PWR_CTRL_IRQ_EN, RPU0_DBG, 8, 1)
579 FIELD(PWR_CTRL_IRQ_EN, R51, 5, 1)
580 FIELD(PWR_CTRL_IRQ_EN, R50, 4, 1)
581 FIELD(PWR_CTRL_IRQ_EN, ACPU1, 1, 1)
582 FIELD(PWR_CTRL_IRQ_EN, ACPU0, 0, 1)
583REG32(PWR_CTRL_IRQ_DIS, 0x720)
584 FIELD(PWR_CTRL_IRQ_DIS, FPD_SUPPLY, 24, 1)
585 FIELD(PWR_CTRL_IRQ_DIS, APU1_DBG_RST, 21, 1)
586 FIELD(PWR_CTRL_IRQ_DIS, APU0_DBG_RST, 20, 1)
587 FIELD(PWR_CTRL_IRQ_DIS, APU1_RST, 17, 1)
588 FIELD(PWR_CTRL_IRQ_DIS, APU0_RST, 16, 1)
589 FIELD(PWR_CTRL_IRQ_DIS, RPU0_DBG, 8, 1)
590 FIELD(PWR_CTRL_IRQ_DIS, R51, 5, 1)
591 FIELD(PWR_CTRL_IRQ_DIS, R50, 4, 1)
592 FIELD(PWR_CTRL_IRQ_DIS, ACPU1, 1, 1)
593 FIELD(PWR_CTRL_IRQ_DIS, ACPU0, 0, 1)
594REG32(PWR_CTRL_IRQ_TRIG, 0x724)
595 FIELD(PWR_CTRL_IRQ_TRIG, FPD_SUPPLY, 24, 1)
596 FIELD(PWR_CTRL_IRQ_TRIG, APU1_DBG_RST, 21, 1)
597 FIELD(PWR_CTRL_IRQ_TRIG, APU0_DBG_RST, 20, 1)
598 FIELD(PWR_CTRL_IRQ_TRIG, APU1_RST, 17, 1)
599 FIELD(PWR_CTRL_IRQ_TRIG, APU0_RST, 16, 1)
600 FIELD(PWR_CTRL_IRQ_TRIG, RPU0_DBG, 8, 1)
601 FIELD(PWR_CTRL_IRQ_TRIG, R51, 5, 1)
602 FIELD(PWR_CTRL_IRQ_TRIG, R50, 4, 1)
603 FIELD(PWR_CTRL_IRQ_TRIG, ACPU1, 1, 1)
604 FIELD(PWR_CTRL_IRQ_TRIG, ACPU0, 0, 1)
605REG32(DBG_PWR_ACK, 0x808)
606 FIELD(DBG_PWR_ACK, FPD, 3, 1)
607 FIELD(DBG_PWR_ACK, R5S, 2, 1)
608 FIELD(DBG_PWR_ACK, A72_1, 1, 1)
609 FIELD(DBG_PWR_ACK, A72_0, 0, 1)
610REG32(MBIST_RSTN, 0x900)
611 FIELD(MBIST_RSTN, INT_FPD, 4, 1)
612 FIELD(MBIST_RSTN, CCI, 3, 1)
613 FIELD(MBIST_RSTN, CPU1, 2, 1)
614 FIELD(MBIST_RSTN, CPU0, 1, 1)
615 FIELD(MBIST_RSTN, APU, 0, 1)
616REG32(MBIST_PG_EN, 0x904)
617 FIELD(MBIST_PG_EN, INT_FPD, 4, 1)
618 FIELD(MBIST_PG_EN, CCI, 3, 1)
619 FIELD(MBIST_PG_EN, CPU1, 2, 1)
620 FIELD(MBIST_PG_EN, CPU0, 1, 1)
621 FIELD(MBIST_PG_EN, APU, 0, 1)
622REG32(MBIST_SETUP, 0x908)
623 FIELD(MBIST_SETUP, INT_FPD, 4, 1)
624 FIELD(MBIST_SETUP, CCI, 3, 1)
625 FIELD(MBIST_SETUP, CPU1, 2, 1)
626 FIELD(MBIST_SETUP, CPU0, 1, 1)
627 FIELD(MBIST_SETUP, APU, 0, 1)
628REG32(MBIST_DONE, 0x910)
629 FIELD(MBIST_DONE, INT_FPD, 4, 1)
630 FIELD(MBIST_DONE, CCI, 3, 1)
631 FIELD(MBIST_DONE, CPU1, 2, 1)
632 FIELD(MBIST_DONE, CPU0, 1, 1)
633 FIELD(MBIST_DONE, APU, 0, 1)
634REG32(MBIST_GO, 0x914)
635 FIELD(MBIST_GO, INT_FPD, 4, 1)
636 FIELD(MBIST_GO, CCI, 3, 1)
637 FIELD(MBIST_GO, CPU1, 2, 1)
638 FIELD(MBIST_GO, CPU0, 1, 1)
639 FIELD(MBIST_GO, APU, 0, 1)
640REG32(SCAN_CLEAR_CPU0, 0x920)
641 FIELD(SCAN_CLEAR_CPU0, PASS, 2, 1)
642 FIELD(SCAN_CLEAR_CPU0, DONE, 1, 1)
643 FIELD(SCAN_CLEAR_CPU0, TRIGGER, 0, 1)
644REG32(SCAN_CLEAR_CPU1, 0x924)
645 FIELD(SCAN_CLEAR_CPU1, PASS, 2, 1)
646 FIELD(SCAN_CLEAR_CPU1, DONE, 1, 1)
647 FIELD(SCAN_CLEAR_CPU1, TRIGGER, 0, 1)
648REG32(SCAN_CLEAR_APU, 0x928)
649 FIELD(SCAN_CLEAR_APU, PASS, 2, 1)
650 FIELD(SCAN_CLEAR_APU, DONE, 1, 1)
651 FIELD(SCAN_CLEAR_APU, TRIGGER, 0, 1)
652REG32(SCAN_CLEAR_FPD, 0x92c)
653 FIELD(SCAN_CLEAR_FPD, PASS, 2, 1)
654 FIELD(SCAN_CLEAR_FPD, DONE, 1, 1)
655 FIELD(SCAN_CLEAR_FPD, TRIGGER, 0, 1)
656REG32(SAFETY_CHK, 0xa00)
657
658#define PSM_GLOBAL_REG_R_MAX (R_SAFETY_CHK + 1)
659
660typedef struct PSM_GLOBAL_REG {
661 SysBusDevice parent_obj;
662 MemoryRegion iomem;
663 qemu_irq irq_req_pwrdwn_int;
664 qemu_irq irq_wakeup_irq;
665 qemu_irq irq_req_swrst_int;
666 qemu_irq irq_req_pwrup_int;
667 qemu_irq irq_req_aux_int;
668 qemu_irq irq_addr_error_int;
669 qemu_irq irq_pwr_ctrl_irq;
670 qemu_irq irq_req_iso_int;
671
672 uint32_t regs[PSM_GLOBAL_REG_R_MAX];
673 RegisterInfo regs_info[PSM_GLOBAL_REG_R_MAX];
674} PSM_GLOBAL_REG;
675
676static void req_pwrdwn_int_update_irq(PSM_GLOBAL_REG *s)
677{
678 bool pending;
679
680 pending = s->regs[R_REQ_PWRDWN_STATUS] & ~s->regs[R_REQ_PWRDWN_INT_MASK];
681 qemu_set_irq(s->irq_req_pwrdwn_int, pending);
682}
683
684static void req_pwrdwn_status_postw(RegisterInfo *reg, uint64_t val64)
685{
686 PSM_GLOBAL_REG *s = XILINX_PSM_GLOBAL_REG(reg->opaque);
687 req_pwrdwn_int_update_irq(s);
688}
689
690static uint64_t req_pwrdwn_int_en_prew(RegisterInfo *reg, uint64_t val64)
691{
692 PSM_GLOBAL_REG *s = XILINX_PSM_GLOBAL_REG(reg->opaque);
693 uint32_t val = val64;
694
695 s->regs[R_REQ_PWRDWN_INT_MASK] &= ~val;
696 req_pwrdwn_int_update_irq(s);
697 return 0;
698}
699
700static uint64_t req_pwrdwn_int_dis_prew(RegisterInfo *reg, uint64_t val64)
701{
702 PSM_GLOBAL_REG *s = XILINX_PSM_GLOBAL_REG(reg->opaque);
703 uint32_t val = val64;
704
705 s->regs[R_REQ_PWRDWN_INT_MASK] |= val;
706 req_pwrdwn_int_update_irq(s);
707 return 0;
708}
709
710static uint64_t req_pwrdwn_trig_prew(RegisterInfo *reg, uint64_t val64)
711{
712 PSM_GLOBAL_REG *s = XILINX_PSM_GLOBAL_REG(reg->opaque);
713 uint32_t val = val64;
714
715 s->regs[R_REQ_PWRDWN_STATUS] |= val;
716 req_pwrdwn_int_update_irq(s);
717 return 0;
718}
719
720static void wakeup_irq_update_irq(PSM_GLOBAL_REG *s)
721{
722 bool pending = s->regs[R_WAKEUP_IRQ_STATUS] & ~s->regs[R_WAKEUP_IRQ_MASK];
723 qemu_set_irq(s->irq_wakeup_irq, pending);
724}
725
726static void wakeup_irq_status_postw(RegisterInfo *reg, uint64_t val64)
727{
728 PSM_GLOBAL_REG *s = XILINX_PSM_GLOBAL_REG(reg->opaque);
729 wakeup_irq_update_irq(s);
730}
731
732static uint64_t wakeup_irq_en_prew(RegisterInfo *reg, uint64_t val64)
733{
734 PSM_GLOBAL_REG *s = XILINX_PSM_GLOBAL_REG(reg->opaque);
735 uint32_t val = val64;
736
737 s->regs[R_WAKEUP_IRQ_MASK] &= ~val;
738 wakeup_irq_update_irq(s);
739 return 0;
740}
741
742static uint64_t wakeup_irq_dis_prew(RegisterInfo *reg, uint64_t val64)
743{
744 PSM_GLOBAL_REG *s = XILINX_PSM_GLOBAL_REG(reg->opaque);
745 uint32_t val = val64;
746
747 s->regs[R_WAKEUP_IRQ_MASK] |= val;
748 wakeup_irq_update_irq(s);
749 return 0;
750}
751
752static uint64_t wakeup_irq_trig_prew(RegisterInfo *reg, uint64_t val64)
753{
754 PSM_GLOBAL_REG *s = XILINX_PSM_GLOBAL_REG(reg->opaque);
755 uint32_t val = val64;
756
757 s->regs[R_WAKEUP_IRQ_STATUS] |= val;
758 wakeup_irq_update_irq(s);
759 return 0;
760}
761
762static void req_swrst_int_update_irq(PSM_GLOBAL_REG *s)
763{
764 bool pending = s->regs[R_REQ_SWRST_STATUS] & ~s->regs[R_REQ_SWRST_INT_MASK];
765 qemu_set_irq(s->irq_req_swrst_int, pending);
766}
767
768static void req_swrst_status_postw(RegisterInfo *reg, uint64_t val64)
769{
770 PSM_GLOBAL_REG *s = XILINX_PSM_GLOBAL_REG(reg->opaque);
771 req_swrst_int_update_irq(s);
772}
773
774static uint64_t req_swrst_int_en_prew(RegisterInfo *reg, uint64_t val64)
775{
776 PSM_GLOBAL_REG *s = XILINX_PSM_GLOBAL_REG(reg->opaque);
777 uint32_t val = val64;
778
779 s->regs[R_REQ_SWRST_INT_MASK] &= ~val;
780 req_swrst_int_update_irq(s);
781 return 0;
782}
783
784static uint64_t req_swrst_int_dis_prew(RegisterInfo *reg, uint64_t val64)
785{
786 PSM_GLOBAL_REG *s = XILINX_PSM_GLOBAL_REG(reg->opaque);
787 uint32_t val = val64;
788
789 s->regs[R_REQ_SWRST_INT_MASK] |= val;
790 req_swrst_int_update_irq(s);
791 return 0;
792}
793
794static uint64_t req_swrst_trig_prew(RegisterInfo *reg, uint64_t val64)
795{
796 PSM_GLOBAL_REG *s = XILINX_PSM_GLOBAL_REG(reg->opaque);
797 uint32_t val = val64;
798
799 s->regs[R_REQ_SWRST_STATUS] |= val;
800 req_swrst_int_update_irq(s);
801 return 0;
802}
803
804static void req_pwrup_int_update_irq(PSM_GLOBAL_REG *s)
805{
806 bool pending = s->regs[R_REQ_PWRUP_STATUS] & ~s->regs[R_REQ_PWRUP_INT_MASK];
807 qemu_set_irq(s->irq_req_pwrup_int, pending);
808}
809
810static void req_pwrup_status_postw(RegisterInfo *reg, uint64_t val64)
811{
812 PSM_GLOBAL_REG *s = XILINX_PSM_GLOBAL_REG(reg->opaque);
813 req_pwrup_int_update_irq(s);
814}
815
816static uint64_t req_pwrup_int_en_prew(RegisterInfo *reg, uint64_t val64)
817{
818 PSM_GLOBAL_REG *s = XILINX_PSM_GLOBAL_REG(reg->opaque);
819 uint32_t val = val64;
820
821 s->regs[R_REQ_PWRUP_INT_MASK] &= ~val;
822 req_pwrup_int_update_irq(s);
823 return 0;
824}
825
826static uint64_t req_pwrup_int_dis_prew(RegisterInfo *reg, uint64_t val64)
827{
828 PSM_GLOBAL_REG *s = XILINX_PSM_GLOBAL_REG(reg->opaque);
829 uint32_t val = val64;
830
831 s->regs[R_REQ_PWRUP_INT_MASK] |= val;
832 req_pwrup_int_update_irq(s);
833 return 0;
834}
835
836static uint64_t req_pwrup_trig_prew(RegisterInfo *reg, uint64_t val64)
837{
838 PSM_GLOBAL_REG *s = XILINX_PSM_GLOBAL_REG(reg->opaque);
839 uint32_t val = val64;
840
841 s->regs[R_REQ_PWRUP_STATUS] |= val;
842 req_pwrup_int_update_irq(s);
843 return 0;
844}
845
846static void req_aux_int_update_irq(PSM_GLOBAL_REG *s)
847{
848 bool pending = s->regs[R_REQ_AUX_STATUS] & ~s->regs[R_REQ_AUX_INT_MASK];
849 qemu_set_irq(s->irq_req_aux_int, pending);
850}
851
852static void req_aux_status_postw(RegisterInfo *reg, uint64_t val64)
853{
854 PSM_GLOBAL_REG *s = XILINX_PSM_GLOBAL_REG(reg->opaque);
855 req_aux_int_update_irq(s);
856}
857
858static uint64_t req_aux_int_en_prew(RegisterInfo *reg, uint64_t val64)
859{
860 PSM_GLOBAL_REG *s = XILINX_PSM_GLOBAL_REG(reg->opaque);
861 uint32_t val = val64;
862
863 s->regs[R_REQ_AUX_INT_MASK] &= ~val;
864 req_aux_int_update_irq(s);
865 return 0;
866}
867
868static uint64_t req_aux_int_dis_prew(RegisterInfo *reg, uint64_t val64)
869{
870 PSM_GLOBAL_REG *s = XILINX_PSM_GLOBAL_REG(reg->opaque);
871 uint32_t val = val64;
872
873 s->regs[R_REQ_AUX_INT_MASK] |= val;
874 req_aux_int_update_irq(s);
875 return 0;
876}
877
878static uint64_t req_aux_trig_prew(RegisterInfo *reg, uint64_t val64)
879{
880 PSM_GLOBAL_REG *s = XILINX_PSM_GLOBAL_REG(reg->opaque);
881 uint32_t val = val64;
882
883 s->regs[R_REQ_AUX_STATUS] |= val;
884 req_aux_int_update_irq(s);
885 return 0;
886}
887
888static void addr_error_int_update_irq(PSM_GLOBAL_REG *s)
889{
890 bool pending;
891
892 pending = s->regs[R_ADDR_ERROR_STATUS] & ~s->regs[R_ADDR_ERROR_INT_MASK];
893 qemu_set_irq(s->irq_addr_error_int, pending);
894}
895
896static void addr_error_status_postw(RegisterInfo *reg, uint64_t val64)
897{
898 PSM_GLOBAL_REG *s = XILINX_PSM_GLOBAL_REG(reg->opaque);
899 addr_error_int_update_irq(s);
900}
901
902static uint64_t addr_error_int_en_prew(RegisterInfo *reg, uint64_t val64)
903{
904 PSM_GLOBAL_REG *s = XILINX_PSM_GLOBAL_REG(reg->opaque);
905 uint32_t val = val64;
906
907 s->regs[R_ADDR_ERROR_INT_MASK] &= ~val;
908 addr_error_int_update_irq(s);
909 return 0;
910}
911
912static uint64_t addr_error_int_dis_prew(RegisterInfo *reg, uint64_t val64)
913{
914 PSM_GLOBAL_REG *s = XILINX_PSM_GLOBAL_REG(reg->opaque);
915 uint32_t val = val64;
916
917 s->regs[R_ADDR_ERROR_INT_MASK] |= val;
918 addr_error_int_update_irq(s);
919 return 0;
920}
921
922static void pwr_ctrl_irq_update_irq(PSM_GLOBAL_REG *s)
923{
924 bool pending;
925
926 pending = s->regs[R_PWR_CTRL_IRQ_STATUS] & ~s->regs[R_PWR_CTRL_IRQ_MASK];
927 qemu_set_irq(s->irq_pwr_ctrl_irq, pending);
928}
929
930static void pwr_ctrl_irq_status_postw(RegisterInfo *reg, uint64_t val64)
931{
932 PSM_GLOBAL_REG *s = XILINX_PSM_GLOBAL_REG(reg->opaque);
933 pwr_ctrl_irq_update_irq(s);
934}
935
936static uint64_t pwr_ctrl_irq_en_prew(RegisterInfo *reg, uint64_t val64)
937{
938 PSM_GLOBAL_REG *s = XILINX_PSM_GLOBAL_REG(reg->opaque);
939 uint32_t val = val64;
940
941 s->regs[R_PWR_CTRL_IRQ_MASK] &= ~val;
942 pwr_ctrl_irq_update_irq(s);
943 return 0;
944}
945
946static uint64_t pwr_ctrl_irq_dis_prew(RegisterInfo *reg, uint64_t val64)
947{
948 PSM_GLOBAL_REG *s = XILINX_PSM_GLOBAL_REG(reg->opaque);
949 uint32_t val = val64;
950
951 s->regs[R_PWR_CTRL_IRQ_MASK] |= val;
952 pwr_ctrl_irq_update_irq(s);
953 return 0;
954}
955
956static uint64_t pwr_ctrl_irq_trig_prew(RegisterInfo *reg, uint64_t val64)
957{
958 PSM_GLOBAL_REG *s = XILINX_PSM_GLOBAL_REG(reg->opaque);
959 uint32_t val = val64;
960
961 s->regs[R_PWR_CTRL_IRQ_STATUS] |= val;
962 pwr_ctrl_irq_update_irq(s);
963 return 0;
964}
965
966static void req_iso_int_update_irq(PSM_GLOBAL_REG *s)
967{
968 bool pending = s->regs[R_REQ_ISO_STATUS] & ~s->regs[R_REQ_ISO_INT_MASK];
969 qemu_set_irq(s->irq_req_iso_int, pending);
970}
971
972static void req_iso_status_postw(RegisterInfo *reg, uint64_t val64)
973{
974 PSM_GLOBAL_REG *s = XILINX_PSM_GLOBAL_REG(reg->opaque);
975 req_iso_int_update_irq(s);
976}
977
978static uint64_t req_iso_int_en_prew(RegisterInfo *reg, uint64_t val64)
979{
980 PSM_GLOBAL_REG *s = XILINX_PSM_GLOBAL_REG(reg->opaque);
981 uint32_t val = val64;
982
983 s->regs[R_REQ_ISO_INT_MASK] &= ~val;
984 req_iso_int_update_irq(s);
985 return 0;
986}
987
988static uint64_t req_iso_int_dis_prew(RegisterInfo *reg, uint64_t val64)
989{
990 PSM_GLOBAL_REG *s = XILINX_PSM_GLOBAL_REG(reg->opaque);
991 uint32_t val = val64;
992
993 s->regs[R_REQ_ISO_INT_MASK] |= val;
994 req_iso_int_update_irq(s);
995 return 0;
996}
997
998static uint64_t req_iso_trig_prew(RegisterInfo *reg, uint64_t val64)
999{
1000 PSM_GLOBAL_REG *s = XILINX_PSM_GLOBAL_REG(reg->opaque);
1001 uint32_t val = val64;
1002
1003 s->regs[R_REQ_ISO_STATUS] |= val;
1004 req_iso_int_update_irq(s);
1005 return 0;
1006}
1007
1008static uint64_t scan_clear_fpd_prew(RegisterInfo *reg, uint64_t val64)
1009{
1010 uint32_t val = (uint32_t)val64;
1011
1012
1013
1014
1015
1016 if (FIELD_EX32(val, SCAN_CLEAR_FPD, TRIGGER)) {
1017 val = 0;
1018 val = FIELD_DP32(val, SCAN_CLEAR_FPD, PASS, 1);
1019 val = FIELD_DP32(val, SCAN_CLEAR_FPD, DONE, 1);
1020 }
1021
1022 return val;
1023}
1024
1025#define MBIST_TRIG(dev) \
1026 if (FIELD_EX32(val, MBIST_PG_EN, dev) && \
1027 !FIELD_EX32(curr_regval, MBIST_PG_EN, dev)) { \
1028 setup = ARRAY_FIELD_EX32(s->regs, MBIST_SETUP, dev); \
1029 rst = !ARRAY_FIELD_EX32(s->regs, MBIST_RSTN, dev); \
1030 if (setup && !rst) { \
1031 ARRAY_FIELD_DP32(s->regs, MBIST_DONE, dev, 1); \
1032 ARRAY_FIELD_DP32(s->regs, MBIST_GO, dev, 1); \
1033 } \
1034 }
1035
1036static uint64_t mbist_pg_en_prew(RegisterInfo *reg, uint64_t val64)
1037{
1038 PSM_GLOBAL_REG *s = XILINX_PSM_GLOBAL_REG(reg->opaque);
1039 uint32_t val = val64;
1040 uint32_t curr_regval = s->regs[R_MBIST_PG_EN];
1041 bool rst;
1042 bool setup;
1043
1044
1045 MBIST_TRIG(INT_FPD);
1046 MBIST_TRIG(CCI);
1047 MBIST_TRIG(CPU0);
1048 MBIST_TRIG(CPU1);
1049 MBIST_TRIG(APU);
1050
1051 return val;
1052}
1053
1054static const RegisterAccessInfo psm_global_reg_regs_info[] = {
1055 { .name = "GLOBAL_CNTRL", .addr = A_GLOBAL_CNTRL,
1056 .reset = 0x8800,
1057 .rsvd = 0xfff800ed,
1058 .ro = 0xfffb00ed,
1059 },{ .name = "APU_PWR_STATUS_INIT", .addr = A_APU_PWR_STATUS_INIT,
1060 .rsvd = 0xfffffffc,
1061 .ro = 0xfffffffc,
1062 },{ .name = "ADDR_ERROR_STATUS", .addr = A_ADDR_ERROR_STATUS,
1063 .rsvd = 0xfffffffe,
1064 .ro = 0xfffffffe,
1065 .w1c = 0x1,
1066 .post_write = addr_error_status_postw,
1067 },{ .name = "ADDR_ERROR_INT_MASK", .addr = A_ADDR_ERROR_INT_MASK,
1068 .reset = 0x1,
1069 .rsvd = 0xfffffffe,
1070 .ro = 0xffffffff,
1071 },{ .name = "ADDR_ERROR_INT_EN", .addr = A_ADDR_ERROR_INT_EN,
1072 .pre_write = addr_error_int_en_prew,
1073 },{ .name = "ADDR_ERROR_INT_DIS", .addr = A_ADDR_ERROR_INT_DIS,
1074 .pre_write = addr_error_int_dis_prew,
1075 },{ .name = "PS_SW_ERR", .addr = A_PS_SW_ERR,
1076 },{ .name = "PSM_BOOT_SERV_ERR", .addr = A_PSM_BOOT_SERV_ERR,
1077 },{ .name = "GLOBAL_GEN_STORAGE0", .addr = A_GLOBAL_GEN_STORAGE0,
1078 },{ .name = "GLOBAL_GEN_STORAGE1", .addr = A_GLOBAL_GEN_STORAGE1,
1079 },{ .name = "GLOBAL_GEN_STORAGE2", .addr = A_GLOBAL_GEN_STORAGE2,
1080 },{ .name = "GLOBAL_GEN_STORAGE3", .addr = A_GLOBAL_GEN_STORAGE3,
1081 },{ .name = "GLOBAL_GEN_STORAGE4", .addr = A_GLOBAL_GEN_STORAGE4,
1082 },{ .name = "GLOBAL_GEN_STORAGE5", .addr = A_GLOBAL_GEN_STORAGE5,
1083 },{ .name = "GLOBAL_GEN_STORAGE6", .addr = A_GLOBAL_GEN_STORAGE6,
1084 },{ .name = "GLOBAL_GEN_STORAGE7", .addr = A_GLOBAL_GEN_STORAGE7,
1085 },{ .name = "PERS_GLOB_GEN_STORAGE0", .addr = A_PERS_GLOB_GEN_STORAGE0,
1086 },{ .name = "PERS_GLOB_GEN_STORAGE1", .addr = A_PERS_GLOB_GEN_STORAGE1,
1087 },{ .name = "PERS_GLOB_GEN_STORAGE2", .addr = A_PERS_GLOB_GEN_STORAGE2,
1088 },{ .name = "PERS_GLOB_GEN_STORAGE3", .addr = A_PERS_GLOB_GEN_STORAGE3,
1089 },{ .name = "PERS_GLOB_GEN_STORAGE4", .addr = A_PERS_GLOB_GEN_STORAGE4,
1090 },{ .name = "PERS_GLOB_GEN_STORAGE5", .addr = A_PERS_GLOB_GEN_STORAGE5,
1091 },{ .name = "PERS_GLOB_GEN_STORAGE6", .addr = A_PERS_GLOB_GEN_STORAGE6,
1092 },{ .name = "PERS_GLOB_GEN_STORAGE7", .addr = A_PERS_GLOB_GEN_STORAGE7,
1093 },{ .name = "PWR_STATE", .addr = A_PWR_STATE,
1094 .reset = 0x3ffc83,
1095 .rsvd = 0xff80037c,
1096 .ro = 0xffffffff,
1097 },{ .name = "AUX_PWR_STATE", .addr = A_AUX_PWR_STATE,
1098 .reset = 0xff080,
1099 .rsvd = 0xc7f00f7f,
1100 .ro = 0xffffffff,
1101 },{ .name = "REQ_PWRUP_STATUS", .addr = A_REQ_PWRUP_STATUS,
1102 .rsvd = 0xff800b7c,
1103 .w1c = 0xffffffff,
1104 .post_write = req_pwrup_status_postw,
1105 },{ .name = "REQ_PWRUP_INT_MASK", .addr = A_REQ_PWRUP_INT_MASK,
1106 .reset = 0x7ff483,
1107 .rsvd = 0xff800b7c,
1108 .ro = 0xffffffff,
1109 },{ .name = "REQ_PWRUP_INT_EN", .addr = A_REQ_PWRUP_INT_EN,
1110 .rsvd = 0xff800b7c,
1111 .pre_write = req_pwrup_int_en_prew,
1112 },{ .name = "REQ_PWRUP_INT_DIS", .addr = A_REQ_PWRUP_INT_DIS,
1113 .rsvd = 0xff800b7c,
1114 .pre_write = req_pwrup_int_dis_prew,
1115 },{ .name = "REQ_PWRUP_TRIG", .addr = A_REQ_PWRUP_TRIG,
1116 .rsvd = 0xff800b7c,
1117 .pre_write = req_pwrup_trig_prew,
1118 },{ .name = "REQ_PWRDWN_STATUS", .addr = A_REQ_PWRDWN_STATUS,
1119 .rsvd = 0xff800b7c,
1120 .w1c = 0xffffffff,
1121 .post_write = req_pwrdwn_status_postw,
1122 },{ .name = "REQ_PWRDWN_INT_MASK", .addr = A_REQ_PWRDWN_INT_MASK,
1123 .reset = 0x7ff483,
1124 .rsvd = 0xff800b7c,
1125 .ro = 0xffffffff,
1126 },{ .name = "REQ_PWRDWN_INT_EN", .addr = A_REQ_PWRDWN_INT_EN,
1127 .rsvd = 0xff800b7c,
1128 .pre_write = req_pwrdwn_int_en_prew,
1129 },{ .name = "REQ_PWRDWN_INT_DIS", .addr = A_REQ_PWRDWN_INT_DIS,
1130 .rsvd = 0xff800b7c,
1131 .pre_write = req_pwrdwn_int_dis_prew,
1132 },{ .name = "REQ_PWRDWN_TRIG", .addr = A_REQ_PWRDWN_TRIG,
1133 .rsvd = 0xff800b7c,
1134 .pre_write = req_pwrdwn_trig_prew,
1135 },{ .name = "REQ_ISO_STATUS", .addr = A_REQ_ISO_STATUS,
1136 .rsvd = 0xfffffffe,
1137 .ro = 0xfffffffe,
1138 .w1c = 0x1,
1139 .post_write = req_iso_status_postw,
1140 },{ .name = "REQ_ISO_INT_MASK", .addr = A_REQ_ISO_INT_MASK,
1141 .reset = 0x1,
1142 .rsvd = 0xfffffffe,
1143 .ro = 0xffffffff,
1144 },{ .name = "REQ_ISO_INT_EN", .addr = A_REQ_ISO_INT_EN,
1145 .pre_write = req_iso_int_en_prew,
1146 },{ .name = "REQ_ISO_INT_DIS", .addr = A_REQ_ISO_INT_DIS,
1147 .pre_write = req_iso_int_dis_prew,
1148 },{ .name = "REQ_ISO_TRIG", .addr = A_REQ_ISO_TRIG,
1149 .pre_write = req_iso_trig_prew,
1150 },{ .name = "REQ_SWRST_STATUS", .addr = A_REQ_SWRST_STATUS,
1151 .rsvd = 0x86cbffec,
1152 .ro = 0x86cbffec,
1153 .w1c = 0x79340013,
1154 .post_write = req_swrst_status_postw,
1155 },{ .name = "REQ_SWRST_INT_MASK", .addr = A_REQ_SWRST_INT_MASK,
1156 .reset = 0x79340013,
1157 .rsvd = 0x86cbffec,
1158 .ro = 0xffffffff,
1159 },{ .name = "REQ_SWRST_INT_EN", .addr = A_REQ_SWRST_INT_EN,
1160 .pre_write = req_swrst_int_en_prew,
1161 },{ .name = "REQ_SWRST_INT_DIS", .addr = A_REQ_SWRST_INT_DIS,
1162 .pre_write = req_swrst_int_dis_prew,
1163 },{ .name = "REQ_SWRST_TRIG", .addr = A_REQ_SWRST_TRIG,
1164 .pre_write = req_swrst_trig_prew,
1165 },{ .name = "REQ_AUX_STATUS", .addr = A_REQ_AUX_STATUS,
1166 .rsvd = 0xfffccb30,
1167 .ro = 0xfffccb30,
1168 .w1c = 0x334cf,
1169 .post_write = req_aux_status_postw,
1170 },{ .name = "REQ_AUX_INT_MASK", .addr = A_REQ_AUX_INT_MASK,
1171 .reset = 0x334cf,
1172 .rsvd = 0xfffccb30,
1173 .ro = 0xffffffff,
1174 },{ .name = "REQ_AUX_INT_EN", .addr = A_REQ_AUX_INT_EN,
1175 .pre_write = req_aux_int_en_prew,
1176 },{ .name = "REQ_AUX_INT_DIS", .addr = A_REQ_AUX_INT_DIS,
1177 .pre_write = req_aux_int_dis_prew,
1178 },{ .name = "REQ_AUX_TRIG", .addr = A_REQ_AUX_TRIG,
1179 .pre_write = req_aux_trig_prew,
1180 },{ .name = "MB_FATAL", .addr = A_MB_FATAL,
1181 .rsvd = 0xfffff8,
1182 .ro = 0xffffff,
1183 },{ .name = "MB1_FAULT_STATUS", .addr = A_MB1_FAULT_STATUS,
1184 .rsvd = 0xffff8000,
1185 .ro = 0xffffffff,
1186 },{ .name = "MB2_FAULT_STATUS", .addr = A_MB2_FAULT_STATUS,
1187 .rsvd = 0xffff8000,
1188 .ro = 0xffffffff,
1189 },{ .name = "MB3_FAULT_STATUS", .addr = A_MB3_FAULT_STATUS,
1190 .rsvd = 0xffff8000,
1191 .ro = 0xffffffff,
1192 },{ .name = "PSM_DEBUG_CTRL", .addr = A_PSM_DEBUG_CTRL,
1193 .reset = 0x1,
1194 .rsvd = 0xfffffffe,
1195 .ro = 0xfffffffe,
1196 },{ .name = "WAKEUP_IRQ_STATUS", .addr = A_WAKEUP_IRQ_STATUS,
1197 .rsvd = 0xf0cc038c,
1198 .w1c = 0xffffffff,
1199 .post_write = wakeup_irq_status_postw,
1200 },{ .name = "WAKEUP_IRQ_MASK", .addr = A_WAKEUP_IRQ_MASK,
1201 .reset = 0xf33fc73,
1202 .rsvd = 0xf0cc038c,
1203 .ro = 0xffffffff,
1204 },{ .name = "WAKEUP_IRQ_EN", .addr = A_WAKEUP_IRQ_EN,
1205 .rsvd = 0xf0cc038c,
1206 .pre_write = wakeup_irq_en_prew,
1207 },{ .name = "WAKEUP_IRQ_DIS", .addr = A_WAKEUP_IRQ_DIS,
1208 .rsvd = 0xf0cc038c,
1209 .pre_write = wakeup_irq_dis_prew,
1210 },{ .name = "WAKEUP_IRQ_TRIG", .addr = A_WAKEUP_IRQ_TRIG,
1211 .rsvd = 0xf0cc038c,
1212 .pre_write = wakeup_irq_trig_prew,
1213 },{ .name = "PWR_CTRL_IRQ_STATUS", .addr = A_PWR_CTRL_IRQ_STATUS,
1214 .rsvd = 0xfeccfecc,
1215 .ro = 0xfeccfecc,
1216 .w1c = 0x1330133,
1217 .post_write = pwr_ctrl_irq_status_postw,
1218 },{ .name = "PWR_CTRL_IRQ_MASK", .addr = A_PWR_CTRL_IRQ_MASK,
1219 .reset = 0x1330133,
1220 .rsvd = 0xfeccfecc,
1221 .ro = 0xffffffff,
1222 },{ .name = "PWR_CTRL_IRQ_EN", .addr = A_PWR_CTRL_IRQ_EN,
1223 .rsvd = 0xfeccfecc,
1224 .pre_write = pwr_ctrl_irq_en_prew,
1225 },{ .name = "PWR_CTRL_IRQ_DIS", .addr = A_PWR_CTRL_IRQ_DIS,
1226 .rsvd = 0xfeccfecc,
1227 .pre_write = pwr_ctrl_irq_dis_prew,
1228 },{ .name = "PWR_CTRL_IRQ_TRIG", .addr = A_PWR_CTRL_IRQ_TRIG,
1229 .rsvd = 0xfeccfecc,
1230 .pre_write = pwr_ctrl_irq_trig_prew,
1231 },{ .name = "DBG_PWR_ACK", .addr = A_DBG_PWR_ACK,
1232 .rsvd = 0xfffffff0,
1233 },{ .name = "MBIST_RSTN", .addr = A_MBIST_RSTN,
1234 .rsvd = 0xffffffe0,
1235 .ro = 0xffffffe0,
1236 },{ .name = "MBIST_PG_EN", .addr = A_MBIST_PG_EN,
1237 .rsvd = 0xffffffe0,
1238 .ro = 0xffffffe0,
1239 .pre_write = mbist_pg_en_prew,
1240 },{ .name = "MBIST_SETUP", .addr = A_MBIST_SETUP,
1241 .rsvd = 0xffffffe0,
1242 .ro = 0xffffffe0,
1243 },{ .name = "MBIST_DONE", .addr = A_MBIST_DONE,
1244 .rsvd = 0xffffffe0,
1245 .ro = 0xffffffff,
1246 },{ .name = "MBIST_GO", .addr = A_MBIST_GO,
1247 .rsvd = 0xffffffe0,
1248 .ro = 0xffffffff,
1249 },{ .name = "SCAN_CLEAR_CPU0", .addr = A_SCAN_CLEAR_CPU0,
1250 .rsvd = 0xfffffff8,
1251 .ro = 0xfffffffe,
1252 },{ .name = "SCAN_CLEAR_CPU1", .addr = A_SCAN_CLEAR_CPU1,
1253 .rsvd = 0xfffffff8,
1254 .ro = 0xfffffffe,
1255 },{ .name = "SCAN_CLEAR_APU", .addr = A_SCAN_CLEAR_APU,
1256 .rsvd = 0xfffffff8,
1257 .ro = 0xfffffffe,
1258 },{ .name = "SCAN_CLEAR_FPD", .addr = A_SCAN_CLEAR_FPD,
1259 .rsvd = 0xfffffff8,
1260 .ro = 0xfffffffe,
1261 .pre_write = scan_clear_fpd_prew,
1262 },{ .name = "SAFETY_CHK", .addr = A_SAFETY_CHK,
1263 }
1264};
1265
1266static void psm_global_reg_reset(DeviceState *dev)
1267{
1268 PSM_GLOBAL_REG *s = XILINX_PSM_GLOBAL_REG(dev);
1269 unsigned int i;
1270
1271 for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
1272 register_reset(&s->regs_info[i]);
1273 }
1274
1275 req_pwrdwn_int_update_irq(s);
1276 wakeup_irq_update_irq(s);
1277 req_swrst_int_update_irq(s);
1278 req_pwrup_int_update_irq(s);
1279 req_aux_int_update_irq(s);
1280 addr_error_int_update_irq(s);
1281 pwr_ctrl_irq_update_irq(s);
1282 req_iso_int_update_irq(s);
1283}
1284
1285static const MemoryRegionOps psm_global_reg_ops = {
1286 .read = register_read_memory,
1287 .write = register_write_memory,
1288 .endianness = DEVICE_LITTLE_ENDIAN,
1289 .valid = {
1290 .min_access_size = 4,
1291 .max_access_size = 4,
1292 },
1293};
1294
1295static void pwr_state_h(void *opaque, int n, int level)
1296{
1297 PSM_GLOBAL_REG *s = XILINX_PSM_GLOBAL_REG(opaque);
1298
1299 s->regs[R_PWR_STATE] = deposit32(s->regs[R_PWR_STATE], n, 1, level);
1300}
1301
1302static void aux_pwr_state_h(void *opaque, int n, int level)
1303{
1304 PSM_GLOBAL_REG *s = XILINX_PSM_GLOBAL_REG(opaque);
1305
1306 s->regs[R_AUX_PWR_STATE] = deposit32(s->regs[R_AUX_PWR_STATE],
1307 n, 1, level);
1308}
1309
1310static void pwr_ctrl_h(void *opaque, int n, int level)
1311{
1312 PSM_GLOBAL_REG *s = XILINX_PSM_GLOBAL_REG(opaque);
1313
1314
1315 s->regs[R_PWR_CTRL_IRQ_STATUS] |= (level << n);
1316 pwr_ctrl_irq_update_irq(s);
1317}
1318
1319static void wake_up_req_h(void *opaque, int n, int level)
1320{
1321 PSM_GLOBAL_REG *s = XILINX_PSM_GLOBAL_REG(opaque);
1322
1323
1324 s->regs[R_WAKEUP_IRQ_STATUS] |= (level << n);
1325 wakeup_irq_update_irq(s);
1326}
1327
1328static void psm_global_reg_realize(DeviceState *dev, Error **errp)
1329{
1330
1331}
1332
1333static void psm_global_reg_init(Object *obj)
1334{
1335 PSM_GLOBAL_REG *s = XILINX_PSM_GLOBAL_REG(obj);
1336 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
1337 RegisterInfoArray *reg_array;
1338
1339 memory_region_init(&s->iomem, obj, TYPE_XILINX_PSM_GLOBAL_REG,
1340 PSM_GLOBAL_REG_R_MAX * 4);
1341 reg_array =
1342 register_init_block32(DEVICE(obj), psm_global_reg_regs_info,
1343 ARRAY_SIZE(psm_global_reg_regs_info),
1344 s->regs_info, s->regs,
1345 &psm_global_reg_ops,
1346 XILINX_PSM_GLOBAL_REG_ERR_DEBUG,
1347 PSM_GLOBAL_REG_R_MAX * 4);
1348 memory_region_add_subregion(&s->iomem,
1349 0x0,
1350 ®_array->mem);
1351 sysbus_init_mmio(sbd, &s->iomem);
1352 sysbus_init_irq(sbd, &s->irq_req_pwrdwn_int);
1353 sysbus_init_irq(sbd, &s->irq_wakeup_irq);
1354 sysbus_init_irq(sbd, &s->irq_req_swrst_int);
1355 sysbus_init_irq(sbd, &s->irq_req_pwrup_int);
1356 sysbus_init_irq(sbd, &s->irq_pwr_ctrl_irq);
1357 sysbus_init_irq(sbd, &s->irq_req_iso_int);
1358 sysbus_init_irq(sbd, &s->irq_addr_error_int);
1359 sysbus_init_irq(sbd, &s->irq_req_aux_int);
1360
1361 qdev_init_gpio_in_named(DEVICE(obj), pwr_state_h, "pwr-state", 32);
1362 qdev_init_gpio_in_named(DEVICE(obj), aux_pwr_state_h, "aux-pwr-state", 32);
1363 qdev_init_gpio_in_named(DEVICE(obj), pwr_ctrl_h, "pwr-ctrl", 32);
1364 qdev_init_gpio_in_named(DEVICE(obj), wake_up_req_h, "wake-up-req", 32);
1365}
1366
1367static const VMStateDescription vmstate_psm_global_reg = {
1368 .name = TYPE_XILINX_PSM_GLOBAL_REG,
1369 .version_id = 1,
1370 .minimum_version_id = 1,
1371 .fields = (VMStateField[]) {
1372 VMSTATE_UINT32_ARRAY(regs, PSM_GLOBAL_REG, PSM_GLOBAL_REG_R_MAX),
1373 VMSTATE_END_OF_LIST(),
1374 }
1375};
1376
1377static const FDTGenericGPIOSet psm_client_gpios[] = {
1378 {
1379 .names = &fdt_generic_gpio_name_set_gpio,
1380 .gpios = (FDTGenericGPIOConnection[]) {
1381 { .name = "pwr-state", .fdt_index = 0, .range = 32 },
1382 { .name = "aux-pwr-state", .fdt_index = 32, .range = 32 },
1383 { .name = "pwr-ctrl", .fdt_index = 64, .range = 32},
1384 { },
1385 },
1386 },
1387 { },
1388};
1389
1390static const FDTGenericGPIOSet psm_controller_gpios[] = {
1391 {
1392 .names = &fdt_generic_gpio_name_set_gpio,
1393 .gpios = (FDTGenericGPIOConnection[]) {
1394 { .name = "wake-up-req", .fdt_index = 0, .range = 32},
1395 { },
1396 },
1397 },
1398 { },
1399};
1400
1401static void psm_global_reg_class_init(ObjectClass *klass, void *data)
1402{
1403 DeviceClass *dc = DEVICE_CLASS(klass);
1404 FDTGenericGPIOClass *fggc = FDT_GENERIC_GPIO_CLASS(klass);
1405
1406 dc->reset = psm_global_reg_reset;
1407 dc->realize = psm_global_reg_realize;
1408 dc->vmsd = &vmstate_psm_global_reg;
1409 fggc->client_gpios = psm_client_gpios;
1410 fggc->controller_gpios = psm_controller_gpios;
1411}
1412
1413static const TypeInfo psm_global_reg_info = {
1414 .name = TYPE_XILINX_PSM_GLOBAL_REG,
1415 .parent = TYPE_SYS_BUS_DEVICE,
1416 .instance_size = sizeof(PSM_GLOBAL_REG),
1417 .class_init = psm_global_reg_class_init,
1418 .instance_init = psm_global_reg_init,
1419 .interfaces = (InterfaceInfo[]) {
1420 { TYPE_FDT_GENERIC_GPIO },
1421 { }
1422 },
1423};
1424
1425static void psm_global_reg_register_types(void)
1426{
1427 type_register_static(&psm_global_reg_info);
1428}
1429
1430type_init(psm_global_reg_register_types)
1431
