LXR qemu/include/hw/intc/riscv

   1/*
   2 * RISC-V ACLINT (Advanced Core Local Interruptor) interface
   3 *
   4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
   5 * Copyright (c) 2017 SiFive, Inc.
   6 * Copyright (c) 2021 Western Digital Corporation or its affiliates.
   7 *
   8 * This program is free software; you can redistribute it and/or modify it
   9 * under the terms and conditions of the GNU General Public License,
  10 * version 2 or later, as published by the Free Software Foundation.
  11 *
  12 * This program is distributed in the hope it will be useful, but WITHOUT
  13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15 * more details.
  16 *
  17 * You should have received a copy of the GNU General Public License along with
  18 * this program.  If not, see <http://www.gnu.org/licenses/>.
  19 */
  20
  21#ifndef HW_RISCV_ACLINT_H
  22#define HW_RISCV_ACLINT_H
  23
  24#include "hw/sysbus.h"
  25
  26#define TYPE_RISCV_ACLINT_MTIMER "riscv.aclint.mtimer"
  27
  28#define RISCV_ACLINT_MTIMER(obj) \
  29    OBJECT_CHECK(RISCVAclintMTimerState, (obj), TYPE_RISCV_ACLINT_MTIMER)
  30
  31typedef struct RISCVAclintMTimerState {
  32    /*< private >*/
  33    SysBusDevice parent_obj;
  34    uint64_t time_delta;
  35
  36    /*< public >*/
  37    MemoryRegion mmio;
  38    uint32_t hartid_base;
  39    uint32_t num_harts;
  40    uint32_t timecmp_base;
  41    uint32_t time_base;
  42    uint32_t aperture_size;
  43    uint32_t timebase_freq;
  44    qemu_irq *timer_irqs;
  45} RISCVAclintMTimerState;
  46
  47DeviceState *riscv_aclint_mtimer_create(hwaddr addr, hwaddr size,
  48    uint32_t hartid_base, uint32_t num_harts,
  49    uint32_t timecmp_base, uint32_t time_base, uint32_t timebase_freq,
  50    bool provide_rdtime);
  51
  52#define TYPE_RISCV_ACLINT_SWI "riscv.aclint.swi"
  53
  54#define RISCV_ACLINT_SWI(obj) \
  55    OBJECT_CHECK(RISCVAclintSwiState, (obj), TYPE_RISCV_ACLINT_SWI)
  56
  57typedef struct RISCVAclintSwiState {
  58    /*< private >*/
  59    SysBusDevice parent_obj;
  60
  61    /*< public >*/
  62    MemoryRegion mmio;
  63    uint32_t hartid_base;
  64    uint32_t num_harts;
  65    uint32_t sswi;
  66    qemu_irq *soft_irqs;
  67} RISCVAclintSwiState;
  68
  69DeviceState *riscv_aclint_swi_create(hwaddr addr, uint32_t hartid_base,
  70    uint32_t num_harts, bool sswi);
  71
  72enum {
  73    RISCV_ACLINT_DEFAULT_MTIMECMP      = 0x0,
  74    RISCV_ACLINT_DEFAULT_MTIME         = 0x7ff8,
  75    RISCV_ACLINT_DEFAULT_MTIMER_SIZE   = 0x8000,
  76    RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ = 10000000,
  77    RISCV_ACLINT_MAX_HARTS             = 4095,
  78    RISCV_ACLINT_SWI_SIZE              = 0x4000
  79};
  80
  81#endif
  82