1#ifndef QEMU_PCI_H
2#define QEMU_PCI_H
3
4#include "exec/memory.h"
5#include "sysemu/dma.h"
6
7
8#include "hw/isa/isa.h"
9
10extern bool pci_available;
11
12
13
14#define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
15#define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
16#define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
17#define PCI_FUNC(devfn) ((devfn) & 0x07)
18#define PCI_BUILD_BDF(bus, devfn) ((bus << 8) | (devfn))
19#define PCI_BDF_TO_DEVFN(x) ((x) & 0xff)
20#define PCI_BUS_MAX 256
21#define PCI_DEVFN_MAX 256
22#define PCI_SLOT_MAX 32
23#define PCI_FUNC_MAX 8
24
25
26#include "hw/pci/pci_ids.h"
27
28
29
30
31#define PCI_DEVICE_ID_IBM_440GX 0x027f
32#define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff
33
34
35#define PCI_VENDOR_ID_HITACHI 0x1054
36#define PCI_DEVICE_ID_HITACHI_SH7751R 0x350e
37
38
39#define PCI_DEVICE_ID_APPLE_343S1201 0x0010
40#define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e
41#define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f
42#define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022
43#define PCI_DEVICE_ID_APPLE_IPID_USB 0x003f
44
45
46#define PCI_DEVICE_ID_REALTEK_8029 0x8029
47
48
49#define PCI_DEVICE_ID_XILINX_XC2VP30 0x0300
50
51
52#define PCI_DEVICE_ID_MARVELL_GT6412X 0x4620
53
54
55#define PCI_VENDOR_ID_QEMU 0x1234
56#define PCI_DEVICE_ID_QEMU_VGA 0x1111
57#define PCI_DEVICE_ID_QEMU_IPMI 0x1112
58
59
60#define PCI_VENDOR_ID_VMWARE 0x15ad
61#define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405
62#define PCI_DEVICE_ID_VMWARE_SVGA 0x0710
63#define PCI_DEVICE_ID_VMWARE_NET 0x0720
64#define PCI_DEVICE_ID_VMWARE_SCSI 0x0730
65#define PCI_DEVICE_ID_VMWARE_PVSCSI 0x07C0
66#define PCI_DEVICE_ID_VMWARE_IDE 0x1729
67#define PCI_DEVICE_ID_VMWARE_VMXNET3 0x07B0
68
69
70#define PCI_DEVICE_ID_INTEL_82551IT 0x1209
71#define PCI_DEVICE_ID_INTEL_82557 0x1229
72#define PCI_DEVICE_ID_INTEL_82801IR 0x2922
73
74
75#define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4
76#define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
77#define PCI_SUBDEVICE_ID_QEMU 0x1100
78
79#define PCI_DEVICE_ID_VIRTIO_NET 0x1000
80#define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001
81#define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002
82#define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003
83#define PCI_DEVICE_ID_VIRTIO_SCSI 0x1004
84#define PCI_DEVICE_ID_VIRTIO_RNG 0x1005
85#define PCI_DEVICE_ID_VIRTIO_9P 0x1009
86#define PCI_DEVICE_ID_VIRTIO_VSOCK 0x1012
87#define PCI_DEVICE_ID_VIRTIO_PMEM 0x1013
88#define PCI_DEVICE_ID_VIRTIO_IOMMU 0x1014
89#define PCI_DEVICE_ID_VIRTIO_MEM 0x1015
90
91#define PCI_VENDOR_ID_REDHAT 0x1b36
92#define PCI_DEVICE_ID_REDHAT_BRIDGE 0x0001
93#define PCI_DEVICE_ID_REDHAT_SERIAL 0x0002
94#define PCI_DEVICE_ID_REDHAT_SERIAL2 0x0003
95#define PCI_DEVICE_ID_REDHAT_SERIAL4 0x0004
96#define PCI_DEVICE_ID_REDHAT_TEST 0x0005
97#define PCI_DEVICE_ID_REDHAT_ROCKER 0x0006
98#define PCI_DEVICE_ID_REDHAT_SDHCI 0x0007
99#define PCI_DEVICE_ID_REDHAT_PCIE_HOST 0x0008
100#define PCI_DEVICE_ID_REDHAT_PXB 0x0009
101#define PCI_DEVICE_ID_REDHAT_BRIDGE_SEAT 0x000a
102#define PCI_DEVICE_ID_REDHAT_PXB_PCIE 0x000b
103#define PCI_DEVICE_ID_REDHAT_PCIE_RP 0x000c
104#define PCI_DEVICE_ID_REDHAT_XHCI 0x000d
105#define PCI_DEVICE_ID_REDHAT_PCIE_BRIDGE 0x000e
106#define PCI_DEVICE_ID_REDHAT_MDPY 0x000f
107#define PCI_DEVICE_ID_REDHAT_NVME 0x0010
108#define PCI_DEVICE_ID_REDHAT_PVPANIC 0x0011
109#define PCI_DEVICE_ID_REDHAT_ACPI_ERST 0x0012
110#define PCI_DEVICE_ID_REDHAT_QXL 0x0100
111
112#define FMT_PCIBUS PRIx64
113
114typedef uint64_t pcibus_t;
115
116struct PCIHostDeviceAddress {
117 unsigned int domain;
118 unsigned int bus;
119 unsigned int slot;
120 unsigned int function;
121};
122
123typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
124 uint32_t address, uint32_t data, int len);
125typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
126 uint32_t address, int len);
127typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
128 pcibus_t addr, pcibus_t size, int type);
129typedef void PCIUnregisterFunc(PCIDevice *pci_dev);
130
131typedef void MSITriggerFunc(PCIDevice *dev, MSIMessage msg);
132typedef MSIMessage MSIPrepareMessageFunc(PCIDevice *dev, unsigned vector);
133typedef MSIMessage MSIxPrepareMessageFunc(PCIDevice *dev, unsigned vector);
134
135typedef struct PCIIORegion {
136 pcibus_t addr;
137#define PCI_BAR_UNMAPPED (~(pcibus_t)0)
138 pcibus_t size;
139 uint8_t type;
140 MemoryRegion *memory;
141 MemoryRegion *address_space;
142} PCIIORegion;
143
144#define PCI_ROM_SLOT 6
145#define PCI_NUM_REGIONS 7
146
147enum {
148 QEMU_PCI_VGA_MEM,
149 QEMU_PCI_VGA_IO_LO,
150 QEMU_PCI_VGA_IO_HI,
151 QEMU_PCI_VGA_NUM_REGIONS,
152};
153
154#define QEMU_PCI_VGA_MEM_BASE 0xa0000
155#define QEMU_PCI_VGA_MEM_SIZE 0x20000
156#define QEMU_PCI_VGA_IO_LO_BASE 0x3b0
157#define QEMU_PCI_VGA_IO_LO_SIZE 0xc
158#define QEMU_PCI_VGA_IO_HI_BASE 0x3c0
159#define QEMU_PCI_VGA_IO_HI_SIZE 0x20
160
161#include "hw/pci/pci_regs.h"
162#include "hw/pci/pcie.h"
163
164
165#define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
166
167
168#define PCI_CONFIG_HEADER_SIZE 0x40
169
170#define PCI_CONFIG_SPACE_SIZE 0x100
171
172#define PCIE_CONFIG_SPACE_SIZE 0x1000
173
174#define PCI_NUM_PINS 4
175
176
177enum {
178 QEMU_PCI_CAP_MSI = 0x1,
179 QEMU_PCI_CAP_MSIX = 0x2,
180 QEMU_PCI_CAP_EXPRESS = 0x4,
181
182
183#define QEMU_PCI_CAP_MULTIFUNCTION_BITNR 3
184 QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR),
185
186
187#define QEMU_PCI_CAP_SERR_BITNR 4
188 QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR),
189
190#define QEMU_PCI_SHPC_BITNR 5
191 QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR),
192#define QEMU_PCI_SLOTID_BITNR 6
193 QEMU_PCI_CAP_SLOTID = (1 << QEMU_PCI_SLOTID_BITNR),
194
195#define QEMU_PCIE_SLTCAP_PCP_BITNR 7
196 QEMU_PCIE_SLTCAP_PCP = (1 << QEMU_PCIE_SLTCAP_PCP_BITNR),
197
198#define QEMU_PCIE_LNKSTA_DLLLA_BITNR 8
199 QEMU_PCIE_LNKSTA_DLLLA = (1 << QEMU_PCIE_LNKSTA_DLLLA_BITNR),
200#define QEMU_PCIE_EXTCAP_INIT_BITNR 9
201 QEMU_PCIE_EXTCAP_INIT = (1 << QEMU_PCIE_EXTCAP_INIT_BITNR),
202#define QEMU_PCIE_CXL_BITNR 10
203 QEMU_PCIE_CAP_CXL = (1 << QEMU_PCIE_CXL_BITNR),
204};
205
206#define TYPE_PCI_DEVICE "pci-device"
207typedef struct PCIDeviceClass PCIDeviceClass;
208DECLARE_OBJ_CHECKERS(PCIDevice, PCIDeviceClass,
209 PCI_DEVICE, TYPE_PCI_DEVICE)
210
211
212
213
214
215#define INTERFACE_CXL_DEVICE "cxl-device"
216
217
218#define INTERFACE_PCIE_DEVICE "pci-express-device"
219
220
221#define INTERFACE_CONVENTIONAL_PCI_DEVICE "conventional-pci-device"
222
223typedef struct PCIINTxRoute {
224 enum {
225 PCI_INTX_ENABLED,
226 PCI_INTX_INVERTED,
227 PCI_INTX_DISABLED,
228 } mode;
229 int irq;
230} PCIINTxRoute;
231
232struct PCIDeviceClass {
233 DeviceClass parent_class;
234
235 void (*realize)(PCIDevice *dev, Error **errp);
236 PCIUnregisterFunc *exit;
237 PCIConfigReadFunc *config_read;
238 PCIConfigWriteFunc *config_write;
239
240 uint16_t vendor_id;
241 uint16_t device_id;
242 uint8_t revision;
243 uint16_t class_id;
244 uint16_t subsystem_vendor_id;
245 uint16_t subsystem_id;
246
247
248
249
250
251
252 bool is_bridge;
253
254
255 const char *romfile;
256};
257
258typedef void (*PCIINTxRoutingNotifier)(PCIDevice *dev);
259typedef int (*MSIVectorUseNotifier)(PCIDevice *dev, unsigned int vector,
260 MSIMessage msg);
261typedef void (*MSIVectorReleaseNotifier)(PCIDevice *dev, unsigned int vector);
262typedef void (*MSIVectorPollNotifier)(PCIDevice *dev,
263 unsigned int vector_start,
264 unsigned int vector_end);
265
266enum PCIReqIDType {
267 PCI_REQ_ID_INVALID = 0,
268 PCI_REQ_ID_BDF,
269 PCI_REQ_ID_SECONDARY_BUS,
270 PCI_REQ_ID_MAX,
271};
272typedef enum PCIReqIDType PCIReqIDType;
273
274struct PCIReqIDCache {
275 PCIDevice *dev;
276 PCIReqIDType type;
277};
278typedef struct PCIReqIDCache PCIReqIDCache;
279
280struct PCIDevice {
281 DeviceState qdev;
282 bool partially_hotplugged;
283 bool has_power;
284
285
286 uint8_t *config;
287
288
289
290 uint8_t *cmask;
291
292
293 uint8_t *wmask;
294
295
296 uint8_t *w1cmask;
297
298
299 uint8_t *used;
300
301
302 int32_t devfn;
303
304
305
306
307 PCIReqIDCache requester_id_cache;
308 char name[64];
309 PCIIORegion io_regions[PCI_NUM_REGIONS];
310 AddressSpace bus_master_as;
311 MemoryRegion bus_master_container_region;
312 MemoryRegion bus_master_enable_region;
313
314
315 PCIConfigReadFunc *config_read;
316 PCIConfigWriteFunc *config_write;
317
318
319 MemoryRegion *vga_regions[QEMU_PCI_VGA_NUM_REGIONS];
320 bool has_vga;
321
322
323 uint8_t irq_state;
324
325
326 uint32_t cap_present;
327
328
329 uint8_t msix_cap;
330
331
332 int msix_entries_nr;
333
334
335 uint8_t *msix_table;
336 uint8_t *msix_pba;
337
338
339 void *irq_opaque;
340
341 MSITriggerFunc *msi_trigger;
342 MSIPrepareMessageFunc *msi_prepare_message;
343 MSIxPrepareMessageFunc *msix_prepare_message;
344
345
346 MemoryRegion msix_exclusive_bar;
347
348 MemoryRegion msix_table_mmio;
349 MemoryRegion msix_pba_mmio;
350
351 unsigned *msix_entry_used;
352
353 bool msix_function_masked;
354
355 int32_t version_id;
356
357
358 uint8_t msi_cap;
359
360
361 PCIExpressDevice exp;
362
363
364 SHPCDevice *shpc;
365
366
367 char *romfile;
368 uint32_t romsize;
369 bool has_rom;
370 MemoryRegion rom;
371 uint32_t rom_bar;
372
373
374 PCIINTxRoutingNotifier intx_routing_notifier;
375
376
377 MSIVectorUseNotifier msix_vector_use_notifier;
378 MSIVectorReleaseNotifier msix_vector_release_notifier;
379 MSIVectorPollNotifier msix_vector_poll_notifier;
380
381
382 char *failover_pair_id;
383 uint32_t acpi_index;
384};
385
386void pci_register_bar(PCIDevice *pci_dev, int region_num,
387 uint8_t attr, MemoryRegion *memory);
388void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem,
389 MemoryRegion *io_lo, MemoryRegion *io_hi);
390void pci_unregister_vga(PCIDevice *pci_dev);
391pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num);
392
393int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
394 uint8_t offset, uint8_t size,
395 Error **errp);
396
397void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
398
399uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id);
400
401
402uint32_t pci_default_read_config(PCIDevice *d,
403 uint32_t address, int len);
404void pci_default_write_config(PCIDevice *d,
405 uint32_t address, uint32_t val, int len);
406void pci_device_save(PCIDevice *s, QEMUFile *f);
407int pci_device_load(PCIDevice *s, QEMUFile *f);
408MemoryRegion *pci_address_space(PCIDevice *dev);
409MemoryRegion *pci_address_space_io(PCIDevice *dev);
410
411
412
413
414
415int pci_bar(PCIDevice *d, int reg);
416
417typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level);
418typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
419typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, int pin);
420
421#define TYPE_PCI_BUS "PCI"
422OBJECT_DECLARE_TYPE(PCIBus, PCIBusClass, PCI_BUS)
423#define TYPE_PCIE_BUS "PCIE"
424#define TYPE_CXL_BUS "CXL"
425
426typedef void (*pci_bus_dev_fn)(PCIBus *b, PCIDevice *d, void *opaque);
427typedef void (*pci_bus_fn)(PCIBus *b, void *opaque);
428typedef void *(*pci_bus_ret_fn)(PCIBus *b, void *opaque);
429
430bool pci_bus_is_express(PCIBus *bus);
431
432void pci_root_bus_init(PCIBus *bus, size_t bus_size, DeviceState *parent,
433 const char *name,
434 MemoryRegion *address_space_mem,
435 MemoryRegion *address_space_io,
436 uint8_t devfn_min, const char *typename);
437PCIBus *pci_root_bus_new(DeviceState *parent, const char *name,
438 MemoryRegion *address_space_mem,
439 MemoryRegion *address_space_io,
440 uint8_t devfn_min, const char *typename);
441void pci_root_bus_cleanup(PCIBus *bus);
442void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
443 void *irq_opaque, int nirq);
444void pci_bus_irqs_cleanup(PCIBus *bus);
445int pci_bus_get_irq_level(PCIBus *bus, int irq_num);
446
447static inline int pci_swizzle(int slot, int pin)
448{
449 return (slot + pin) % PCI_NUM_PINS;
450}
451int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin);
452PCIBus *pci_register_root_bus(DeviceState *parent, const char *name,
453 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
454 void *irq_opaque,
455 MemoryRegion *address_space_mem,
456 MemoryRegion *address_space_io,
457 uint8_t devfn_min, int nirq,
458 const char *typename);
459void pci_unregister_root_bus(PCIBus *bus);
460void pci_bus_set_route_irq_fn(PCIBus *, pci_route_irq_fn);
461PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin);
462bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new);
463void pci_bus_fire_intx_routing_notifier(PCIBus *bus);
464void pci_device_set_intx_routing_notifier(PCIDevice *dev,
465 PCIINTxRoutingNotifier notifier);
466void pci_device_reset(PCIDevice *dev);
467
468PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus,
469 const char *default_model,
470 const char *default_devaddr);
471
472PCIDevice *pci_vga_init(PCIBus *bus);
473
474static inline PCIBus *pci_get_bus(const PCIDevice *dev)
475{
476 return PCI_BUS(qdev_get_parent_bus(DEVICE(dev)));
477}
478int pci_bus_num(PCIBus *s);
479void pci_bus_range(PCIBus *bus, int *min_bus, int *max_bus);
480static inline int pci_dev_bus_num(const PCIDevice *dev)
481{
482 return pci_bus_num(pci_get_bus(dev));
483}
484
485int pci_bus_numa_node(PCIBus *bus);
486void pci_for_each_device(PCIBus *bus, int bus_num,
487 pci_bus_dev_fn fn,
488 void *opaque);
489void pci_for_each_device_reverse(PCIBus *bus, int bus_num,
490 pci_bus_dev_fn fn,
491 void *opaque);
492void pci_for_each_device_under_bus(PCIBus *bus,
493 pci_bus_dev_fn fn, void *opaque);
494void pci_for_each_device_under_bus_reverse(PCIBus *bus,
495 pci_bus_dev_fn fn,
496 void *opaque);
497void pci_for_each_bus_depth_first(PCIBus *bus, pci_bus_ret_fn begin,
498 pci_bus_fn end, void *parent_state);
499PCIDevice *pci_get_function_0(PCIDevice *pci_dev);
500
501
502static inline
503void pci_for_each_bus(PCIBus *bus, pci_bus_fn fn, void *opaque)
504{
505 pci_for_each_bus_depth_first(bus, NULL, fn, opaque);
506}
507
508PCIBus *pci_device_root_bus(const PCIDevice *d);
509const char *pci_root_bus_path(PCIDevice *dev);
510bool pci_bus_bypass_iommu(PCIBus *bus);
511PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn);
512int pci_qdev_find_device(const char *id, PCIDevice **pdev);
513void pci_bus_get_w64_range(PCIBus *bus, Range *range);
514
515void pci_device_deassert_intx(PCIDevice *dev);
516
517typedef AddressSpace *(*PCIIOMMUFunc)(PCIBus *, void *, int);
518
519AddressSpace *pci_device_iommu_address_space(PCIDevice *dev);
520void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque);
521
522pcibus_t pci_bar_address(PCIDevice *d,
523 int reg, uint8_t type, pcibus_t size);
524
525static inline void
526pci_set_byte(uint8_t *config, uint8_t val)
527{
528 *config = val;
529}
530
531static inline uint8_t
532pci_get_byte(const uint8_t *config)
533{
534 return *config;
535}
536
537static inline void
538pci_set_word(uint8_t *config, uint16_t val)
539{
540 stw_le_p(config, val);
541}
542
543static inline uint16_t
544pci_get_word(const uint8_t *config)
545{
546 return lduw_le_p(config);
547}
548
549static inline void
550pci_set_long(uint8_t *config, uint32_t val)
551{
552 stl_le_p(config, val);
553}
554
555static inline uint32_t
556pci_get_long(const uint8_t *config)
557{
558 return ldl_le_p(config);
559}
560
561
562
563
564
565
566
567
568static inline void
569pci_set_quad(uint8_t *config, uint64_t val)
570{
571 stq_le_p(config, val);
572}
573
574static inline uint64_t
575pci_get_quad(const uint8_t *config)
576{
577 return ldq_le_p(config);
578}
579
580static inline void
581pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val)
582{
583 pci_set_word(&pci_config[PCI_VENDOR_ID], val);
584}
585
586static inline void
587pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
588{
589 pci_set_word(&pci_config[PCI_DEVICE_ID], val);
590}
591
592static inline void
593pci_config_set_revision(uint8_t *pci_config, uint8_t val)
594{
595 pci_set_byte(&pci_config[PCI_REVISION_ID], val);
596}
597
598static inline void
599pci_config_set_class(uint8_t *pci_config, uint16_t val)
600{
601 pci_set_word(&pci_config[PCI_CLASS_DEVICE], val);
602}
603
604static inline void
605pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val)
606{
607 pci_set_byte(&pci_config[PCI_CLASS_PROG], val);
608}
609
610static inline void
611pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val)
612{
613 pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val);
614}
615
616
617
618
619
620
621
622static inline uint8_t
623pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask)
624{
625 uint8_t val = pci_get_byte(config);
626 pci_set_byte(config, val & ~mask);
627 return val & mask;
628}
629
630static inline uint8_t
631pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask)
632{
633 uint8_t val = pci_get_byte(config);
634 pci_set_byte(config, val | mask);
635 return val & mask;
636}
637
638static inline uint16_t
639pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask)
640{
641 uint16_t val = pci_get_word(config);
642 pci_set_word(config, val & ~mask);
643 return val & mask;
644}
645
646static inline uint16_t
647pci_word_test_and_set_mask(uint8_t *config, uint16_t mask)
648{
649 uint16_t val = pci_get_word(config);
650 pci_set_word(config, val | mask);
651 return val & mask;
652}
653
654static inline uint32_t
655pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask)
656{
657 uint32_t val = pci_get_long(config);
658 pci_set_long(config, val & ~mask);
659 return val & mask;
660}
661
662static inline uint32_t
663pci_long_test_and_set_mask(uint8_t *config, uint32_t mask)
664{
665 uint32_t val = pci_get_long(config);
666 pci_set_long(config, val | mask);
667 return val & mask;
668}
669
670static inline uint64_t
671pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask)
672{
673 uint64_t val = pci_get_quad(config);
674 pci_set_quad(config, val & ~mask);
675 return val & mask;
676}
677
678static inline uint64_t
679pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask)
680{
681 uint64_t val = pci_get_quad(config);
682 pci_set_quad(config, val | mask);
683 return val & mask;
684}
685
686
687static inline void
688pci_set_byte_by_mask(uint8_t *config, uint8_t mask, uint8_t reg)
689{
690 uint8_t val = pci_get_byte(config);
691 uint8_t rval = reg << ctz32(mask);
692 pci_set_byte(config, (~mask & val) | (mask & rval));
693}
694
695static inline uint8_t
696pci_get_byte_by_mask(uint8_t *config, uint8_t mask)
697{
698 uint8_t val = pci_get_byte(config);
699 return (val & mask) >> ctz32(mask);
700}
701
702static inline void
703pci_set_word_by_mask(uint8_t *config, uint16_t mask, uint16_t reg)
704{
705 uint16_t val = pci_get_word(config);
706 uint16_t rval = reg << ctz32(mask);
707 pci_set_word(config, (~mask & val) | (mask & rval));
708}
709
710static inline uint16_t
711pci_get_word_by_mask(uint8_t *config, uint16_t mask)
712{
713 uint16_t val = pci_get_word(config);
714 return (val & mask) >> ctz32(mask);
715}
716
717static inline void
718pci_set_long_by_mask(uint8_t *config, uint32_t mask, uint32_t reg)
719{
720 uint32_t val = pci_get_long(config);
721 uint32_t rval = reg << ctz32(mask);
722 pci_set_long(config, (~mask & val) | (mask & rval));
723}
724
725static inline uint32_t
726pci_get_long_by_mask(uint8_t *config, uint32_t mask)
727{
728 uint32_t val = pci_get_long(config);
729 return (val & mask) >> ctz32(mask);
730}
731
732static inline void
733pci_set_quad_by_mask(uint8_t *config, uint64_t mask, uint64_t reg)
734{
735 uint64_t val = pci_get_quad(config);
736 uint64_t rval = reg << ctz32(mask);
737 pci_set_quad(config, (~mask & val) | (mask & rval));
738}
739
740static inline uint64_t
741pci_get_quad_by_mask(uint8_t *config, uint64_t mask)
742{
743 uint64_t val = pci_get_quad(config);
744 return (val & mask) >> ctz32(mask);
745}
746
747PCIDevice *pci_new_multifunction(int devfn, bool multifunction,
748 const char *name);
749PCIDevice *pci_new(int devfn, const char *name);
750bool pci_realize_and_unref(PCIDevice *dev, PCIBus *bus, Error **errp);
751
752PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
753 bool multifunction,
754 const char *name);
755PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name);
756
757void lsi53c8xx_handle_legacy_cmdline(DeviceState *lsi_dev);
758
759qemu_irq pci_allocate_irq(PCIDevice *pci_dev);
760void pci_set_irq(PCIDevice *pci_dev, int level);
761
762static inline int pci_intx(PCIDevice *pci_dev)
763{
764 return pci_get_byte(pci_dev->config + PCI_INTERRUPT_PIN) - 1;
765}
766
767static inline void pci_irq_assert(PCIDevice *pci_dev)
768{
769 pci_set_irq(pci_dev, 1);
770}
771
772static inline void pci_irq_deassert(PCIDevice *pci_dev)
773{
774 pci_set_irq(pci_dev, 0);
775}
776
777
778
779
780
781static inline void pci_irq_pulse(PCIDevice *pci_dev)
782{
783 pci_irq_assert(pci_dev);
784 pci_irq_deassert(pci_dev);
785}
786
787static inline int pci_is_cxl(const PCIDevice *d)
788{
789 return d->cap_present & QEMU_PCIE_CAP_CXL;
790}
791
792static inline int pci_is_express(const PCIDevice *d)
793{
794 return d->cap_present & QEMU_PCI_CAP_EXPRESS;
795}
796
797static inline int pci_is_express_downstream_port(const PCIDevice *d)
798{
799 uint8_t type;
800
801 if (!pci_is_express(d) || !d->exp.exp_cap) {
802 return 0;
803 }
804
805 type = pcie_cap_get_type(d);
806
807 return type == PCI_EXP_TYPE_DOWNSTREAM || type == PCI_EXP_TYPE_ROOT_PORT;
808}
809
810static inline int pci_is_vf(const PCIDevice *d)
811{
812 return d->exp.sriov_vf.pf != NULL;
813}
814
815static inline uint32_t pci_config_size(const PCIDevice *d)
816{
817 return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE;
818}
819
820static inline uint16_t pci_get_bdf(PCIDevice *dev)
821{
822 return PCI_BUILD_BDF(pci_bus_num(pci_get_bus(dev)), dev->devfn);
823}
824
825uint16_t pci_requester_id(PCIDevice *dev);
826
827
828static inline AddressSpace *pci_get_address_space(PCIDevice *dev)
829{
830 return &dev->bus_master_as;
831}
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846static inline MemTxResult pci_dma_rw(PCIDevice *dev, dma_addr_t addr,
847 void *buf, dma_addr_t len,
848 DMADirection dir, MemTxAttrs attrs)
849{
850 attrs.requester_id = pci_requester_id(dev);
851 dma_memory_rw_attr(pci_get_address_space(dev), addr, buf, len, dir, attrs);
852 return 0;
853}
854
855
856
857
858
859
860
861
862
863
864
865
866
867static inline MemTxResult pci_dma_read(PCIDevice *dev, dma_addr_t addr,
868 void *buf, dma_addr_t len)
869{
870 return pci_dma_rw(dev, addr, buf, len,
871 DMA_DIRECTION_TO_DEVICE, MEMTXATTRS_UNSPECIFIED);
872}
873
874
875
876
877
878
879
880
881
882
883
884
885
886static inline MemTxResult pci_dma_write(PCIDevice *dev, dma_addr_t addr,
887 const void *buf, dma_addr_t len)
888{
889 return pci_dma_rw(dev, addr, (void *) buf, len,
890 DMA_DIRECTION_FROM_DEVICE, MEMTXATTRS_UNSPECIFIED);
891}
892
893#define PCI_DMA_DEFINE_LDST(_l, _s, _bits) \
894 static inline MemTxResult ld##_l##_pci_dma(PCIDevice *dev, \
895 dma_addr_t addr, \
896 uint##_bits##_t *val, \
897 MemTxAttrs attrs) \
898 { \
899 return ld##_l##_dma(pci_get_address_space(dev), addr, val, attrs); \
900 } \
901 static inline MemTxResult st##_s##_pci_dma(PCIDevice *dev, \
902 dma_addr_t addr, \
903 uint##_bits##_t val, \
904 MemTxAttrs attrs) \
905 { \
906 return st##_s##_dma(pci_get_address_space(dev), addr, val, attrs); \
907 }
908
909PCI_DMA_DEFINE_LDST(ub, b, 8);
910PCI_DMA_DEFINE_LDST(uw_le, w_le, 16)
911PCI_DMA_DEFINE_LDST(l_le, l_le, 32);
912PCI_DMA_DEFINE_LDST(q_le, q_le, 64);
913PCI_DMA_DEFINE_LDST(uw_be, w_be, 16)
914PCI_DMA_DEFINE_LDST(l_be, l_be, 32);
915PCI_DMA_DEFINE_LDST(q_be, q_be, 64);
916
917#undef PCI_DMA_DEFINE_LDST
918
919
920
921
922
923
924
925
926
927
928
929
930
931static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr,
932 dma_addr_t *plen, DMADirection dir)
933{
934 MemTxAttrs attr = MEMTXATTRS_UNSPECIFIED;
935 attr.requester_id = pci_requester_id(dev);
936 hwaddr xlen = *plen;
937 void *buf;
938
939 buf = address_space_map(pci_get_address_space(dev), addr, &xlen,
940 dir == DMA_DIRECTION_FROM_DEVICE, attr);
941 *plen = xlen;
942 return buf;
943}
944
945static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len,
946 DMADirection dir, dma_addr_t access_len)
947{
948 dma_memory_unmap(pci_get_address_space(dev), buffer, len, dir, access_len);
949}
950
951static inline void pci_dma_sglist_init(QEMUSGList *qsg, PCIDevice *dev,
952 int alloc_hint)
953{
954 qemu_sglist_init(qsg, DEVICE(dev), alloc_hint, pci_get_address_space(dev));
955}
956
957extern const VMStateDescription vmstate_pci_device;
958
959#define VMSTATE_PCI_DEVICE(_field, _state) { \
960 .name = (stringify(_field)), \
961 .size = sizeof(PCIDevice), \
962 .vmsd = &vmstate_pci_device, \
963 .flags = VMS_STRUCT, \
964 .offset = vmstate_offset_value(_state, _field, PCIDevice), \
965}
966
967#define VMSTATE_PCI_DEVICE_POINTER(_field, _state) { \
968 .name = (stringify(_field)), \
969 .size = sizeof(PCIDevice), \
970 .vmsd = &vmstate_pci_device, \
971 .flags = VMS_STRUCT|VMS_POINTER, \
972 .offset = vmstate_offset_pointer(_state, _field, PCIDevice), \
973}
974
975MSIMessage pci_get_msi_message(PCIDevice *dev, int vector);
976void pci_set_power(PCIDevice *pci_dev, bool state);
977
978#endif
979