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31#include "qemu/osdep.h"
32#include "qapi/error.h"
33#include "cpu.h"
34#include "fpu/softfloat.h"
35#include "qemu/module.h"
36#include "migration/vmstate.h"
37#include "hw/qdev-clock.h"
38
39
40static void xtensa_cpu_set_pc(CPUState *cs, vaddr value)
41{
42 XtensaCPU *cpu = XTENSA_CPU(cs);
43
44 cpu->env.pc = value;
45}
46
47static bool xtensa_cpu_has_work(CPUState *cs)
48{
49#ifndef CONFIG_USER_ONLY
50 XtensaCPU *cpu = XTENSA_CPU(cs);
51
52 return !cpu->env.runstall && cpu->env.pending_irq_level;
53#else
54 return true;
55#endif
56}
57
58#ifdef CONFIG_USER_ONLY
59static bool abi_call0;
60
61void xtensa_set_abi_call0(void)
62{
63 abi_call0 = true;
64}
65
66bool xtensa_abi_call0(void)
67{
68 return abi_call0;
69}
70#endif
71
72static void xtensa_cpu_reset(DeviceState *dev)
73{
74 CPUState *s = CPU(dev);
75 XtensaCPU *cpu = XTENSA_CPU(s);
76 XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(cpu);
77 CPUXtensaState *env = &cpu->env;
78 bool dfpu = xtensa_option_enabled(env->config,
79 XTENSA_OPTION_DFP_COPROCESSOR);
80
81 xcc->parent_reset(dev);
82
83 env->pc = env->config->exception_vector[EXC_RESET0 + env->static_vectors];
84 env->sregs[LITBASE] &= ~1;
85#ifndef CONFIG_USER_ONLY
86 env->sregs[PS] = xtensa_option_enabled(env->config,
87 XTENSA_OPTION_INTERRUPT) ? 0x1f : 0x10;
88 env->pending_irq_level = 0;
89#else
90 env->sregs[PS] = PS_UM | (3 << PS_RING_SHIFT);
91 if (xtensa_option_enabled(env->config,
92 XTENSA_OPTION_WINDOWED_REGISTER) &&
93 !xtensa_abi_call0()) {
94 env->sregs[PS] |= PS_WOE;
95 }
96 env->sregs[CPENABLE] = 0xff;
97#endif
98 env->sregs[VECBASE] = env->config->vecbase;
99 env->sregs[IBREAKENABLE] = 0;
100 env->sregs[MEMCTL] = MEMCTL_IL0EN & env->config->memctl_mask;
101 env->sregs[ATOMCTL] = xtensa_option_enabled(env->config,
102 XTENSA_OPTION_ATOMCTL) ? 0x28 : 0x15;
103 env->sregs[CONFIGID0] = env->config->configid[0];
104 env->sregs[CONFIGID1] = env->config->configid[1];
105 env->exclusive_addr = -1;
106
107#ifndef CONFIG_USER_ONLY
108 reset_mmu(env);
109 s->halted = env->runstall;
110#endif
111 set_no_signaling_nans(!dfpu, &env->fp_status);
112 set_use_first_nan(!dfpu, &env->fp_status);
113}
114
115static ObjectClass *xtensa_cpu_class_by_name(const char *cpu_model)
116{
117 ObjectClass *oc;
118 char *typename;
119
120 typename = g_strdup_printf(XTENSA_CPU_TYPE_NAME("%s"), cpu_model);
121 oc = object_class_by_name(typename);
122 g_free(typename);
123 if (oc == NULL || !object_class_dynamic_cast(oc, TYPE_XTENSA_CPU) ||
124 object_class_is_abstract(oc)) {
125 return NULL;
126 }
127 return oc;
128}
129
130static void xtensa_cpu_disas_set_info(CPUState *cs, disassemble_info *info)
131{
132 XtensaCPU *cpu = XTENSA_CPU(cs);
133
134 info->private_data = cpu->env.config->isa;
135 info->print_insn = print_insn_xtensa;
136}
137
138static void xtensa_cpu_realizefn(DeviceState *dev, Error **errp)
139{
140 CPUState *cs = CPU(dev);
141 XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(dev);
142 Error *local_err = NULL;
143
144#ifndef CONFIG_USER_ONLY
145 xtensa_irq_init(&XTENSA_CPU(dev)->env);
146#endif
147
148 cpu_exec_realizefn(cs, &local_err);
149 if (local_err != NULL) {
150 error_propagate(errp, local_err);
151 return;
152 }
153
154 cs->gdb_num_regs = xcc->config->gdb_regmap.num_regs;
155
156 qemu_init_vcpu(cs);
157
158 xcc->parent_realize(dev, errp);
159}
160
161static void xtensa_cpu_initfn(Object *obj)
162{
163 XtensaCPU *cpu = XTENSA_CPU(obj);
164 XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(obj);
165 CPUXtensaState *env = &cpu->env;
166
167 cpu_set_cpustate_pointers(cpu);
168 env->config = xcc->config;
169
170#ifndef CONFIG_USER_ONLY
171 env->address_space_er = g_malloc(sizeof(*env->address_space_er));
172 env->system_er = g_malloc(sizeof(*env->system_er));
173 memory_region_init_io(env->system_er, obj, NULL, env, "er",
174 UINT64_C(0x100000000));
175 address_space_init(env->address_space_er, env->system_er, "ER");
176
177 cpu->clock = qdev_init_clock_in(DEVICE(obj), "clk-in", NULL, cpu, 0);
178 clock_set_hz(cpu->clock, env->config->clock_freq_khz * 1000);
179#endif
180}
181
182XtensaCPU *xtensa_cpu_create_with_clock(const char *cpu_type, Clock *cpu_refclk)
183{
184 DeviceState *cpu;
185
186 cpu = DEVICE(object_new(cpu_type));
187 qdev_connect_clock_in(cpu, "clk-in", cpu_refclk);
188 qdev_realize(cpu, NULL, &error_abort);
189
190 return XTENSA_CPU(cpu);
191}
192
193#ifndef CONFIG_USER_ONLY
194static const VMStateDescription vmstate_xtensa_cpu = {
195 .name = "cpu",
196 .unmigratable = 1,
197};
198
199#include "hw/core/sysemu-cpu-ops.h"
200
201static const struct SysemuCPUOps xtensa_sysemu_ops = {
202 .get_phys_page_debug = xtensa_cpu_get_phys_page_debug,
203};
204#endif
205
206#include "hw/core/tcg-cpu-ops.h"
207
208static const struct TCGCPUOps xtensa_tcg_ops = {
209 .initialize = xtensa_translate_init,
210 .debug_excp_handler = xtensa_breakpoint_handler,
211
212#ifndef CONFIG_USER_ONLY
213 .tlb_fill = xtensa_cpu_tlb_fill,
214 .cpu_exec_interrupt = xtensa_cpu_exec_interrupt,
215 .do_interrupt = xtensa_cpu_do_interrupt,
216 .do_transaction_failed = xtensa_cpu_do_transaction_failed,
217 .do_unaligned_access = xtensa_cpu_do_unaligned_access,
218#endif
219};
220
221static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
222{
223 DeviceClass *dc = DEVICE_CLASS(oc);
224 CPUClass *cc = CPU_CLASS(oc);
225 XtensaCPUClass *xcc = XTENSA_CPU_CLASS(cc);
226
227 device_class_set_parent_realize(dc, xtensa_cpu_realizefn,
228 &xcc->parent_realize);
229
230 device_class_set_parent_reset(dc, xtensa_cpu_reset, &xcc->parent_reset);
231
232 cc->class_by_name = xtensa_cpu_class_by_name;
233 cc->has_work = xtensa_cpu_has_work;
234 cc->dump_state = xtensa_cpu_dump_state;
235 cc->set_pc = xtensa_cpu_set_pc;
236 cc->gdb_read_register = xtensa_cpu_gdb_read_register;
237 cc->gdb_write_register = xtensa_cpu_gdb_write_register;
238 cc->gdb_stop_before_watchpoint = true;
239#ifndef CONFIG_USER_ONLY
240 cc->sysemu_ops = &xtensa_sysemu_ops;
241 dc->vmsd = &vmstate_xtensa_cpu;
242#endif
243 cc->disas_set_info = xtensa_cpu_disas_set_info;
244 cc->tcg_ops = &xtensa_tcg_ops;
245}
246
247static const TypeInfo xtensa_cpu_type_info = {
248 .name = TYPE_XTENSA_CPU,
249 .parent = TYPE_CPU,
250 .instance_size = sizeof(XtensaCPU),
251 .instance_init = xtensa_cpu_initfn,
252 .abstract = true,
253 .class_size = sizeof(XtensaCPUClass),
254 .class_init = xtensa_cpu_class_init,
255};
256
257static void xtensa_cpu_register_types(void)
258{
259 type_register_static(&xtensa_cpu_type_info);
260}
261
262type_init(xtensa_cpu_register_types)
263
