1pci-test is a device used for testing low level IO 2 3device implements up to three BARs: BAR0, BAR1 and BAR2. 4Each of BAR 0+1 can be memory or IO. Guests must detect 5BAR types and act accordingly. 6 7BAR 0+1 size is up to 4K bytes each. 8BAR 0+1 starts with the following header: 9 10typedef struct PCITestDevHdr { 11 uint8_t test; <- write-only, starts a given test number 12 uint8_t width_type; <- read-only, type and width of access for a given test. 13 1,2,4 for byte,word or long write. 14 any other value if test not supported on this BAR 15 uint8_t pad0[2]; 16 uint32_t offset; <- read-only, offset in this BAR for a given test 17 uint32_t data; <- read-only, data to use for a given test 18 uint32_t count; <- for debugging. number of writes detected. 19 uint8_t name[]; <- for debugging. 0-terminated ASCII string. 20} PCITestDevHdr; 21 22All registers are little endian. 23 24device is expected to always implement tests 0 to N on each BAR, and to add new 25tests with higher numbers. In this way a guest can scan test numbers until it 26detects an access type that it does not support on this BAR, then stop. 27 28BAR2 is a 64bit memory bar, without backing storage. It is disabled 29by default and can be enabled using the membar=<size> property. This 30can be used to test whether guests handle pci bars of a specific 31(possibly quite large) size correctly. 32