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10#include "qemu/osdep.h"
11#include "cpu.h"
12#include "hw/irq.h"
13#include "hw/qdev-properties.h"
14#include "hw/sysbus.h"
15#include "migration/vmstate.h"
16#include "hw/arm/pxa.h"
17#include "qapi/error.h"
18#include "qemu/log.h"
19#include "qemu/module.h"
20#include "qom/object.h"
21
22#define PXA2XX_GPIO_BANKS 4
23
24#define TYPE_PXA2XX_GPIO "pxa2xx-gpio"
25OBJECT_DECLARE_SIMPLE_TYPE(PXA2xxGPIOInfo, PXA2XX_GPIO)
26
27struct PXA2xxGPIOInfo {
28
29 SysBusDevice parent_obj;
30
31
32 MemoryRegion iomem;
33 qemu_irq irq0, irq1, irqX;
34 int lines;
35 int ncpu;
36 ARMCPU *cpu;
37
38
39 uint32_t ilevel[PXA2XX_GPIO_BANKS];
40 uint32_t olevel[PXA2XX_GPIO_BANKS];
41 uint32_t dir[PXA2XX_GPIO_BANKS];
42 uint32_t rising[PXA2XX_GPIO_BANKS];
43 uint32_t falling[PXA2XX_GPIO_BANKS];
44 uint32_t status[PXA2XX_GPIO_BANKS];
45 uint32_t gafr[PXA2XX_GPIO_BANKS * 2];
46
47 uint32_t prev_level[PXA2XX_GPIO_BANKS];
48 qemu_irq handler[PXA2XX_GPIO_BANKS * 32];
49 qemu_irq read_notify;
50};
51
52static struct {
53 enum {
54 GPIO_NONE,
55 GPLR,
56 GPSR,
57 GPCR,
58 GPDR,
59 GRER,
60 GFER,
61 GEDR,
62 GAFR_L,
63 GAFR_U,
64 } reg;
65 int bank;
66} pxa2xx_gpio_regs[0x200] = {
67 [0 ... 0x1ff] = { GPIO_NONE, 0 },
68#define PXA2XX_REG(reg, a0, a1, a2, a3) \
69 [a0] = { reg, 0 }, [a1] = { reg, 1 }, [a2] = { reg, 2 }, [a3] = { reg, 3 },
70
71 PXA2XX_REG(GPLR, 0x000, 0x004, 0x008, 0x100)
72 PXA2XX_REG(GPSR, 0x018, 0x01c, 0x020, 0x118)
73 PXA2XX_REG(GPCR, 0x024, 0x028, 0x02c, 0x124)
74 PXA2XX_REG(GPDR, 0x00c, 0x010, 0x014, 0x10c)
75 PXA2XX_REG(GRER, 0x030, 0x034, 0x038, 0x130)
76 PXA2XX_REG(GFER, 0x03c, 0x040, 0x044, 0x13c)
77 PXA2XX_REG(GEDR, 0x048, 0x04c, 0x050, 0x148)
78 PXA2XX_REG(GAFR_L, 0x054, 0x05c, 0x064, 0x06c)
79 PXA2XX_REG(GAFR_U, 0x058, 0x060, 0x068, 0x070)
80};
81
82static void pxa2xx_gpio_irq_update(PXA2xxGPIOInfo *s)
83{
84 if (s->status[0] & (1 << 0))
85 qemu_irq_raise(s->irq0);
86 else
87 qemu_irq_lower(s->irq0);
88
89 if (s->status[0] & (1 << 1))
90 qemu_irq_raise(s->irq1);
91 else
92 qemu_irq_lower(s->irq1);
93
94 if ((s->status[0] & ~3) | s->status[1] | s->status[2] | s->status[3])
95 qemu_irq_raise(s->irqX);
96 else
97 qemu_irq_lower(s->irqX);
98}
99
100
101static const int pxa2xx_gpio_wake[PXA2XX_GPIO_BANKS] = {
102 0x8003fe1b, 0x002001fc, 0xec080000, 0x0012007f,
103};
104
105static void pxa2xx_gpio_set(void *opaque, int line, int level)
106{
107 PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
108 CPUState *cpu = CPU(s->cpu);
109 int bank;
110 uint32_t mask;
111
112 if (line >= s->lines) {
113 printf("%s: No GPIO pin %i\n", __func__, line);
114 return;
115 }
116
117 bank = line >> 5;
118 mask = 1U << (line & 31);
119
120 if (level) {
121 s->status[bank] |= s->rising[bank] & mask &
122 ~s->ilevel[bank] & ~s->dir[bank];
123 s->ilevel[bank] |= mask;
124 } else {
125 s->status[bank] |= s->falling[bank] & mask &
126 s->ilevel[bank] & ~s->dir[bank];
127 s->ilevel[bank] &= ~mask;
128 }
129
130 if (s->status[bank] & mask)
131 pxa2xx_gpio_irq_update(s);
132
133
134 if (cpu->halted && (mask & ~s->dir[bank] & pxa2xx_gpio_wake[bank])) {
135 cpu_interrupt(cpu, CPU_INTERRUPT_EXITTB);
136 }
137}
138
139static void pxa2xx_gpio_handler_update(PXA2xxGPIOInfo *s) {
140 uint32_t level, diff;
141 int i, bit, line;
142 for (i = 0; i < PXA2XX_GPIO_BANKS; i ++) {
143 level = s->olevel[i] & s->dir[i];
144
145 for (diff = s->prev_level[i] ^ level; diff; diff ^= 1 << bit) {
146 bit = ctz32(diff);
147 line = bit + 32 * i;
148 qemu_set_irq(s->handler[line], (level >> bit) & 1);
149 }
150
151 s->prev_level[i] = level;
152 }
153}
154
155static uint64_t pxa2xx_gpio_read(void *opaque, hwaddr offset,
156 unsigned size)
157{
158 PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
159 uint32_t ret;
160 int bank;
161 if (offset >= 0x200)
162 return 0;
163
164 bank = pxa2xx_gpio_regs[offset].bank;
165 switch (pxa2xx_gpio_regs[offset].reg) {
166 case GPDR:
167 return s->dir[bank];
168
169 case GPSR:
170 qemu_log_mask(LOG_GUEST_ERROR,
171 "pxa2xx GPIO: read from write only register GPSR\n");
172 return 0;
173
174 case GPCR:
175 qemu_log_mask(LOG_GUEST_ERROR,
176 "pxa2xx GPIO: read from write only register GPCR\n");
177 return 0;
178
179 case GRER:
180 return s->rising[bank];
181
182 case GFER:
183 return s->falling[bank];
184
185 case GAFR_L:
186 return s->gafr[bank * 2];
187
188 case GAFR_U:
189 return s->gafr[bank * 2 + 1];
190
191 case GPLR:
192 ret = (s->olevel[bank] & s->dir[bank]) |
193 (s->ilevel[bank] & ~s->dir[bank]);
194 qemu_irq_raise(s->read_notify);
195 return ret;
196
197 case GEDR:
198 return s->status[bank];
199
200 default:
201 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
202 __func__, offset);
203 }
204
205 return 0;
206}
207
208static void pxa2xx_gpio_write(void *opaque, hwaddr offset,
209 uint64_t value, unsigned size)
210{
211 PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
212 int bank;
213 if (offset >= 0x200)
214 return;
215
216 bank = pxa2xx_gpio_regs[offset].bank;
217 switch (pxa2xx_gpio_regs[offset].reg) {
218 case GPDR:
219 s->dir[bank] = value;
220 pxa2xx_gpio_handler_update(s);
221 break;
222
223 case GPSR:
224 s->olevel[bank] |= value;
225 pxa2xx_gpio_handler_update(s);
226 break;
227
228 case GPCR:
229 s->olevel[bank] &= ~value;
230 pxa2xx_gpio_handler_update(s);
231 break;
232
233 case GRER:
234 s->rising[bank] = value;
235 break;
236
237 case GFER:
238 s->falling[bank] = value;
239 break;
240
241 case GAFR_L:
242 s->gafr[bank * 2] = value;
243 break;
244
245 case GAFR_U:
246 s->gafr[bank * 2 + 1] = value;
247 break;
248
249 case GEDR:
250 s->status[bank] &= ~value;
251 pxa2xx_gpio_irq_update(s);
252 break;
253
254 default:
255 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
256 __func__, offset);
257 }
258}
259
260static const MemoryRegionOps pxa_gpio_ops = {
261 .read = pxa2xx_gpio_read,
262 .write = pxa2xx_gpio_write,
263 .endianness = DEVICE_NATIVE_ENDIAN,
264};
265
266DeviceState *pxa2xx_gpio_init(hwaddr base,
267 ARMCPU *cpu, DeviceState *pic, int lines)
268{
269 CPUState *cs = CPU(cpu);
270 DeviceState *dev;
271
272 dev = qdev_new(TYPE_PXA2XX_GPIO);
273 qdev_prop_set_int32(dev, "lines", lines);
274 qdev_prop_set_int32(dev, "ncpu", cs->cpu_index);
275 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
276
277 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
278 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
279 qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_0));
280 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1,
281 qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_1));
282 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2,
283 qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_X));
284
285 return dev;
286}
287
288static void pxa2xx_gpio_initfn(Object *obj)
289{
290 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
291 DeviceState *dev = DEVICE(sbd);
292 PXA2xxGPIOInfo *s = PXA2XX_GPIO(dev);
293
294 memory_region_init_io(&s->iomem, obj, &pxa_gpio_ops,
295 s, "pxa2xx-gpio", 0x1000);
296 sysbus_init_mmio(sbd, &s->iomem);
297 sysbus_init_irq(sbd, &s->irq0);
298 sysbus_init_irq(sbd, &s->irq1);
299 sysbus_init_irq(sbd, &s->irqX);
300}
301
302static void pxa2xx_gpio_realize(DeviceState *dev, Error **errp)
303{
304 PXA2xxGPIOInfo *s = PXA2XX_GPIO(dev);
305
306 s->cpu = ARM_CPU(qemu_get_cpu(s->ncpu));
307
308 qdev_init_gpio_in(dev, pxa2xx_gpio_set, s->lines);
309 qdev_init_gpio_out(dev, s->handler, s->lines);
310}
311
312
313
314
315
316void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler)
317{
318 PXA2xxGPIOInfo *s = PXA2XX_GPIO(dev);
319
320 s->read_notify = handler;
321}
322
323static const VMStateDescription vmstate_pxa2xx_gpio_regs = {
324 .name = "pxa2xx-gpio",
325 .version_id = 1,
326 .minimum_version_id = 1,
327 .fields = (VMStateField[]) {
328 VMSTATE_UINT32_ARRAY(ilevel, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
329 VMSTATE_UINT32_ARRAY(olevel, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
330 VMSTATE_UINT32_ARRAY(dir, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
331 VMSTATE_UINT32_ARRAY(rising, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
332 VMSTATE_UINT32_ARRAY(falling, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
333 VMSTATE_UINT32_ARRAY(status, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
334 VMSTATE_UINT32_ARRAY(gafr, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS * 2),
335 VMSTATE_UINT32_ARRAY(prev_level, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
336 VMSTATE_END_OF_LIST(),
337 },
338};
339
340static Property pxa2xx_gpio_properties[] = {
341 DEFINE_PROP_INT32("lines", PXA2xxGPIOInfo, lines, 0),
342 DEFINE_PROP_INT32("ncpu", PXA2xxGPIOInfo, ncpu, 0),
343 DEFINE_PROP_END_OF_LIST(),
344};
345
346static void pxa2xx_gpio_class_init(ObjectClass *klass, void *data)
347{
348 DeviceClass *dc = DEVICE_CLASS(klass);
349
350 dc->desc = "PXA2xx GPIO controller";
351 device_class_set_props(dc, pxa2xx_gpio_properties);
352 dc->vmsd = &vmstate_pxa2xx_gpio_regs;
353 dc->realize = pxa2xx_gpio_realize;
354}
355
356static const TypeInfo pxa2xx_gpio_info = {
357 .name = TYPE_PXA2XX_GPIO,
358 .parent = TYPE_SYS_BUS_DEVICE,
359 .instance_size = sizeof(PXA2xxGPIOInfo),
360 .instance_init = pxa2xx_gpio_initfn,
361 .class_init = pxa2xx_gpio_class_init,
362};
363
364static void pxa2xx_gpio_register_types(void)
365{
366 type_register_static(&pxa2xx_gpio_info);
367}
368
369type_init(pxa2xx_gpio_register_types)
370
