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10#include "qemu/osdep.h"
11#include "qapi/error.h"
12#include "hw/sysbus.h"
13#include "hw/ssi/ssi.h"
14#include "hw/arm/boot.h"
15#include "qemu/timer.h"
16#include "hw/i2c/i2c.h"
17#include "net/net.h"
18#include "hw/boards.h"
19#include "qemu/log.h"
20#include "exec/address-spaces.h"
21#include "sysemu/sysemu.h"
22#include "hw/arm/armv7m.h"
23#include "hw/char/pl011.h"
24#include "hw/input/gamepad.h"
25#include "hw/irq.h"
26#include "hw/watchdog/cmsdk-apb-watchdog.h"
27#include "migration/vmstate.h"
28#include "hw/misc/unimp.h"
29#include "hw/timer/stellaris-gptm.h"
30#include "hw/qdev-clock.h"
31#include "qom/object.h"
32
33#define GPIO_A 0
34#define GPIO_B 1
35#define GPIO_C 2
36#define GPIO_D 3
37#define GPIO_E 4
38#define GPIO_F 5
39#define GPIO_G 6
40
41#define BP_OLED_I2C 0x01
42#define BP_OLED_SSI 0x02
43#define BP_GAMEPAD 0x04
44
45#define NUM_IRQ_LINES 64
46
47typedef const struct {
48 const char *name;
49 uint32_t did0;
50 uint32_t did1;
51 uint32_t dc0;
52 uint32_t dc1;
53 uint32_t dc2;
54 uint32_t dc3;
55 uint32_t dc4;
56 uint32_t peripherals;
57} stellaris_board_info;
58
59
60
61#define TYPE_STELLARIS_SYS "stellaris-sys"
62OBJECT_DECLARE_SIMPLE_TYPE(ssys_state, STELLARIS_SYS)
63
64struct ssys_state {
65 SysBusDevice parent_obj;
66
67 MemoryRegion iomem;
68 uint32_t pborctl;
69 uint32_t ldopctl;
70 uint32_t int_status;
71 uint32_t int_mask;
72 uint32_t resc;
73 uint32_t rcc;
74 uint32_t rcc2;
75 uint32_t rcgc[3];
76 uint32_t scgc[3];
77 uint32_t dcgc[3];
78 uint32_t clkvclr;
79 uint32_t ldoarst;
80 qemu_irq irq;
81 Clock *sysclk;
82
83 uint32_t user0;
84 uint32_t user1;
85 uint32_t did0;
86 uint32_t did1;
87 uint32_t dc0;
88 uint32_t dc1;
89 uint32_t dc2;
90 uint32_t dc3;
91 uint32_t dc4;
92};
93
94static void ssys_update(ssys_state *s)
95{
96 qemu_set_irq(s->irq, (s->int_status & s->int_mask) != 0);
97}
98
99static uint32_t pllcfg_sandstorm[16] = {
100 0x31c0,
101 0x1ae0,
102 0x18c0,
103 0xd573,
104 0x37a6,
105 0x1ae2,
106 0x0c40,
107 0x98bc,
108 0x935b,
109 0x09c0,
110 0x4dee,
111 0x0c41,
112 0x75db,
113 0x1ae6,
114 0x0600,
115 0x585b
116};
117
118static uint32_t pllcfg_fury[16] = {
119 0x3200,
120 0x1b20,
121 0x1900,
122 0xf42b,
123 0x37e3,
124 0x1b21,
125 0x0c80,
126 0x98ee,
127 0xd5b4,
128 0x0a00,
129 0x4e27,
130 0x1902,
131 0xec1c,
132 0x1b23,
133 0x0640,
134 0xb11c
135};
136
137#define DID0_VER_MASK 0x70000000
138#define DID0_VER_0 0x00000000
139#define DID0_VER_1 0x10000000
140
141#define DID0_CLASS_MASK 0x00FF0000
142#define DID0_CLASS_SANDSTORM 0x00000000
143#define DID0_CLASS_FURY 0x00010000
144
145static int ssys_board_class(const ssys_state *s)
146{
147 uint32_t did0 = s->did0;
148 switch (did0 & DID0_VER_MASK) {
149 case DID0_VER_0:
150 return DID0_CLASS_SANDSTORM;
151 case DID0_VER_1:
152 switch (did0 & DID0_CLASS_MASK) {
153 case DID0_CLASS_SANDSTORM:
154 case DID0_CLASS_FURY:
155 return did0 & DID0_CLASS_MASK;
156 }
157
158 default:
159
160
161
162 g_assert_not_reached();
163 }
164}
165
166static uint64_t ssys_read(void *opaque, hwaddr offset,
167 unsigned size)
168{
169 ssys_state *s = (ssys_state *)opaque;
170
171 switch (offset) {
172 case 0x000:
173 return s->did0;
174 case 0x004:
175 return s->did1;
176 case 0x008:
177 return s->dc0;
178 case 0x010:
179 return s->dc1;
180 case 0x014:
181 return s->dc2;
182 case 0x018:
183 return s->dc3;
184 case 0x01c:
185 return s->dc4;
186 case 0x030:
187 return s->pborctl;
188 case 0x034:
189 return s->ldopctl;
190 case 0x040:
191 return 0;
192 case 0x044:
193 return 0;
194 case 0x048:
195 return 0;
196 case 0x050:
197 return s->int_status;
198 case 0x054:
199 return s->int_mask;
200 case 0x058:
201 return s->int_status & s->int_mask;
202 case 0x05c:
203 return s->resc;
204 case 0x060:
205 return s->rcc;
206 case 0x064:
207 {
208 int xtal;
209 xtal = (s->rcc >> 6) & 0xf;
210 switch (ssys_board_class(s)) {
211 case DID0_CLASS_FURY:
212 return pllcfg_fury[xtal];
213 case DID0_CLASS_SANDSTORM:
214 return pllcfg_sandstorm[xtal];
215 default:
216 g_assert_not_reached();
217 }
218 }
219 case 0x070:
220 return s->rcc2;
221 case 0x100:
222 return s->rcgc[0];
223 case 0x104:
224 return s->rcgc[1];
225 case 0x108:
226 return s->rcgc[2];
227 case 0x110:
228 return s->scgc[0];
229 case 0x114:
230 return s->scgc[1];
231 case 0x118:
232 return s->scgc[2];
233 case 0x120:
234 return s->dcgc[0];
235 case 0x124:
236 return s->dcgc[1];
237 case 0x128:
238 return s->dcgc[2];
239 case 0x150:
240 return s->clkvclr;
241 case 0x160:
242 return s->ldoarst;
243 case 0x1e0:
244 return s->user0;
245 case 0x1e4:
246 return s->user1;
247 default:
248 qemu_log_mask(LOG_GUEST_ERROR,
249 "SSYS: read at bad offset 0x%x\n", (int)offset);
250 return 0;
251 }
252}
253
254static bool ssys_use_rcc2(ssys_state *s)
255{
256 return (s->rcc2 >> 31) & 0x1;
257}
258
259
260
261
262
263
264static void ssys_calculate_system_clock(ssys_state *s, bool propagate_clock)
265{
266 int period_ns;
267
268
269
270
271
272 if (ssys_use_rcc2(s)) {
273 period_ns = 5 * (((s->rcc2 >> 23) & 0x3f) + 1);
274 } else {
275 period_ns = 5 * (((s->rcc >> 23) & 0xf) + 1);
276 }
277 clock_set_ns(s->sysclk, period_ns);
278 if (propagate_clock) {
279 clock_propagate(s->sysclk);
280 }
281}
282
283static void ssys_write(void *opaque, hwaddr offset,
284 uint64_t value, unsigned size)
285{
286 ssys_state *s = (ssys_state *)opaque;
287
288 switch (offset) {
289 case 0x030:
290 s->pborctl = value & 0xffff;
291 break;
292 case 0x034:
293 s->ldopctl = value & 0x1f;
294 break;
295 case 0x040:
296 case 0x044:
297 case 0x048:
298 qemu_log_mask(LOG_UNIMP, "Peripheral reset not implemented\n");
299 break;
300 case 0x054:
301 s->int_mask = value & 0x7f;
302 break;
303 case 0x058:
304 s->int_status &= ~value;
305 break;
306 case 0x05c:
307 s->resc = value & 0x3f;
308 break;
309 case 0x060:
310 if ((s->rcc & (1 << 13)) != 0 && (value & (1 << 13)) == 0) {
311
312 s->int_status |= (1 << 6);
313 }
314 s->rcc = value;
315 ssys_calculate_system_clock(s, true);
316 break;
317 case 0x070:
318 if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) {
319 break;
320 }
321
322 if ((s->rcc2 & (1 << 13)) != 0 && (value & (1 << 13)) == 0) {
323
324 s->int_status |= (1 << 6);
325 }
326 s->rcc2 = value;
327 ssys_calculate_system_clock(s, true);
328 break;
329 case 0x100:
330 s->rcgc[0] = value;
331 break;
332 case 0x104:
333 s->rcgc[1] = value;
334 break;
335 case 0x108:
336 s->rcgc[2] = value;
337 break;
338 case 0x110:
339 s->scgc[0] = value;
340 break;
341 case 0x114:
342 s->scgc[1] = value;
343 break;
344 case 0x118:
345 s->scgc[2] = value;
346 break;
347 case 0x120:
348 s->dcgc[0] = value;
349 break;
350 case 0x124:
351 s->dcgc[1] = value;
352 break;
353 case 0x128:
354 s->dcgc[2] = value;
355 break;
356 case 0x150:
357 s->clkvclr = value;
358 break;
359 case 0x160:
360 s->ldoarst = value;
361 break;
362 default:
363 qemu_log_mask(LOG_GUEST_ERROR,
364 "SSYS: write at bad offset 0x%x\n", (int)offset);
365 }
366 ssys_update(s);
367}
368
369static const MemoryRegionOps ssys_ops = {
370 .read = ssys_read,
371 .write = ssys_write,
372 .endianness = DEVICE_NATIVE_ENDIAN,
373};
374
375static void stellaris_sys_reset_enter(Object *obj, ResetType type)
376{
377 ssys_state *s = STELLARIS_SYS(obj);
378
379 s->pborctl = 0x7ffd;
380 s->rcc = 0x078e3ac0;
381
382 if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) {
383 s->rcc2 = 0;
384 } else {
385 s->rcc2 = 0x07802810;
386 }
387 s->rcgc[0] = 1;
388 s->scgc[0] = 1;
389 s->dcgc[0] = 1;
390}
391
392static void stellaris_sys_reset_hold(Object *obj)
393{
394 ssys_state *s = STELLARIS_SYS(obj);
395
396
397 ssys_calculate_system_clock(s, true);
398}
399
400static void stellaris_sys_reset_exit(Object *obj)
401{
402}
403
404static int stellaris_sys_post_load(void *opaque, int version_id)
405{
406 ssys_state *s = opaque;
407
408 ssys_calculate_system_clock(s, false);
409
410 return 0;
411}
412
413static const VMStateDescription vmstate_stellaris_sys = {
414 .name = "stellaris_sys",
415 .version_id = 2,
416 .minimum_version_id = 1,
417 .post_load = stellaris_sys_post_load,
418 .fields = (VMStateField[]) {
419 VMSTATE_UINT32(pborctl, ssys_state),
420 VMSTATE_UINT32(ldopctl, ssys_state),
421 VMSTATE_UINT32(int_mask, ssys_state),
422 VMSTATE_UINT32(int_status, ssys_state),
423 VMSTATE_UINT32(resc, ssys_state),
424 VMSTATE_UINT32(rcc, ssys_state),
425 VMSTATE_UINT32_V(rcc2, ssys_state, 2),
426 VMSTATE_UINT32_ARRAY(rcgc, ssys_state, 3),
427 VMSTATE_UINT32_ARRAY(scgc, ssys_state, 3),
428 VMSTATE_UINT32_ARRAY(dcgc, ssys_state, 3),
429 VMSTATE_UINT32(clkvclr, ssys_state),
430 VMSTATE_UINT32(ldoarst, ssys_state),
431
432 VMSTATE_END_OF_LIST()
433 }
434};
435
436static Property stellaris_sys_properties[] = {
437 DEFINE_PROP_UINT32("user0", ssys_state, user0, 0),
438 DEFINE_PROP_UINT32("user1", ssys_state, user1, 0),
439 DEFINE_PROP_UINT32("did0", ssys_state, did0, 0),
440 DEFINE_PROP_UINT32("did1", ssys_state, did1, 0),
441 DEFINE_PROP_UINT32("dc0", ssys_state, dc0, 0),
442 DEFINE_PROP_UINT32("dc1", ssys_state, dc1, 0),
443 DEFINE_PROP_UINT32("dc2", ssys_state, dc2, 0),
444 DEFINE_PROP_UINT32("dc3", ssys_state, dc3, 0),
445 DEFINE_PROP_UINT32("dc4", ssys_state, dc4, 0),
446 DEFINE_PROP_END_OF_LIST()
447};
448
449static void stellaris_sys_instance_init(Object *obj)
450{
451 ssys_state *s = STELLARIS_SYS(obj);
452 SysBusDevice *sbd = SYS_BUS_DEVICE(s);
453
454 memory_region_init_io(&s->iomem, obj, &ssys_ops, s, "ssys", 0x00001000);
455 sysbus_init_mmio(sbd, &s->iomem);
456 sysbus_init_irq(sbd, &s->irq);
457 s->sysclk = qdev_init_clock_out(DEVICE(s), "SYSCLK");
458}
459
460
461
462#define TYPE_STELLARIS_I2C "stellaris-i2c"
463OBJECT_DECLARE_SIMPLE_TYPE(stellaris_i2c_state, STELLARIS_I2C)
464
465struct stellaris_i2c_state {
466 SysBusDevice parent_obj;
467
468 I2CBus *bus;
469 qemu_irq irq;
470 MemoryRegion iomem;
471 uint32_t msa;
472 uint32_t mcs;
473 uint32_t mdr;
474 uint32_t mtpr;
475 uint32_t mimr;
476 uint32_t mris;
477 uint32_t mcr;
478};
479
480#define STELLARIS_I2C_MCS_BUSY 0x01
481#define STELLARIS_I2C_MCS_ERROR 0x02
482#define STELLARIS_I2C_MCS_ADRACK 0x04
483#define STELLARIS_I2C_MCS_DATACK 0x08
484#define STELLARIS_I2C_MCS_ARBLST 0x10
485#define STELLARIS_I2C_MCS_IDLE 0x20
486#define STELLARIS_I2C_MCS_BUSBSY 0x40
487
488static uint64_t stellaris_i2c_read(void *opaque, hwaddr offset,
489 unsigned size)
490{
491 stellaris_i2c_state *s = (stellaris_i2c_state *)opaque;
492
493 switch (offset) {
494 case 0x00:
495 return s->msa;
496 case 0x04:
497
498 return s->mcs | STELLARIS_I2C_MCS_IDLE;
499 case 0x08:
500 return s->mdr;
501 case 0x0c:
502 return s->mtpr;
503 case 0x10:
504 return s->mimr;
505 case 0x14:
506 return s->mris;
507 case 0x18:
508 return s->mris & s->mimr;
509 case 0x20:
510 return s->mcr;
511 default:
512 qemu_log_mask(LOG_GUEST_ERROR,
513 "stellaris_i2c: read at bad offset 0x%x\n", (int)offset);
514 return 0;
515 }
516}
517
518static void stellaris_i2c_update(stellaris_i2c_state *s)
519{
520 int level;
521
522 level = (s->mris & s->mimr) != 0;
523 qemu_set_irq(s->irq, level);
524}
525
526static void stellaris_i2c_write(void *opaque, hwaddr offset,
527 uint64_t value, unsigned size)
528{
529 stellaris_i2c_state *s = (stellaris_i2c_state *)opaque;
530
531 switch (offset) {
532 case 0x00:
533 s->msa = value & 0xff;
534 break;
535 case 0x04:
536 if ((s->mcr & 0x10) == 0) {
537
538 break;
539 }
540
541 if ((value & 2) && (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) {
542 if (i2c_start_transfer(s->bus, s->msa >> 1, s->msa & 1)) {
543 s->mcs |= STELLARIS_I2C_MCS_ARBLST;
544 } else {
545 s->mcs &= ~STELLARIS_I2C_MCS_ARBLST;
546 s->mcs |= STELLARIS_I2C_MCS_BUSBSY;
547 }
548 }
549
550 if (!i2c_bus_busy(s->bus)
551 || (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) {
552 s->mcs |= STELLARIS_I2C_MCS_ERROR;
553 break;
554 }
555 s->mcs &= ~STELLARIS_I2C_MCS_ERROR;
556 if (value & 1) {
557
558
559 if (s->msa & 1) {
560
561 s->mdr = i2c_recv(s->bus);
562 } else {
563
564 i2c_send(s->bus, s->mdr);
565 }
566
567 s->mris |= 1;
568 }
569 if (value & 4) {
570
571 i2c_end_transfer(s->bus);
572 s->mcs &= ~STELLARIS_I2C_MCS_BUSBSY;
573 }
574 break;
575 case 0x08:
576 s->mdr = value & 0xff;
577 break;
578 case 0x0c:
579 s->mtpr = value & 0xff;
580 break;
581 case 0x10:
582 s->mimr = 1;
583 break;
584 case 0x1c:
585 s->mris &= ~value;
586 break;
587 case 0x20:
588 if (value & 1) {
589 qemu_log_mask(LOG_UNIMP,
590 "stellaris_i2c: Loopback not implemented\n");
591 }
592 if (value & 0x20) {
593 qemu_log_mask(LOG_UNIMP,
594 "stellaris_i2c: Slave mode not implemented\n");
595 }
596 s->mcr = value & 0x31;
597 break;
598 default:
599 qemu_log_mask(LOG_GUEST_ERROR,
600 "stellaris_i2c: write at bad offset 0x%x\n", (int)offset);
601 }
602 stellaris_i2c_update(s);
603}
604
605static void stellaris_i2c_reset(stellaris_i2c_state *s)
606{
607 if (s->mcs & STELLARIS_I2C_MCS_BUSBSY)
608 i2c_end_transfer(s->bus);
609
610 s->msa = 0;
611 s->mcs = 0;
612 s->mdr = 0;
613 s->mtpr = 1;
614 s->mimr = 0;
615 s->mris = 0;
616 s->mcr = 0;
617 stellaris_i2c_update(s);
618}
619
620static const MemoryRegionOps stellaris_i2c_ops = {
621 .read = stellaris_i2c_read,
622 .write = stellaris_i2c_write,
623 .endianness = DEVICE_NATIVE_ENDIAN,
624};
625
626static const VMStateDescription vmstate_stellaris_i2c = {
627 .name = "stellaris_i2c",
628 .version_id = 1,
629 .minimum_version_id = 1,
630 .fields = (VMStateField[]) {
631 VMSTATE_UINT32(msa, stellaris_i2c_state),
632 VMSTATE_UINT32(mcs, stellaris_i2c_state),
633 VMSTATE_UINT32(mdr, stellaris_i2c_state),
634 VMSTATE_UINT32(mtpr, stellaris_i2c_state),
635 VMSTATE_UINT32(mimr, stellaris_i2c_state),
636 VMSTATE_UINT32(mris, stellaris_i2c_state),
637 VMSTATE_UINT32(mcr, stellaris_i2c_state),
638 VMSTATE_END_OF_LIST()
639 }
640};
641
642static void stellaris_i2c_init(Object *obj)
643{
644 DeviceState *dev = DEVICE(obj);
645 stellaris_i2c_state *s = STELLARIS_I2C(obj);
646 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
647 I2CBus *bus;
648
649 sysbus_init_irq(sbd, &s->irq);
650 bus = i2c_init_bus(dev, "i2c");
651 s->bus = bus;
652
653 memory_region_init_io(&s->iomem, obj, &stellaris_i2c_ops, s,
654 "i2c", 0x1000);
655 sysbus_init_mmio(sbd, &s->iomem);
656
657 stellaris_i2c_reset(s);
658}
659
660
661
662
663#define STELLARIS_ADC_EM_CONTROLLER 0
664#define STELLARIS_ADC_EM_COMP 1
665#define STELLARIS_ADC_EM_EXTERNAL 4
666#define STELLARIS_ADC_EM_TIMER 5
667#define STELLARIS_ADC_EM_PWM0 6
668#define STELLARIS_ADC_EM_PWM1 7
669#define STELLARIS_ADC_EM_PWM2 8
670
671#define STELLARIS_ADC_FIFO_EMPTY 0x0100
672#define STELLARIS_ADC_FIFO_FULL 0x1000
673
674#define TYPE_STELLARIS_ADC "stellaris-adc"
675typedef struct StellarisADCState stellaris_adc_state;
676DECLARE_INSTANCE_CHECKER(stellaris_adc_state, STELLARIS_ADC,
677 TYPE_STELLARIS_ADC)
678
679struct StellarisADCState {
680 SysBusDevice parent_obj;
681
682 MemoryRegion iomem;
683 uint32_t actss;
684 uint32_t ris;
685 uint32_t im;
686 uint32_t emux;
687 uint32_t ostat;
688 uint32_t ustat;
689 uint32_t sspri;
690 uint32_t sac;
691 struct {
692 uint32_t state;
693 uint32_t data[16];
694 } fifo[4];
695 uint32_t ssmux[4];
696 uint32_t ssctl[4];
697 uint32_t noise;
698 qemu_irq irq[4];
699};
700
701static uint32_t stellaris_adc_fifo_read(stellaris_adc_state *s, int n)
702{
703 int tail;
704
705 tail = s->fifo[n].state & 0xf;
706 if (s->fifo[n].state & STELLARIS_ADC_FIFO_EMPTY) {
707 s->ustat |= 1 << n;
708 } else {
709 s->fifo[n].state = (s->fifo[n].state & ~0xf) | ((tail + 1) & 0xf);
710 s->fifo[n].state &= ~STELLARIS_ADC_FIFO_FULL;
711 if (tail + 1 == ((s->fifo[n].state >> 4) & 0xf))
712 s->fifo[n].state |= STELLARIS_ADC_FIFO_EMPTY;
713 }
714 return s->fifo[n].data[tail];
715}
716
717static void stellaris_adc_fifo_write(stellaris_adc_state *s, int n,
718 uint32_t value)
719{
720 int head;
721
722
723
724 head = (s->fifo[n].state >> 4) & 0xf;
725 if (s->fifo[n].state & STELLARIS_ADC_FIFO_FULL) {
726 s->ostat |= 1 << n;
727 return;
728 }
729 s->fifo[n].data[head] = value;
730 head = (head + 1) & 0xf;
731 s->fifo[n].state &= ~STELLARIS_ADC_FIFO_EMPTY;
732 s->fifo[n].state = (s->fifo[n].state & ~0xf0) | (head << 4);
733 if ((s->fifo[n].state & 0xf) == head)
734 s->fifo[n].state |= STELLARIS_ADC_FIFO_FULL;
735}
736
737static void stellaris_adc_update(stellaris_adc_state *s)
738{
739 int level;
740 int n;
741
742 for (n = 0; n < 4; n++) {
743 level = (s->ris & s->im & (1 << n)) != 0;
744 qemu_set_irq(s->irq[n], level);
745 }
746}
747
748static void stellaris_adc_trigger(void *opaque, int irq, int level)
749{
750 stellaris_adc_state *s = (stellaris_adc_state *)opaque;
751 int n;
752
753 for (n = 0; n < 4; n++) {
754 if ((s->actss & (1 << n)) == 0) {
755 continue;
756 }
757
758 if (((s->emux >> (n * 4)) & 0xff) != 5) {
759 continue;
760 }
761
762
763
764 s->noise = s->noise * 314159 + 1;
765
766 stellaris_adc_fifo_write(s, n, 0x200 + ((s->noise >> 16) & 7));
767 s->ris |= (1 << n);
768 stellaris_adc_update(s);
769 }
770}
771
772static void stellaris_adc_reset(stellaris_adc_state *s)
773{
774 int n;
775
776 for (n = 0; n < 4; n++) {
777 s->ssmux[n] = 0;
778 s->ssctl[n] = 0;
779 s->fifo[n].state = STELLARIS_ADC_FIFO_EMPTY;
780 }
781}
782
783static uint64_t stellaris_adc_read(void *opaque, hwaddr offset,
784 unsigned size)
785{
786 stellaris_adc_state *s = (stellaris_adc_state *)opaque;
787
788
789 if (offset >= 0x40 && offset < 0xc0) {
790 int n;
791 n = (offset - 0x40) >> 5;
792 switch (offset & 0x1f) {
793 case 0x00:
794 return s->ssmux[n];
795 case 0x04:
796 return s->ssctl[n];
797 case 0x08:
798 return stellaris_adc_fifo_read(s, n);
799 case 0x0c:
800 return s->fifo[n].state;
801 default:
802 break;
803 }
804 }
805 switch (offset) {
806 case 0x00:
807 return s->actss;
808 case 0x04:
809 return s->ris;
810 case 0x08:
811 return s->im;
812 case 0x0c:
813 return s->ris & s->im;
814 case 0x10:
815 return s->ostat;
816 case 0x14:
817 return s->emux;
818 case 0x18:
819 return s->ustat;
820 case 0x20:
821 return s->sspri;
822 case 0x30:
823 return s->sac;
824 default:
825 qemu_log_mask(LOG_GUEST_ERROR,
826 "stellaris_adc: read at bad offset 0x%x\n", (int)offset);
827 return 0;
828 }
829}
830
831static void stellaris_adc_write(void *opaque, hwaddr offset,
832 uint64_t value, unsigned size)
833{
834 stellaris_adc_state *s = (stellaris_adc_state *)opaque;
835
836
837 if (offset >= 0x40 && offset < 0xc0) {
838 int n;
839 n = (offset - 0x40) >> 5;
840 switch (offset & 0x1f) {
841 case 0x00:
842 s->ssmux[n] = value & 0x33333333;
843 return;
844 case 0x04:
845 if (value != 6) {
846 qemu_log_mask(LOG_UNIMP,
847 "ADC: Unimplemented sequence %" PRIx64 "\n",
848 value);
849 }
850 s->ssctl[n] = value;
851 return;
852 default:
853 break;
854 }
855 }
856 switch (offset) {
857 case 0x00:
858 s->actss = value & 0xf;
859 break;
860 case 0x08:
861 s->im = value;
862 break;
863 case 0x0c:
864 s->ris &= ~value;
865 break;
866 case 0x10:
867 s->ostat &= ~value;
868 break;
869 case 0x14:
870 s->emux = value;
871 break;
872 case 0x18:
873 s->ustat &= ~value;
874 break;
875 case 0x20:
876 s->sspri = value;
877 break;
878 case 0x28:
879 qemu_log_mask(LOG_UNIMP, "ADC: sample initiate unimplemented\n");
880 break;
881 case 0x30:
882 s->sac = value;
883 break;
884 default:
885 qemu_log_mask(LOG_GUEST_ERROR,
886 "stellaris_adc: write at bad offset 0x%x\n", (int)offset);
887 }
888 stellaris_adc_update(s);
889}
890
891static const MemoryRegionOps stellaris_adc_ops = {
892 .read = stellaris_adc_read,
893 .write = stellaris_adc_write,
894 .endianness = DEVICE_NATIVE_ENDIAN,
895};
896
897static const VMStateDescription vmstate_stellaris_adc = {
898 .name = "stellaris_adc",
899 .version_id = 1,
900 .minimum_version_id = 1,
901 .fields = (VMStateField[]) {
902 VMSTATE_UINT32(actss, stellaris_adc_state),
903 VMSTATE_UINT32(ris, stellaris_adc_state),
904 VMSTATE_UINT32(im, stellaris_adc_state),
905 VMSTATE_UINT32(emux, stellaris_adc_state),
906 VMSTATE_UINT32(ostat, stellaris_adc_state),
907 VMSTATE_UINT32(ustat, stellaris_adc_state),
908 VMSTATE_UINT32(sspri, stellaris_adc_state),
909 VMSTATE_UINT32(sac, stellaris_adc_state),
910 VMSTATE_UINT32(fifo[0].state, stellaris_adc_state),
911 VMSTATE_UINT32_ARRAY(fifo[0].data, stellaris_adc_state, 16),
912 VMSTATE_UINT32(ssmux[0], stellaris_adc_state),
913 VMSTATE_UINT32(ssctl[0], stellaris_adc_state),
914 VMSTATE_UINT32(fifo[1].state, stellaris_adc_state),
915 VMSTATE_UINT32_ARRAY(fifo[1].data, stellaris_adc_state, 16),
916 VMSTATE_UINT32(ssmux[1], stellaris_adc_state),
917 VMSTATE_UINT32(ssctl[1], stellaris_adc_state),
918 VMSTATE_UINT32(fifo[2].state, stellaris_adc_state),
919 VMSTATE_UINT32_ARRAY(fifo[2].data, stellaris_adc_state, 16),
920 VMSTATE_UINT32(ssmux[2], stellaris_adc_state),
921 VMSTATE_UINT32(ssctl[2], stellaris_adc_state),
922 VMSTATE_UINT32(fifo[3].state, stellaris_adc_state),
923 VMSTATE_UINT32_ARRAY(fifo[3].data, stellaris_adc_state, 16),
924 VMSTATE_UINT32(ssmux[3], stellaris_adc_state),
925 VMSTATE_UINT32(ssctl[3], stellaris_adc_state),
926 VMSTATE_UINT32(noise, stellaris_adc_state),
927 VMSTATE_END_OF_LIST()
928 }
929};
930
931static void stellaris_adc_init(Object *obj)
932{
933 DeviceState *dev = DEVICE(obj);
934 stellaris_adc_state *s = STELLARIS_ADC(obj);
935 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
936 int n;
937
938 for (n = 0; n < 4; n++) {
939 sysbus_init_irq(sbd, &s->irq[n]);
940 }
941
942 memory_region_init_io(&s->iomem, obj, &stellaris_adc_ops, s,
943 "adc", 0x1000);
944 sysbus_init_mmio(sbd, &s->iomem);
945 stellaris_adc_reset(s);
946 qdev_init_gpio_in(dev, stellaris_adc_trigger, 1);
947}
948
949
950static stellaris_board_info stellaris_boards[] = {
951 { "LM3S811EVB",
952 0,
953 0x0032000e,
954 0x001f001f,
955 0x001132bf,
956 0x01071013,
957 0x3f0f01ff,
958 0x0000001f,
959 BP_OLED_I2C
960 },
961 { "LM3S6965EVB",
962 0x10010002,
963 0x1073402e,
964 0x00ff007f,
965 0x001133ff,
966 0x030f5317,
967 0x0f0f87ff,
968 0x5000007f,
969 BP_OLED_SSI | BP_GAMEPAD
970 }
971};
972
973static void stellaris_init(MachineState *ms, stellaris_board_info *board)
974{
975 static const int uart_irq[] = {5, 6, 33, 34};
976 static const int timer_irq[] = {19, 21, 23, 35};
977 static const uint32_t gpio_addr[7] =
978 { 0x40004000, 0x40005000, 0x40006000, 0x40007000,
979 0x40024000, 0x40025000, 0x40026000};
980 static const int gpio_irq[7] = {0, 1, 2, 3, 4, 30, 31};
981
982
983
984
985
986
987
988
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990
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998
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1003
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1008
1009
1010
1011
1012
1013
1014
1015
1016 DeviceState *gpio_dev[7], *nvic;
1017 qemu_irq gpio_in[7][8];
1018 qemu_irq gpio_out[7][8];
1019 qemu_irq adc;
1020 int sram_size;
1021 int flash_size;
1022 I2CBus *i2c;
1023 DeviceState *dev;
1024 DeviceState *ssys_dev;
1025 int i;
1026 int j;
1027 const uint8_t *macaddr;
1028
1029 MemoryRegion *sram = g_new(MemoryRegion, 1);
1030 MemoryRegion *flash = g_new(MemoryRegion, 1);
1031 MemoryRegion *system_memory = get_system_memory();
1032
1033 flash_size = (((board->dc0 & 0xffff) + 1) << 1) * 1024;
1034 sram_size = ((board->dc0 >> 18) + 1) * 1024;
1035
1036
1037 memory_region_init_rom(flash, NULL, "stellaris.flash", flash_size,
1038 &error_fatal);
1039 memory_region_add_subregion(system_memory, 0, flash);
1040
1041 memory_region_init_ram(sram, NULL, "stellaris.sram", sram_size,
1042 &error_fatal);
1043 memory_region_add_subregion(system_memory, 0x20000000, sram);
1044
1045
1046
1047
1048
1049 ssys_dev = qdev_new(TYPE_STELLARIS_SYS);
1050
1051 macaddr = nd_table[0].macaddr.a;
1052 qdev_prop_set_uint32(ssys_dev, "user0",
1053 macaddr[0] | (macaddr[1] << 8) | (macaddr[2] << 16));
1054 qdev_prop_set_uint32(ssys_dev, "user1",
1055 macaddr[3] | (macaddr[4] << 8) | (macaddr[5] << 16));
1056 qdev_prop_set_uint32(ssys_dev, "did0", board->did0);
1057 qdev_prop_set_uint32(ssys_dev, "did1", board->did1);
1058 qdev_prop_set_uint32(ssys_dev, "dc0", board->dc0);
1059 qdev_prop_set_uint32(ssys_dev, "dc1", board->dc1);
1060 qdev_prop_set_uint32(ssys_dev, "dc2", board->dc2);
1061 qdev_prop_set_uint32(ssys_dev, "dc3", board->dc3);
1062 qdev_prop_set_uint32(ssys_dev, "dc4", board->dc4);
1063 sysbus_realize_and_unref(SYS_BUS_DEVICE(ssys_dev), &error_fatal);
1064
1065 nvic = qdev_new(TYPE_ARMV7M);
1066 qdev_prop_set_uint32(nvic, "num-irq", NUM_IRQ_LINES);
1067 qdev_prop_set_string(nvic, "cpu-type", ms->cpu_type);
1068 qdev_prop_set_bit(nvic, "enable-bitband", true);
1069 qdev_connect_clock_in(nvic, "cpuclk",
1070 qdev_get_clock_out(ssys_dev, "SYSCLK"));
1071
1072 object_property_set_link(OBJECT(nvic), "memory",
1073 OBJECT(get_system_memory()), &error_abort);
1074
1075 sysbus_realize_and_unref(SYS_BUS_DEVICE(nvic), &error_fatal);
1076
1077
1078 sysbus_mmio_map(SYS_BUS_DEVICE(ssys_dev), 0, 0x400fe000);
1079 sysbus_connect_irq(SYS_BUS_DEVICE(ssys_dev), 0, qdev_get_gpio_in(nvic, 28));
1080
1081 if (board->dc1 & (1 << 16)) {
1082 dev = sysbus_create_varargs(TYPE_STELLARIS_ADC, 0x40038000,
1083 qdev_get_gpio_in(nvic, 14),
1084 qdev_get_gpio_in(nvic, 15),
1085 qdev_get_gpio_in(nvic, 16),
1086 qdev_get_gpio_in(nvic, 17),
1087 NULL);
1088 adc = qdev_get_gpio_in(dev, 0);
1089 } else {
1090 adc = NULL;
1091 }
1092 for (i = 0; i < 4; i++) {
1093 if (board->dc2 & (0x10000 << i)) {
1094 SysBusDevice *sbd;
1095
1096 dev = qdev_new(TYPE_STELLARIS_GPTM);
1097 sbd = SYS_BUS_DEVICE(dev);
1098 qdev_connect_clock_in(dev, "clk",
1099 qdev_get_clock_out(ssys_dev, "SYSCLK"));
1100 sysbus_realize_and_unref(sbd, &error_fatal);
1101 sysbus_mmio_map(sbd, 0, 0x40030000 + i * 0x1000);
1102 sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(nvic, timer_irq[i]));
1103
1104
1105 qdev_connect_gpio_out(dev, 0, adc);
1106 }
1107 }
1108
1109 if (board->dc1 & (1 << 3)) {
1110 dev = qdev_new(TYPE_LUMINARY_WATCHDOG);
1111
1112 qdev_connect_clock_in(dev, "WDOGCLK",
1113 qdev_get_clock_out(ssys_dev, "SYSCLK"));
1114
1115 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1116 sysbus_mmio_map(SYS_BUS_DEVICE(dev),
1117 0,
1118 0x40000000u);
1119 sysbus_connect_irq(SYS_BUS_DEVICE(dev),
1120 0,
1121 qdev_get_gpio_in(nvic, 18));
1122 }
1123
1124
1125 for (i = 0; i < 7; i++) {
1126 if (board->dc4 & (1 << i)) {
1127 gpio_dev[i] = sysbus_create_simple("pl061_luminary", gpio_addr[i],
1128 qdev_get_gpio_in(nvic,
1129 gpio_irq[i]));
1130 for (j = 0; j < 8; j++) {
1131 gpio_in[i][j] = qdev_get_gpio_in(gpio_dev[i], j);
1132 gpio_out[i][j] = NULL;
1133 }
1134 }
1135 }
1136
1137 if (board->dc2 & (1 << 12)) {
1138 dev = sysbus_create_simple(TYPE_STELLARIS_I2C, 0x40020000,
1139 qdev_get_gpio_in(nvic, 8));
1140 i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
1141 if (board->peripherals & BP_OLED_I2C) {
1142 i2c_slave_create_simple(i2c, "ssd0303", 0x3d);
1143 }
1144 }
1145
1146 for (i = 0; i < 4; i++) {
1147 if (board->dc2 & (1 << i)) {
1148 pl011_luminary_create(0x4000c000 + i * 0x1000,
1149 qdev_get_gpio_in(nvic, uart_irq[i]),
1150 serial_hd(i));
1151 }
1152 }
1153 if (board->dc2 & (1 << 4)) {
1154 dev = sysbus_create_simple("pl022", 0x40008000,
1155 qdev_get_gpio_in(nvic, 7));
1156 if (board->peripherals & BP_OLED_SSI) {
1157 void *bus;
1158 DeviceState *sddev;
1159 DeviceState *ssddev;
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
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1185
1186
1187
1188
1189
1190
1191
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1201
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1207
1208
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1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223 bus = qdev_get_child_bus(dev, "ssi");
1224
1225 sddev = ssi_create_peripheral(bus, "ssi-sd");
1226 ssddev = ssi_create_peripheral(bus, "ssd0323");
1227 gpio_out[GPIO_D][0] = qemu_irq_split(
1228 qdev_get_gpio_in_named(sddev, SSI_GPIO_CS, 0),
1229 qdev_get_gpio_in_named(ssddev, SSI_GPIO_CS, 0));
1230 gpio_out[GPIO_C][7] = qdev_get_gpio_in(ssddev, 0);
1231
1232
1233 qemu_irq_raise(gpio_out[GPIO_D][0]);
1234 }
1235 }
1236 if (board->dc4 & (1 << 28)) {
1237 DeviceState *enet;
1238
1239 qemu_check_nic_model(&nd_table[0], "stellaris");
1240
1241 enet = qdev_new("stellaris_enet");
1242 qdev_set_nic_properties(enet, &nd_table[0]);
1243 sysbus_realize_and_unref(SYS_BUS_DEVICE(enet), &error_fatal);
1244 sysbus_mmio_map(SYS_BUS_DEVICE(enet), 0, 0x40048000);
1245 sysbus_connect_irq(SYS_BUS_DEVICE(enet), 0, qdev_get_gpio_in(nvic, 42));
1246 }
1247 if (board->peripherals & BP_GAMEPAD) {
1248 qemu_irq gpad_irq[5];
1249 static const int gpad_keycode[5] = { 0xc8, 0xd0, 0xcb, 0xcd, 0x1d };
1250
1251 gpad_irq[0] = qemu_irq_invert(gpio_in[GPIO_E][0]);
1252 gpad_irq[1] = qemu_irq_invert(gpio_in[GPIO_E][1]);
1253 gpad_irq[2] = qemu_irq_invert(gpio_in[GPIO_E][2]);
1254 gpad_irq[3] = qemu_irq_invert(gpio_in[GPIO_E][3]);
1255 gpad_irq[4] = qemu_irq_invert(gpio_in[GPIO_F][1]);
1256
1257 stellaris_gamepad_init(5, gpad_irq, gpad_keycode);
1258 }
1259 for (i = 0; i < 7; i++) {
1260 if (board->dc4 & (1 << i)) {
1261 for (j = 0; j < 8; j++) {
1262 if (gpio_out[i][j]) {
1263 qdev_connect_gpio_out(gpio_dev[i], j, gpio_out[i][j]);
1264 }
1265 }
1266 }
1267 }
1268
1269
1270
1271
1272 create_unimplemented_device("i2c-0", 0x40002000, 0x1000);
1273 create_unimplemented_device("i2c-2", 0x40021000, 0x1000);
1274 create_unimplemented_device("PWM", 0x40028000, 0x1000);
1275 create_unimplemented_device("QEI-0", 0x4002c000, 0x1000);
1276 create_unimplemented_device("QEI-1", 0x4002d000, 0x1000);
1277 create_unimplemented_device("analogue-comparator", 0x4003c000, 0x1000);
1278 create_unimplemented_device("hibernation", 0x400fc000, 0x1000);
1279 create_unimplemented_device("flash-control", 0x400fd000, 0x1000);
1280
1281 armv7m_load_kernel(ARM_CPU(first_cpu), ms->kernel_filename, flash_size);
1282}
1283
1284
1285static void lm3s811evb_init(MachineState *machine)
1286{
1287 stellaris_init(machine, &stellaris_boards[0]);
1288}
1289
1290static void lm3s6965evb_init(MachineState *machine)
1291{
1292 stellaris_init(machine, &stellaris_boards[1]);
1293}
1294
1295static void lm3s811evb_class_init(ObjectClass *oc, void *data)
1296{
1297 MachineClass *mc = MACHINE_CLASS(oc);
1298
1299 mc->desc = "Stellaris LM3S811EVB (Cortex-M3)";
1300 mc->init = lm3s811evb_init;
1301 mc->ignore_memory_transaction_failures = true;
1302 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");
1303}
1304
1305static const TypeInfo lm3s811evb_type = {
1306 .name = MACHINE_TYPE_NAME("lm3s811evb"),
1307 .parent = TYPE_MACHINE,
1308 .class_init = lm3s811evb_class_init,
1309};
1310
1311static void lm3s6965evb_class_init(ObjectClass *oc, void *data)
1312{
1313 MachineClass *mc = MACHINE_CLASS(oc);
1314
1315 mc->desc = "Stellaris LM3S6965EVB (Cortex-M3)";
1316 mc->init = lm3s6965evb_init;
1317 mc->ignore_memory_transaction_failures = true;
1318 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");
1319}
1320
1321static const TypeInfo lm3s6965evb_type = {
1322 .name = MACHINE_TYPE_NAME("lm3s6965evb"),
1323 .parent = TYPE_MACHINE,
1324 .class_init = lm3s6965evb_class_init,
1325};
1326
1327static void stellaris_machine_init(void)
1328{
1329 type_register_static(&lm3s811evb_type);
1330 type_register_static(&lm3s6965evb_type);
1331}
1332
1333type_init(stellaris_machine_init)
1334
1335static void stellaris_i2c_class_init(ObjectClass *klass, void *data)
1336{
1337 DeviceClass *dc = DEVICE_CLASS(klass);
1338
1339 dc->vmsd = &vmstate_stellaris_i2c;
1340}
1341
1342static const TypeInfo stellaris_i2c_info = {
1343 .name = TYPE_STELLARIS_I2C,
1344 .parent = TYPE_SYS_BUS_DEVICE,
1345 .instance_size = sizeof(stellaris_i2c_state),
1346 .instance_init = stellaris_i2c_init,
1347 .class_init = stellaris_i2c_class_init,
1348};
1349
1350static void stellaris_adc_class_init(ObjectClass *klass, void *data)
1351{
1352 DeviceClass *dc = DEVICE_CLASS(klass);
1353
1354 dc->vmsd = &vmstate_stellaris_adc;
1355}
1356
1357static const TypeInfo stellaris_adc_info = {
1358 .name = TYPE_STELLARIS_ADC,
1359 .parent = TYPE_SYS_BUS_DEVICE,
1360 .instance_size = sizeof(stellaris_adc_state),
1361 .instance_init = stellaris_adc_init,
1362 .class_init = stellaris_adc_class_init,
1363};
1364
1365static void stellaris_sys_class_init(ObjectClass *klass, void *data)
1366{
1367 DeviceClass *dc = DEVICE_CLASS(klass);
1368 ResettableClass *rc = RESETTABLE_CLASS(klass);
1369
1370 dc->vmsd = &vmstate_stellaris_sys;
1371 rc->phases.enter = stellaris_sys_reset_enter;
1372 rc->phases.hold = stellaris_sys_reset_hold;
1373 rc->phases.exit = stellaris_sys_reset_exit;
1374 device_class_set_props(dc, stellaris_sys_properties);
1375}
1376
1377static const TypeInfo stellaris_sys_info = {
1378 .name = TYPE_STELLARIS_SYS,
1379 .parent = TYPE_SYS_BUS_DEVICE,
1380 .instance_size = sizeof(ssys_state),
1381 .instance_init = stellaris_sys_instance_init,
1382 .class_init = stellaris_sys_class_init,
1383};
1384
1385static void stellaris_register_types(void)
1386{
1387 type_register_static(&stellaris_i2c_info);
1388 type_register_static(&stellaris_adc_info);
1389 type_register_static(&stellaris_sys_info);
1390}
1391
1392type_init(stellaris_register_types)
1393