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24#include "qemu/osdep.h"
25#include "qapi/error.h"
26#include "qemu-common.h"
27#include "qemu/datadir.h"
28#include "cpu.h"
29#include "hw/sysbus.h"
30#include "hw/arm/boot.h"
31#include "hw/arm/primecell.h"
32#include "hw/net/lan9118.h"
33#include "hw/i2c/i2c.h"
34#include "net/net.h"
35#include "sysemu/sysemu.h"
36#include "hw/boards.h"
37#include "hw/loader.h"
38#include "hw/block/flash.h"
39#include "sysemu/device_tree.h"
40#include "qemu/error-report.h"
41#include <libfdt.h>
42#include "hw/char/pl011.h"
43#include "hw/cpu/a9mpcore.h"
44#include "hw/cpu/a15mpcore.h"
45#include "hw/i2c/arm_sbcon_i2c.h"
46#include "hw/sd/sd.h"
47#include "qom/object.h"
48
49#define VEXPRESS_BOARD_ID 0x8e0
50#define VEXPRESS_FLASH_SIZE (64 * 1024 * 1024)
51#define VEXPRESS_FLASH_SECT_SIZE (256 * 1024)
52
53
54
55
56#define NUM_VIRTIO_TRANSPORTS 4
57
58
59
60
61
62
63
64
65
66enum {
67 VE_SYSREGS,
68 VE_SP810,
69 VE_SERIALPCI,
70 VE_PL041,
71 VE_MMCI,
72 VE_KMI0,
73 VE_KMI1,
74 VE_UART0,
75 VE_UART1,
76 VE_UART2,
77 VE_UART3,
78 VE_WDT,
79 VE_TIMER01,
80 VE_TIMER23,
81 VE_SERIALDVI,
82 VE_RTC,
83 VE_COMPACTFLASH,
84 VE_CLCD,
85 VE_NORFLASH0,
86 VE_NORFLASH1,
87 VE_NORFLASHALIAS,
88 VE_SRAM,
89 VE_VIDEORAM,
90 VE_ETHERNET,
91 VE_USB,
92 VE_DAPROM,
93 VE_VIRTIO,
94};
95
96static hwaddr motherboard_legacy_map[] = {
97 [VE_NORFLASHALIAS] = 0,
98
99 [VE_SYSREGS] = 0x10000000,
100 [VE_SP810] = 0x10001000,
101 [VE_SERIALPCI] = 0x10002000,
102 [VE_PL041] = 0x10004000,
103 [VE_MMCI] = 0x10005000,
104 [VE_KMI0] = 0x10006000,
105 [VE_KMI1] = 0x10007000,
106 [VE_UART0] = 0x10009000,
107 [VE_UART1] = 0x1000a000,
108 [VE_UART2] = 0x1000b000,
109 [VE_UART3] = 0x1000c000,
110 [VE_WDT] = 0x1000f000,
111 [VE_TIMER01] = 0x10011000,
112 [VE_TIMER23] = 0x10012000,
113 [VE_VIRTIO] = 0x10013000,
114 [VE_SERIALDVI] = 0x10016000,
115 [VE_RTC] = 0x10017000,
116 [VE_COMPACTFLASH] = 0x1001a000,
117 [VE_CLCD] = 0x1001f000,
118
119 [VE_NORFLASH0] = 0x40000000,
120
121 [VE_NORFLASH1] = 0x44000000,
122
123 [VE_SRAM] = 0x48000000,
124
125 [VE_VIDEORAM] = 0x4c000000,
126 [VE_ETHERNET] = 0x4e000000,
127 [VE_USB] = 0x4f000000,
128};
129
130static hwaddr motherboard_aseries_map[] = {
131 [VE_NORFLASHALIAS] = 0,
132
133 [VE_NORFLASH0] = 0x08000000,
134
135 [VE_NORFLASH1] = 0x0c000000,
136
137
138 [VE_SRAM] = 0x14000000,
139
140 [VE_VIDEORAM] = 0x18000000,
141 [VE_ETHERNET] = 0x1a000000,
142 [VE_USB] = 0x1b000000,
143
144 [VE_DAPROM] = 0x1c000000,
145 [VE_SYSREGS] = 0x1c010000,
146 [VE_SP810] = 0x1c020000,
147 [VE_SERIALPCI] = 0x1c030000,
148 [VE_PL041] = 0x1c040000,
149 [VE_MMCI] = 0x1c050000,
150 [VE_KMI0] = 0x1c060000,
151 [VE_KMI1] = 0x1c070000,
152 [VE_UART0] = 0x1c090000,
153 [VE_UART1] = 0x1c0a0000,
154 [VE_UART2] = 0x1c0b0000,
155 [VE_UART3] = 0x1c0c0000,
156 [VE_WDT] = 0x1c0f0000,
157 [VE_TIMER01] = 0x1c110000,
158 [VE_TIMER23] = 0x1c120000,
159 [VE_VIRTIO] = 0x1c130000,
160 [VE_SERIALDVI] = 0x1c160000,
161 [VE_RTC] = 0x1c170000,
162 [VE_COMPACTFLASH] = 0x1c1a0000,
163 [VE_CLCD] = 0x1c1f0000,
164};
165
166
167
168typedef struct VEDBoardInfo VEDBoardInfo;
169
170struct VexpressMachineClass {
171 MachineClass parent;
172 VEDBoardInfo *daughterboard;
173};
174
175struct VexpressMachineState {
176 MachineState parent;
177 bool secure;
178 bool virt;
179};
180
181#define TYPE_VEXPRESS_MACHINE "vexpress"
182#define TYPE_VEXPRESS_A9_MACHINE MACHINE_TYPE_NAME("vexpress-a9")
183#define TYPE_VEXPRESS_A15_MACHINE MACHINE_TYPE_NAME("vexpress-a15")
184OBJECT_DECLARE_TYPE(VexpressMachineState, VexpressMachineClass, VEXPRESS_MACHINE)
185
186typedef void DBoardInitFn(const VexpressMachineState *machine,
187 ram_addr_t ram_size,
188 const char *cpu_type,
189 qemu_irq *pic);
190
191struct VEDBoardInfo {
192 struct arm_boot_info bootinfo;
193 const hwaddr *motherboard_map;
194 hwaddr loader_start;
195 const hwaddr gic_cpu_if_addr;
196 uint32_t proc_id;
197 uint32_t num_voltage_sensors;
198 const uint32_t *voltages;
199 uint32_t num_clocks;
200 const uint32_t *clocks;
201 DBoardInitFn *init;
202};
203
204static void init_cpus(MachineState *ms, const char *cpu_type,
205 const char *privdev, hwaddr periphbase,
206 qemu_irq *pic, bool secure, bool virt)
207{
208 DeviceState *dev;
209 SysBusDevice *busdev;
210 int n;
211 unsigned int smp_cpus = ms->smp.cpus;
212
213
214 for (n = 0; n < smp_cpus; n++) {
215 Object *cpuobj = object_new(cpu_type);
216
217 if (!secure) {
218 object_property_set_bool(cpuobj, "has_el3", false, NULL);
219 }
220 if (!virt) {
221 if (object_property_find(cpuobj, "has_el2")) {
222 object_property_set_bool(cpuobj, "has_el2", false, NULL);
223 }
224 }
225
226 if (object_property_find(cpuobj, "reset-cbar")) {
227 object_property_set_int(cpuobj, "reset-cbar", periphbase,
228 &error_abort);
229 }
230 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
231 }
232
233
234
235
236
237 dev = qdev_new(privdev);
238 qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
239 busdev = SYS_BUS_DEVICE(dev);
240 sysbus_realize_and_unref(busdev, &error_fatal);
241 sysbus_mmio_map(busdev, 0, periphbase);
242
243
244
245
246
247
248
249 for (n = 0; n < 64; n++) {
250 pic[n] = qdev_get_gpio_in(dev, n);
251 }
252
253
254 for (n = 0; n < smp_cpus; n++) {
255 DeviceState *cpudev = DEVICE(qemu_get_cpu(n));
256
257 sysbus_connect_irq(busdev, n, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
258 sysbus_connect_irq(busdev, n + smp_cpus,
259 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
260 sysbus_connect_irq(busdev, n + 2 * smp_cpus,
261 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
262 sysbus_connect_irq(busdev, n + 3 * smp_cpus,
263 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
264 }
265}
266
267static void a9_daughterboard_init(const VexpressMachineState *vms,
268 ram_addr_t ram_size,
269 const char *cpu_type,
270 qemu_irq *pic)
271{
272 MachineState *machine = MACHINE(vms);
273 MemoryRegion *sysmem = get_system_memory();
274 MemoryRegion *lowram = g_new(MemoryRegion, 1);
275 ram_addr_t low_ram_size;
276
277 if (ram_size > 0x40000000) {
278
279 error_report("vexpress-a9: cannot model more than 1GB RAM");
280 exit(1);
281 }
282
283 low_ram_size = ram_size;
284 if (low_ram_size > 0x4000000) {
285 low_ram_size = 0x4000000;
286 }
287
288
289
290
291 memory_region_init_alias(lowram, NULL, "vexpress.lowmem", machine->ram,
292 0, low_ram_size);
293 memory_region_add_subregion(sysmem, 0x0, lowram);
294 memory_region_add_subregion(sysmem, 0x60000000, machine->ram);
295
296
297 init_cpus(machine, cpu_type, TYPE_A9MPCORE_PRIV, 0x1e000000, pic,
298 vms->secure, vms->virt);
299
300
301
302
303 sysbus_create_simple("pl111", 0x10020000, pic[44]);
304
305
306
307
308
309
310 sysbus_create_simple("sp804", 0x100e4000, pic[48]);
311
312
313
314
315
316
317
318 sysbus_create_varargs("l2x0", 0x1e00a000, NULL);
319}
320
321
322
323
324static const uint32_t a9_voltages[] = {
325 1000000,
326 1000000,
327 1000000,
328 1800000,
329 900000,
330 3300000,
331};
332
333
334static const uint32_t a9_clocks[] = {
335 45000000,
336 23750000,
337 66670000,
338};
339
340static VEDBoardInfo a9_daughterboard = {
341 .motherboard_map = motherboard_legacy_map,
342 .loader_start = 0x60000000,
343 .gic_cpu_if_addr = 0x1e000100,
344 .proc_id = 0x0c000191,
345 .num_voltage_sensors = ARRAY_SIZE(a9_voltages),
346 .voltages = a9_voltages,
347 .num_clocks = ARRAY_SIZE(a9_clocks),
348 .clocks = a9_clocks,
349 .init = a9_daughterboard_init,
350};
351
352static void a15_daughterboard_init(const VexpressMachineState *vms,
353 ram_addr_t ram_size,
354 const char *cpu_type,
355 qemu_irq *pic)
356{
357 MachineState *machine = MACHINE(vms);
358 MemoryRegion *sysmem = get_system_memory();
359 MemoryRegion *sram = g_new(MemoryRegion, 1);
360
361 {
362
363
364
365
366 uint64_t rsz = ram_size;
367 if (rsz > (30ULL * 1024 * 1024 * 1024)) {
368 error_report("vexpress-a15: cannot model more than 30GB RAM");
369 exit(1);
370 }
371 }
372
373
374 memory_region_add_subregion(sysmem, 0x80000000, machine->ram);
375
376
377 init_cpus(machine, cpu_type, TYPE_A15MPCORE_PRIV,
378 0x2c000000, pic, vms->secure, vms->virt);
379
380
381
382
383
384
385
386
387
388
389
390 memory_region_init_ram(sram, NULL, "vexpress.a15sram", 0x10000,
391 &error_fatal);
392 memory_region_add_subregion(sysmem, 0x2e000000, sram);
393
394
395
396}
397
398static const uint32_t a15_voltages[] = {
399 900000,
400};
401
402static const uint32_t a15_clocks[] = {
403 60000000,
404 0,
405 0,
406 0,
407 40000000,
408 23750000,
409 50000000,
410 60000000,
411 40000000,
412};
413
414static VEDBoardInfo a15_daughterboard = {
415 .motherboard_map = motherboard_aseries_map,
416 .loader_start = 0x80000000,
417 .gic_cpu_if_addr = 0x2c002000,
418 .proc_id = 0x14000237,
419 .num_voltage_sensors = ARRAY_SIZE(a15_voltages),
420 .voltages = a15_voltages,
421 .num_clocks = ARRAY_SIZE(a15_clocks),
422 .clocks = a15_clocks,
423 .init = a15_daughterboard_init,
424};
425
426static int add_virtio_mmio_node(void *fdt, uint32_t acells, uint32_t scells,
427 hwaddr addr, hwaddr size, uint32_t intc,
428 int irq)
429{
430
431
432
433
434
435
436
437
438
439
440
441 int rc;
442 char *nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, addr);
443
444 rc = qemu_fdt_add_subnode(fdt, nodename);
445 rc |= qemu_fdt_setprop_string(fdt, nodename,
446 "compatible", "virtio,mmio");
447 rc |= qemu_fdt_setprop_sized_cells(fdt, nodename, "reg",
448 acells, addr, scells, size);
449 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", intc);
450 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 0, irq, 1);
451 qemu_fdt_setprop(fdt, nodename, "dma-coherent", NULL, 0);
452 g_free(nodename);
453 if (rc) {
454 return -1;
455 }
456 return 0;
457}
458
459static uint32_t find_int_controller(void *fdt)
460{
461
462
463
464
465
466
467 const char *compat = "arm,cortex-a9-gic";
468 int offset;
469
470 offset = fdt_node_offset_by_compatible(fdt, -1, compat);
471 if (offset >= 0) {
472 return fdt_get_phandle(fdt, offset);
473 }
474 return 0;
475}
476
477static void vexpress_modify_dtb(const struct arm_boot_info *info, void *fdt)
478{
479 uint32_t acells, scells, intc;
480 const VEDBoardInfo *daughterboard = (const VEDBoardInfo *)info;
481
482 acells = qemu_fdt_getprop_cell(fdt, "/", "#address-cells",
483 NULL, &error_fatal);
484 scells = qemu_fdt_getprop_cell(fdt, "/", "#size-cells",
485 NULL, &error_fatal);
486 intc = find_int_controller(fdt);
487 if (!intc) {
488
489
490
491 warn_report("couldn't find interrupt controller in "
492 "dtb; will not include virtio-mmio devices in the dtb");
493 } else {
494 int i;
495 const hwaddr *map = daughterboard->motherboard_map;
496
497
498
499
500 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) {
501 add_virtio_mmio_node(fdt, acells, scells,
502 map[VE_VIRTIO] + 0x200 * i,
503 0x200, intc, 40 + i);
504 }
505 }
506}
507
508
509
510
511
512static PFlashCFI01 *ve_pflash_cfi01_register(hwaddr base, const char *name,
513 DriveInfo *di)
514{
515 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01);
516
517 if (di) {
518 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(di));
519 }
520
521 qdev_prop_set_uint32(dev, "num-blocks",
522 VEXPRESS_FLASH_SIZE / VEXPRESS_FLASH_SECT_SIZE);
523 qdev_prop_set_uint64(dev, "sector-length", VEXPRESS_FLASH_SECT_SIZE);
524 qdev_prop_set_uint8(dev, "width", 4);
525 qdev_prop_set_uint8(dev, "device-width", 2);
526 qdev_prop_set_bit(dev, "big-endian", false);
527 qdev_prop_set_uint16(dev, "id0", 0x89);
528 qdev_prop_set_uint16(dev, "id1", 0x18);
529 qdev_prop_set_uint16(dev, "id2", 0x00);
530 qdev_prop_set_uint16(dev, "id3", 0x00);
531 qdev_prop_set_string(dev, "name", name);
532 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
533
534 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
535 return PFLASH_CFI01(dev);
536}
537
538static void vexpress_common_init(MachineState *machine)
539{
540 VexpressMachineState *vms = VEXPRESS_MACHINE(machine);
541 VexpressMachineClass *vmc = VEXPRESS_MACHINE_GET_CLASS(machine);
542 VEDBoardInfo *daughterboard = vmc->daughterboard;
543 DeviceState *dev, *sysctl, *pl041;
544 qemu_irq pic[64];
545 uint32_t sys_id;
546 DriveInfo *dinfo;
547 PFlashCFI01 *pflash0;
548 I2CBus *i2c;
549 ram_addr_t vram_size, sram_size;
550 MemoryRegion *sysmem = get_system_memory();
551 MemoryRegion *vram = g_new(MemoryRegion, 1);
552 MemoryRegion *sram = g_new(MemoryRegion, 1);
553 MemoryRegion *flashalias = g_new(MemoryRegion, 1);
554 MemoryRegion *flash0mem;
555 const hwaddr *map = daughterboard->motherboard_map;
556 int i;
557
558 daughterboard->init(vms, machine->ram_size, machine->cpu_type, pic);
559
560
561
562
563 if (machine->firmware) {
564 char *fn;
565 int image_size;
566
567 if (drive_get(IF_PFLASH, 0, 0)) {
568 error_report("The contents of the first flash device may be "
569 "specified with -bios or with -drive if=pflash... "
570 "but you cannot use both options at once");
571 exit(1);
572 }
573 fn = qemu_find_file(QEMU_FILE_TYPE_BIOS, machine->firmware);
574 if (!fn) {
575 error_report("Could not find ROM image '%s'", machine->firmware);
576 exit(1);
577 }
578 image_size = load_image_targphys(fn, map[VE_NORFLASH0],
579 VEXPRESS_FLASH_SIZE);
580 g_free(fn);
581 if (image_size < 0) {
582 error_report("Could not load ROM image '%s'", machine->firmware);
583 exit(1);
584 }
585 }
586
587
588
589
590
591 sys_id = 0x1190f500;
592
593 sysctl = qdev_new("realview_sysctl");
594 qdev_prop_set_uint32(sysctl, "sys_id", sys_id);
595 qdev_prop_set_uint32(sysctl, "proc_id", daughterboard->proc_id);
596 qdev_prop_set_uint32(sysctl, "len-db-voltage",
597 daughterboard->num_voltage_sensors);
598 for (i = 0; i < daughterboard->num_voltage_sensors; i++) {
599 char *propname = g_strdup_printf("db-voltage[%d]", i);
600 qdev_prop_set_uint32(sysctl, propname, daughterboard->voltages[i]);
601 g_free(propname);
602 }
603 qdev_prop_set_uint32(sysctl, "len-db-clock",
604 daughterboard->num_clocks);
605 for (i = 0; i < daughterboard->num_clocks; i++) {
606 char *propname = g_strdup_printf("db-clock[%d]", i);
607 qdev_prop_set_uint32(sysctl, propname, daughterboard->clocks[i]);
608 g_free(propname);
609 }
610 sysbus_realize_and_unref(SYS_BUS_DEVICE(sysctl), &error_fatal);
611 sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, map[VE_SYSREGS]);
612
613
614
615
616 pl041 = qdev_new("pl041");
617 qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512);
618 sysbus_realize_and_unref(SYS_BUS_DEVICE(pl041), &error_fatal);
619 sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, map[VE_PL041]);
620 sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, pic[11]);
621
622 dev = sysbus_create_varargs("pl181", map[VE_MMCI], pic[9], pic[10], NULL);
623
624 qdev_connect_gpio_out_named(dev, "card-read-only", 0,
625 qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT));
626 qdev_connect_gpio_out_named(dev, "card-inserted", 0,
627 qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN));
628 dinfo = drive_get_next(IF_SD);
629 if (dinfo) {
630 DeviceState *card;
631
632 card = qdev_new(TYPE_SD_CARD);
633 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo),
634 &error_fatal);
635 qdev_realize_and_unref(card, qdev_get_child_bus(dev, "sd-bus"),
636 &error_fatal);
637 }
638
639 sysbus_create_simple("pl050_keyboard", map[VE_KMI0], pic[12]);
640 sysbus_create_simple("pl050_mouse", map[VE_KMI1], pic[13]);
641
642 pl011_create(map[VE_UART0], pic[5], serial_hd(0));
643 pl011_create(map[VE_UART1], pic[6], serial_hd(1));
644 pl011_create(map[VE_UART2], pic[7], serial_hd(2));
645 pl011_create(map[VE_UART3], pic[8], serial_hd(3));
646
647 sysbus_create_simple("sp804", map[VE_TIMER01], pic[2]);
648 sysbus_create_simple("sp804", map[VE_TIMER23], pic[3]);
649
650 dev = sysbus_create_simple(TYPE_VERSATILE_I2C, map[VE_SERIALDVI], NULL);
651 i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
652 i2c_slave_create_simple(i2c, "sii9022", 0x39);
653
654 sysbus_create_simple("pl031", map[VE_RTC], pic[4]);
655
656
657
658 sysbus_create_simple("pl111", map[VE_CLCD], pic[14]);
659
660 dinfo = drive_get_next(IF_PFLASH);
661 pflash0 = ve_pflash_cfi01_register(map[VE_NORFLASH0], "vexpress.flash0",
662 dinfo);
663 if (!pflash0) {
664 error_report("vexpress: error registering flash 0");
665 exit(1);
666 }
667
668 if (map[VE_NORFLASHALIAS] != -1) {
669
670 flash0mem = sysbus_mmio_get_region(SYS_BUS_DEVICE(pflash0), 0);
671 memory_region_init_alias(flashalias, NULL, "vexpress.flashalias",
672 flash0mem, 0, VEXPRESS_FLASH_SIZE);
673 memory_region_add_subregion(sysmem, map[VE_NORFLASHALIAS], flashalias);
674 }
675
676 dinfo = drive_get_next(IF_PFLASH);
677 if (!ve_pflash_cfi01_register(map[VE_NORFLASH1], "vexpress.flash1",
678 dinfo)) {
679 error_report("vexpress: error registering flash 1");
680 exit(1);
681 }
682
683 sram_size = 0x2000000;
684 memory_region_init_ram(sram, NULL, "vexpress.sram", sram_size,
685 &error_fatal);
686 memory_region_add_subregion(sysmem, map[VE_SRAM], sram);
687
688 vram_size = 0x800000;
689 memory_region_init_ram(vram, NULL, "vexpress.vram", vram_size,
690 &error_fatal);
691 memory_region_add_subregion(sysmem, map[VE_VIDEORAM], vram);
692
693
694 if (nd_table[0].used) {
695 lan9118_init(&nd_table[0], map[VE_ETHERNET], pic[15]);
696 }
697
698
699
700
701
702
703
704
705
706 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) {
707 sysbus_create_simple("virtio-mmio", map[VE_VIRTIO] + 0x200 * i,
708 pic[40 + i]);
709 }
710
711 daughterboard->bootinfo.ram_size = machine->ram_size;
712 daughterboard->bootinfo.nb_cpus = machine->smp.cpus;
713 daughterboard->bootinfo.board_id = VEXPRESS_BOARD_ID;
714 daughterboard->bootinfo.loader_start = daughterboard->loader_start;
715 daughterboard->bootinfo.smp_loader_start = map[VE_SRAM];
716 daughterboard->bootinfo.smp_bootreg_addr = map[VE_SYSREGS] + 0x30;
717 daughterboard->bootinfo.gic_cpu_if_addr = daughterboard->gic_cpu_if_addr;
718 daughterboard->bootinfo.modify_dtb = vexpress_modify_dtb;
719
720 daughterboard->bootinfo.secure_boot = vms->secure;
721 arm_load_kernel(ARM_CPU(first_cpu), machine, &daughterboard->bootinfo);
722}
723
724static bool vexpress_get_secure(Object *obj, Error **errp)
725{
726 VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
727
728 return vms->secure;
729}
730
731static void vexpress_set_secure(Object *obj, bool value, Error **errp)
732{
733 VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
734
735 vms->secure = value;
736}
737
738static bool vexpress_get_virt(Object *obj, Error **errp)
739{
740 VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
741
742 return vms->virt;
743}
744
745static void vexpress_set_virt(Object *obj, bool value, Error **errp)
746{
747 VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
748
749 vms->virt = value;
750}
751
752static void vexpress_instance_init(Object *obj)
753{
754 VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
755
756
757 vms->secure = true;
758}
759
760static void vexpress_a15_instance_init(Object *obj)
761{
762 VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
763
764
765
766
767
768 vms->virt = true;
769}
770
771static void vexpress_a9_instance_init(Object *obj)
772{
773 VexpressMachineState *vms = VEXPRESS_MACHINE(obj);
774
775
776 vms->virt = false;
777}
778
779static void vexpress_class_init(ObjectClass *oc, void *data)
780{
781 MachineClass *mc = MACHINE_CLASS(oc);
782
783 mc->desc = "ARM Versatile Express";
784 mc->init = vexpress_common_init;
785 mc->max_cpus = 4;
786 mc->ignore_memory_transaction_failures = true;
787 mc->default_ram_id = "vexpress.highmem";
788
789 object_class_property_add_bool(oc, "secure", vexpress_get_secure,
790 vexpress_set_secure);
791 object_class_property_set_description(oc, "secure",
792 "Set on/off to enable/disable the ARM "
793 "Security Extensions (TrustZone)");
794}
795
796static void vexpress_a9_class_init(ObjectClass *oc, void *data)
797{
798 MachineClass *mc = MACHINE_CLASS(oc);
799 VexpressMachineClass *vmc = VEXPRESS_MACHINE_CLASS(oc);
800
801 mc->desc = "ARM Versatile Express for Cortex-A9";
802 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9");
803
804 vmc->daughterboard = &a9_daughterboard;
805}
806
807static void vexpress_a15_class_init(ObjectClass *oc, void *data)
808{
809 MachineClass *mc = MACHINE_CLASS(oc);
810 VexpressMachineClass *vmc = VEXPRESS_MACHINE_CLASS(oc);
811
812 mc->desc = "ARM Versatile Express for Cortex-A15";
813 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
814
815 vmc->daughterboard = &a15_daughterboard;
816
817 object_class_property_add_bool(oc, "virtualization", vexpress_get_virt,
818 vexpress_set_virt);
819 object_class_property_set_description(oc, "virtualization",
820 "Set on/off to enable/disable the ARM "
821 "Virtualization Extensions "
822 "(defaults to same as 'secure')");
823
824}
825
826static const TypeInfo vexpress_info = {
827 .name = TYPE_VEXPRESS_MACHINE,
828 .parent = TYPE_MACHINE,
829 .abstract = true,
830 .instance_size = sizeof(VexpressMachineState),
831 .instance_init = vexpress_instance_init,
832 .class_size = sizeof(VexpressMachineClass),
833 .class_init = vexpress_class_init,
834};
835
836static const TypeInfo vexpress_a9_info = {
837 .name = TYPE_VEXPRESS_A9_MACHINE,
838 .parent = TYPE_VEXPRESS_MACHINE,
839 .class_init = vexpress_a9_class_init,
840 .instance_init = vexpress_a9_instance_init,
841};
842
843static const TypeInfo vexpress_a15_info = {
844 .name = TYPE_VEXPRESS_A15_MACHINE,
845 .parent = TYPE_VEXPRESS_MACHINE,
846 .class_init = vexpress_a15_class_init,
847 .instance_init = vexpress_a15_instance_init,
848};
849
850static void vexpress_machine_init(void)
851{
852 type_register_static(&vexpress_info);
853 type_register_static(&vexpress_a9_info);
854 type_register_static(&vexpress_a15_info);
855}
856
857type_init(vexpress_machine_init);
858