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31#include "qemu/osdep.h"
32#include "qemu-common.h"
33#include "qemu/datadir.h"
34#include "qemu/units.h"
35#include "qemu/option.h"
36#include "monitor/qdev.h"
37#include "qapi/error.h"
38#include "hw/sysbus.h"
39#include "hw/arm/boot.h"
40#include "hw/arm/primecell.h"
41#include "hw/arm/virt.h"
42#include "hw/block/flash.h"
43#include "hw/vfio/vfio-calxeda-xgmac.h"
44#include "hw/vfio/vfio-amd-xgbe.h"
45#include "hw/display/ramfb.h"
46#include "net/net.h"
47#include "sysemu/device_tree.h"
48#include "sysemu/numa.h"
49#include "sysemu/runstate.h"
50#include "sysemu/tpm.h"
51#include "sysemu/kvm.h"
52#include "sysemu/hvf.h"
53#include "hw/loader.h"
54#include "qapi/error.h"
55#include "qemu/bitops.h"
56#include "qemu/error-report.h"
57#include "qemu/module.h"
58#include "hw/pci-host/gpex.h"
59#include "hw/virtio/virtio-pci.h"
60#include "hw/arm/sysbus-fdt.h"
61#include "hw/platform-bus.h"
62#include "hw/qdev-properties.h"
63#include "hw/arm/fdt.h"
64#include "hw/intc/arm_gic.h"
65#include "hw/intc/arm_gicv3_common.h"
66#include "hw/irq.h"
67#include "kvm_arm.h"
68#include "hw/firmware/smbios.h"
69#include "qapi/visitor.h"
70#include "qapi/qapi-visit-common.h"
71#include "standard-headers/linux/input.h"
72#include "hw/arm/smmuv3.h"
73#include "hw/acpi/acpi.h"
74#include "target/arm/internals.h"
75#include "hw/mem/pc-dimm.h"
76#include "hw/mem/nvdimm.h"
77#include "hw/acpi/generic_event_device.h"
78#include "hw/virtio/virtio-iommu.h"
79#include "hw/char/pl011.h"
80#include "qemu/guest-random.h"
81
82#define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \
83 static void virt_##major##_##minor##_class_init(ObjectClass *oc, \
84 void *data) \
85 { \
86 MachineClass *mc = MACHINE_CLASS(oc); \
87 virt_machine_##major##_##minor##_options(mc); \
88 mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \
89 if (latest) { \
90 mc->alias = "virt"; \
91 } \
92 } \
93 static const TypeInfo machvirt_##major##_##minor##_info = { \
94 .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \
95 .parent = TYPE_VIRT_MACHINE, \
96 .class_init = virt_##major##_##minor##_class_init, \
97 }; \
98 static void machvirt_machine_##major##_##minor##_init(void) \
99 { \
100 type_register_static(&machvirt_##major##_##minor##_info); \
101 } \
102 type_init(machvirt_machine_##major##_##minor##_init);
103
104#define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \
105 DEFINE_VIRT_MACHINE_LATEST(major, minor, true)
106#define DEFINE_VIRT_MACHINE(major, minor) \
107 DEFINE_VIRT_MACHINE_LATEST(major, minor, false)
108
109
110
111#define NUM_IRQS 256
112
113#define PLATFORM_BUS_NUM_IRQS 64
114
115
116#define LEGACY_RAMLIMIT_GB 255
117#define LEGACY_RAMLIMIT_BYTES (LEGACY_RAMLIMIT_GB * GiB)
118
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130
131static const MemMapEntry base_memmap[] = {
132
133 [VIRT_FLASH] = { 0, 0x08000000 },
134 [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 },
135
136 [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 },
137 [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 },
138 [VIRT_GIC_V2M] = { 0x08020000, 0x00001000 },
139 [VIRT_GIC_HYP] = { 0x08030000, 0x00010000 },
140 [VIRT_GIC_VCPU] = { 0x08040000, 0x00010000 },
141
142 [VIRT_GIC_ITS] = { 0x08080000, 0x00020000 },
143
144 [VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 },
145 [VIRT_UART] = { 0x09000000, 0x00001000 },
146 [VIRT_RTC] = { 0x09010000, 0x00001000 },
147 [VIRT_FW_CFG] = { 0x09020000, 0x00000018 },
148 [VIRT_GPIO] = { 0x09030000, 0x00001000 },
149 [VIRT_SECURE_UART] = { 0x09040000, 0x00001000 },
150 [VIRT_SMMU] = { 0x09050000, 0x00020000 },
151 [VIRT_PCDIMM_ACPI] = { 0x09070000, MEMORY_HOTPLUG_IO_LEN },
152 [VIRT_ACPI_GED] = { 0x09080000, ACPI_GED_EVT_SEL_LEN },
153 [VIRT_NVDIMM_ACPI] = { 0x09090000, NVDIMM_ACPI_IO_LEN},
154 [VIRT_PVTIME] = { 0x090a0000, 0x00010000 },
155 [VIRT_SECURE_GPIO] = { 0x090b0000, 0x00001000 },
156 [VIRT_MMIO] = { 0x0a000000, 0x00000200 },
157
158 [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 },
159 [VIRT_SECURE_MEM] = { 0x0e000000, 0x01000000 },
160 [VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 },
161 [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 },
162 [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 },
163
164 [VIRT_MEM] = { GiB, LEGACY_RAMLIMIT_BYTES },
165};
166
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176
177static MemMapEntry extended_memmap[] = {
178
179 [VIRT_HIGH_GIC_REDIST2] = { 0x0, 64 * MiB },
180 [VIRT_HIGH_PCIE_ECAM] = { 0x0, 256 * MiB },
181
182 [VIRT_HIGH_PCIE_MMIO] = { 0x0, 512 * GiB },
183};
184
185static const int a15irqmap[] = {
186 [VIRT_UART] = 1,
187 [VIRT_RTC] = 2,
188 [VIRT_PCIE] = 3,
189 [VIRT_GPIO] = 7,
190 [VIRT_SECURE_UART] = 8,
191 [VIRT_ACPI_GED] = 9,
192 [VIRT_MMIO] = 16,
193 [VIRT_GIC_V2M] = 48,
194 [VIRT_SMMU] = 74,
195 [VIRT_PLATFORM_BUS] = 112,
196};
197
198static const char *valid_cpus[] = {
199 ARM_CPU_TYPE_NAME("cortex-a7"),
200 ARM_CPU_TYPE_NAME("cortex-a15"),
201 ARM_CPU_TYPE_NAME("cortex-a53"),
202 ARM_CPU_TYPE_NAME("cortex-a57"),
203 ARM_CPU_TYPE_NAME("cortex-a72"),
204 ARM_CPU_TYPE_NAME("a64fx"),
205 ARM_CPU_TYPE_NAME("host"),
206 ARM_CPU_TYPE_NAME("max"),
207};
208
209static bool cpu_type_valid(const char *cpu)
210{
211 int i;
212
213 for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) {
214 if (strcmp(cpu, valid_cpus[i]) == 0) {
215 return true;
216 }
217 }
218 return false;
219}
220
221static void create_kaslr_seed(MachineState *ms, const char *node)
222{
223 uint64_t seed;
224
225 if (qemu_guest_getrandom(&seed, sizeof(seed), NULL)) {
226 return;
227 }
228 qemu_fdt_setprop_u64(ms->fdt, node, "kaslr-seed", seed);
229}
230
231static void create_fdt(VirtMachineState *vms)
232{
233 MachineState *ms = MACHINE(vms);
234 int nb_numa_nodes = ms->numa_state->num_nodes;
235 void *fdt = create_device_tree(&vms->fdt_size);
236
237 if (!fdt) {
238 error_report("create_device_tree() failed");
239 exit(1);
240 }
241
242 ms->fdt = fdt;
243
244
245 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt");
246 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
247 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
248
249
250 qemu_fdt_add_subnode(fdt, "/chosen");
251 create_kaslr_seed(ms, "/chosen");
252
253 if (vms->secure) {
254 qemu_fdt_add_subnode(fdt, "/secure-chosen");
255 create_kaslr_seed(ms, "/secure-chosen");
256 }
257
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262
263 vms->clock_phandle = qemu_fdt_alloc_phandle(fdt);
264 qemu_fdt_add_subnode(fdt, "/apb-pclk");
265 qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock");
266 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0);
267 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000);
268 qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names",
269 "clk24mhz");
270 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vms->clock_phandle);
271
272 if (nb_numa_nodes > 0 && ms->numa_state->have_numa_distance) {
273 int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t);
274 uint32_t *matrix = g_malloc0(size);
275 int idx, i, j;
276
277 for (i = 0; i < nb_numa_nodes; i++) {
278 for (j = 0; j < nb_numa_nodes; j++) {
279 idx = (i * nb_numa_nodes + j) * 3;
280 matrix[idx + 0] = cpu_to_be32(i);
281 matrix[idx + 1] = cpu_to_be32(j);
282 matrix[idx + 2] =
283 cpu_to_be32(ms->numa_state->nodes[i].distance[j]);
284 }
285 }
286
287 qemu_fdt_add_subnode(fdt, "/distance-map");
288 qemu_fdt_setprop_string(fdt, "/distance-map", "compatible",
289 "numa-distance-map-v1");
290 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix",
291 matrix, size);
292 g_free(matrix);
293 }
294}
295
296static void fdt_add_timer_nodes(const VirtMachineState *vms)
297{
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316 ARMCPU *armcpu;
317 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
318 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
319 MachineState *ms = MACHINE(vms);
320
321 if (vmc->claim_edge_triggered_timers) {
322 irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI;
323 }
324
325 if (vms->gic_version == VIRT_GIC_VERSION_2) {
326 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
327 GIC_FDT_IRQ_PPI_CPU_WIDTH,
328 (1 << MACHINE(vms)->smp.cpus) - 1);
329 }
330
331 qemu_fdt_add_subnode(ms->fdt, "/timer");
332
333 armcpu = ARM_CPU(qemu_get_cpu(0));
334 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) {
335 const char compat[] = "arm,armv8-timer\0arm,armv7-timer";
336 qemu_fdt_setprop(ms->fdt, "/timer", "compatible",
337 compat, sizeof(compat));
338 } else {
339 qemu_fdt_setprop_string(ms->fdt, "/timer", "compatible",
340 "arm,armv7-timer");
341 }
342 qemu_fdt_setprop(ms->fdt, "/timer", "always-on", NULL, 0);
343 qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts",
344 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_S_EL1_IRQ, irqflags,
345 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL1_IRQ, irqflags,
346 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_VIRT_IRQ, irqflags,
347 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL2_IRQ, irqflags);
348}
349
350static void fdt_add_cpu_nodes(const VirtMachineState *vms)
351{
352 int cpu;
353 int addr_cells = 1;
354 const MachineState *ms = MACHINE(vms);
355 const VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
356 int smp_cpus = ms->smp.cpus;
357
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370
371 for (cpu = 0; cpu < smp_cpus; cpu++) {
372 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
373
374 if (armcpu->mp_affinity & ARM_AFF3_MASK) {
375 addr_cells = 2;
376 break;
377 }
378 }
379
380 qemu_fdt_add_subnode(ms->fdt, "/cpus");
381 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", addr_cells);
382 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0);
383
384 for (cpu = smp_cpus - 1; cpu >= 0; cpu--) {
385 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
386 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
387 CPUState *cs = CPU(armcpu);
388
389 qemu_fdt_add_subnode(ms->fdt, nodename);
390 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu");
391 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
392 armcpu->dtb_compatible);
393
394 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED && smp_cpus > 1) {
395 qemu_fdt_setprop_string(ms->fdt, nodename,
396 "enable-method", "psci");
397 }
398
399 if (addr_cells == 2) {
400 qemu_fdt_setprop_u64(ms->fdt, nodename, "reg",
401 armcpu->mp_affinity);
402 } else {
403 qemu_fdt_setprop_cell(ms->fdt, nodename, "reg",
404 armcpu->mp_affinity);
405 }
406
407 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) {
408 qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id",
409 ms->possible_cpus->cpus[cs->cpu_index].props.node_id);
410 }
411
412 if (!vmc->no_cpu_topology) {
413 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle",
414 qemu_fdt_alloc_phandle(ms->fdt));
415 }
416
417 g_free(nodename);
418 }
419
420 if (!vmc->no_cpu_topology) {
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437
438 qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map");
439
440 for (cpu = smp_cpus - 1; cpu >= 0; cpu--) {
441 char *cpu_path = g_strdup_printf("/cpus/cpu@%d", cpu);
442 char *map_path;
443
444 if (ms->smp.threads > 1) {
445 map_path = g_strdup_printf(
446 "/cpus/cpu-map/socket%d/cluster0/core%d/thread%d",
447 cpu / (ms->smp.cores * ms->smp.threads),
448 (cpu / ms->smp.threads) % ms->smp.cores,
449 cpu % ms->smp.threads);
450 } else {
451 map_path = g_strdup_printf(
452 "/cpus/cpu-map/socket%d/cluster0/core%d",
453 cpu / ms->smp.cores,
454 cpu % ms->smp.cores);
455 }
456 qemu_fdt_add_path(ms->fdt, map_path);
457 qemu_fdt_setprop_phandle(ms->fdt, map_path, "cpu", cpu_path);
458
459 g_free(map_path);
460 g_free(cpu_path);
461 }
462 }
463}
464
465static void fdt_add_its_gic_node(VirtMachineState *vms)
466{
467 char *nodename;
468 MachineState *ms = MACHINE(vms);
469
470 vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt);
471 nodename = g_strdup_printf("/intc/its@%" PRIx64,
472 vms->memmap[VIRT_GIC_ITS].base);
473 qemu_fdt_add_subnode(ms->fdt, nodename);
474 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
475 "arm,gic-v3-its");
476 qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0);
477 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
478 2, vms->memmap[VIRT_GIC_ITS].base,
479 2, vms->memmap[VIRT_GIC_ITS].size);
480 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle);
481 g_free(nodename);
482}
483
484static void fdt_add_v2m_gic_node(VirtMachineState *vms)
485{
486 MachineState *ms = MACHINE(vms);
487 char *nodename;
488
489 nodename = g_strdup_printf("/intc/v2m@%" PRIx64,
490 vms->memmap[VIRT_GIC_V2M].base);
491 vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt);
492 qemu_fdt_add_subnode(ms->fdt, nodename);
493 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
494 "arm,gic-v2m-frame");
495 qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0);
496 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
497 2, vms->memmap[VIRT_GIC_V2M].base,
498 2, vms->memmap[VIRT_GIC_V2M].size);
499 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle);
500 g_free(nodename);
501}
502
503static void fdt_add_gic_node(VirtMachineState *vms)
504{
505 MachineState *ms = MACHINE(vms);
506 char *nodename;
507
508 vms->gic_phandle = qemu_fdt_alloc_phandle(ms->fdt);
509 qemu_fdt_setprop_cell(ms->fdt, "/", "interrupt-parent", vms->gic_phandle);
510
511 nodename = g_strdup_printf("/intc@%" PRIx64,
512 vms->memmap[VIRT_GIC_DIST].base);
513 qemu_fdt_add_subnode(ms->fdt, nodename);
514 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 3);
515 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0);
516 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 0x2);
517 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 0x2);
518 qemu_fdt_setprop(ms->fdt, nodename, "ranges", NULL, 0);
519 if (vms->gic_version == VIRT_GIC_VERSION_3) {
520 int nb_redist_regions = virt_gicv3_redist_region_count(vms);
521
522 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
523 "arm,gic-v3");
524
525 qemu_fdt_setprop_cell(ms->fdt, nodename,
526 "#redistributor-regions", nb_redist_regions);
527
528 if (nb_redist_regions == 1) {
529 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
530 2, vms->memmap[VIRT_GIC_DIST].base,
531 2, vms->memmap[VIRT_GIC_DIST].size,
532 2, vms->memmap[VIRT_GIC_REDIST].base,
533 2, vms->memmap[VIRT_GIC_REDIST].size);
534 } else {
535 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
536 2, vms->memmap[VIRT_GIC_DIST].base,
537 2, vms->memmap[VIRT_GIC_DIST].size,
538 2, vms->memmap[VIRT_GIC_REDIST].base,
539 2, vms->memmap[VIRT_GIC_REDIST].size,
540 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].base,
541 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].size);
542 }
543
544 if (vms->virt) {
545 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
546 GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ,
547 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
548 }
549 } else {
550
551 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
552 "arm,cortex-a15-gic");
553 if (!vms->virt) {
554 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
555 2, vms->memmap[VIRT_GIC_DIST].base,
556 2, vms->memmap[VIRT_GIC_DIST].size,
557 2, vms->memmap[VIRT_GIC_CPU].base,
558 2, vms->memmap[VIRT_GIC_CPU].size);
559 } else {
560 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
561 2, vms->memmap[VIRT_GIC_DIST].base,
562 2, vms->memmap[VIRT_GIC_DIST].size,
563 2, vms->memmap[VIRT_GIC_CPU].base,
564 2, vms->memmap[VIRT_GIC_CPU].size,
565 2, vms->memmap[VIRT_GIC_HYP].base,
566 2, vms->memmap[VIRT_GIC_HYP].size,
567 2, vms->memmap[VIRT_GIC_VCPU].base,
568 2, vms->memmap[VIRT_GIC_VCPU].size);
569 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
570 GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ,
571 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
572 }
573 }
574
575 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->gic_phandle);
576 g_free(nodename);
577}
578
579static void fdt_add_pmu_nodes(const VirtMachineState *vms)
580{
581 ARMCPU *armcpu = ARM_CPU(first_cpu);
582 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
583 MachineState *ms = MACHINE(vms);
584
585 if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) {
586 assert(!object_property_get_bool(OBJECT(armcpu), "pmu", NULL));
587 return;
588 }
589
590 if (vms->gic_version == VIRT_GIC_VERSION_2) {
591 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
592 GIC_FDT_IRQ_PPI_CPU_WIDTH,
593 (1 << MACHINE(vms)->smp.cpus) - 1);
594 }
595
596 qemu_fdt_add_subnode(ms->fdt, "/pmu");
597 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) {
598 const char compat[] = "arm,armv8-pmuv3";
599 qemu_fdt_setprop(ms->fdt, "/pmu", "compatible",
600 compat, sizeof(compat));
601 qemu_fdt_setprop_cells(ms->fdt, "/pmu", "interrupts",
602 GIC_FDT_IRQ_TYPE_PPI, VIRTUAL_PMU_IRQ, irqflags);
603 }
604}
605
606static inline DeviceState *create_acpi_ged(VirtMachineState *vms)
607{
608 DeviceState *dev;
609 MachineState *ms = MACHINE(vms);
610 int irq = vms->irqmap[VIRT_ACPI_GED];
611 uint32_t event = ACPI_GED_PWR_DOWN_EVT;
612
613 if (ms->ram_slots) {
614 event |= ACPI_GED_MEM_HOTPLUG_EVT;
615 }
616
617 if (ms->nvdimms_state->is_enabled) {
618 event |= ACPI_GED_NVDIMM_HOTPLUG_EVT;
619 }
620
621 dev = qdev_new(TYPE_ACPI_GED);
622 qdev_prop_set_uint32(dev, "ged-event", event);
623
624 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_ACPI_GED].base);
625 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, vms->memmap[VIRT_PCDIMM_ACPI].base);
626 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(vms->gic, irq));
627
628 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
629
630 return dev;
631}
632
633static void create_its(VirtMachineState *vms)
634{
635 const char *itsclass = its_class_name();
636 DeviceState *dev;
637
638 if (!strcmp(itsclass, "arm-gicv3-its")) {
639 if (!vms->tcg_its) {
640 itsclass = NULL;
641 }
642 }
643
644 if (!itsclass) {
645
646 return;
647 }
648
649 dev = qdev_new(itsclass);
650
651 object_property_set_link(OBJECT(dev), "parent-gicv3", OBJECT(vms->gic),
652 &error_abort);
653 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
654 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base);
655
656 fdt_add_its_gic_node(vms);
657 vms->msi_controller = VIRT_MSI_CTRL_ITS;
658}
659
660static void create_v2m(VirtMachineState *vms)
661{
662 int i;
663 int irq = vms->irqmap[VIRT_GIC_V2M];
664 DeviceState *dev;
665
666 dev = qdev_new("arm-gicv2m");
667 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base);
668 qdev_prop_set_uint32(dev, "base-spi", irq);
669 qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS);
670 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
671
672 for (i = 0; i < NUM_GICV2M_SPIS; i++) {
673 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
674 qdev_get_gpio_in(vms->gic, irq + i));
675 }
676
677 fdt_add_v2m_gic_node(vms);
678 vms->msi_controller = VIRT_MSI_CTRL_GICV2M;
679}
680
681static void create_gic(VirtMachineState *vms, MemoryRegion *mem)
682{
683 MachineState *ms = MACHINE(vms);
684
685 SysBusDevice *gicbusdev;
686 const char *gictype;
687 int type = vms->gic_version, i;
688 unsigned int smp_cpus = ms->smp.cpus;
689 uint32_t nb_redist_regions = 0;
690
691 gictype = (type == 3) ? gicv3_class_name() : gic_class_name();
692
693 vms->gic = qdev_new(gictype);
694 qdev_prop_set_uint32(vms->gic, "revision", type);
695 qdev_prop_set_uint32(vms->gic, "num-cpu", smp_cpus);
696
697
698
699 qdev_prop_set_uint32(vms->gic, "num-irq", NUM_IRQS + 32);
700 if (!kvm_irqchip_in_kernel()) {
701 qdev_prop_set_bit(vms->gic, "has-security-extensions", vms->secure);
702 }
703
704 if (type == 3) {
705 uint32_t redist0_capacity =
706 vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE;
707 uint32_t redist0_count = MIN(smp_cpus, redist0_capacity);
708
709 nb_redist_regions = virt_gicv3_redist_region_count(vms);
710
711 qdev_prop_set_uint32(vms->gic, "len-redist-region-count",
712 nb_redist_regions);
713 qdev_prop_set_uint32(vms->gic, "redist-region-count[0]", redist0_count);
714
715 if (!kvm_irqchip_in_kernel()) {
716 if (vms->tcg_its) {
717 object_property_set_link(OBJECT(vms->gic), "sysmem",
718 OBJECT(mem), &error_fatal);
719 qdev_prop_set_bit(vms->gic, "has-lpi", true);
720 }
721 }
722
723 if (nb_redist_regions == 2) {
724 uint32_t redist1_capacity =
725 vms->memmap[VIRT_HIGH_GIC_REDIST2].size / GICV3_REDIST_SIZE;
726
727 qdev_prop_set_uint32(vms->gic, "redist-region-count[1]",
728 MIN(smp_cpus - redist0_count, redist1_capacity));
729 }
730 } else {
731 if (!kvm_irqchip_in_kernel()) {
732 qdev_prop_set_bit(vms->gic, "has-virtualization-extensions",
733 vms->virt);
734 }
735 }
736 gicbusdev = SYS_BUS_DEVICE(vms->gic);
737 sysbus_realize_and_unref(gicbusdev, &error_fatal);
738 sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base);
739 if (type == 3) {
740 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base);
741 if (nb_redist_regions == 2) {
742 sysbus_mmio_map(gicbusdev, 2,
743 vms->memmap[VIRT_HIGH_GIC_REDIST2].base);
744 }
745 } else {
746 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base);
747 if (vms->virt) {
748 sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_GIC_HYP].base);
749 sysbus_mmio_map(gicbusdev, 3, vms->memmap[VIRT_GIC_VCPU].base);
750 }
751 }
752
753
754
755
756
757 for (i = 0; i < smp_cpus; i++) {
758 DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
759 int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS;
760 int irq;
761
762
763
764 const int timer_irq[] = {
765 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ,
766 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,
767 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ,
768 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ,
769 };
770
771 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
772 qdev_connect_gpio_out(cpudev, irq,
773 qdev_get_gpio_in(vms->gic,
774 ppibase + timer_irq[irq]));
775 }
776
777 if (type == 3) {
778 qemu_irq irq = qdev_get_gpio_in(vms->gic,
779 ppibase + ARCH_GIC_MAINT_IRQ);
780 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt",
781 0, irq);
782 } else if (vms->virt) {
783 qemu_irq irq = qdev_get_gpio_in(vms->gic,
784 ppibase + ARCH_GIC_MAINT_IRQ);
785 sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq);
786 }
787
788 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0,
789 qdev_get_gpio_in(vms->gic, ppibase
790 + VIRTUAL_PMU_IRQ));
791
792 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
793 sysbus_connect_irq(gicbusdev, i + smp_cpus,
794 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
795 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus,
796 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
797 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus,
798 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
799 }
800
801 fdt_add_gic_node(vms);
802
803 if (type == 3 && vms->its) {
804 create_its(vms);
805 } else if (type == 2) {
806 create_v2m(vms);
807 }
808}
809
810static void create_uart(const VirtMachineState *vms, int uart,
811 MemoryRegion *mem, Chardev *chr)
812{
813 char *nodename;
814 hwaddr base = vms->memmap[uart].base;
815 hwaddr size = vms->memmap[uart].size;
816 int irq = vms->irqmap[uart];
817 const char compat[] = "arm,pl011\0arm,primecell";
818 const char clocknames[] = "uartclk\0apb_pclk";
819 DeviceState *dev = qdev_new(TYPE_PL011);
820 SysBusDevice *s = SYS_BUS_DEVICE(dev);
821 MachineState *ms = MACHINE(vms);
822
823 qdev_prop_set_chr(dev, "chardev", chr);
824 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
825 memory_region_add_subregion(mem, base,
826 sysbus_mmio_get_region(s, 0));
827 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq));
828
829 nodename = g_strdup_printf("/pl011@%" PRIx64, base);
830 qemu_fdt_add_subnode(ms->fdt, nodename);
831
832 qemu_fdt_setprop(ms->fdt, nodename, "compatible",
833 compat, sizeof(compat));
834 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
835 2, base, 2, size);
836 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
837 GIC_FDT_IRQ_TYPE_SPI, irq,
838 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
839 qemu_fdt_setprop_cells(ms->fdt, nodename, "clocks",
840 vms->clock_phandle, vms->clock_phandle);
841 qemu_fdt_setprop(ms->fdt, nodename, "clock-names",
842 clocknames, sizeof(clocknames));
843
844 if (uart == VIRT_UART) {
845 qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", nodename);
846 } else {
847
848 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled");
849 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay");
850
851 qemu_fdt_setprop_string(ms->fdt, "/secure-chosen", "stdout-path",
852 nodename);
853 }
854
855 g_free(nodename);
856}
857
858static void create_rtc(const VirtMachineState *vms)
859{
860 char *nodename;
861 hwaddr base = vms->memmap[VIRT_RTC].base;
862 hwaddr size = vms->memmap[VIRT_RTC].size;
863 int irq = vms->irqmap[VIRT_RTC];
864 const char compat[] = "arm,pl031\0arm,primecell";
865 MachineState *ms = MACHINE(vms);
866
867 sysbus_create_simple("pl031", base, qdev_get_gpio_in(vms->gic, irq));
868
869 nodename = g_strdup_printf("/pl031@%" PRIx64, base);
870 qemu_fdt_add_subnode(ms->fdt, nodename);
871 qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat));
872 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
873 2, base, 2, size);
874 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
875 GIC_FDT_IRQ_TYPE_SPI, irq,
876 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
877 qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle);
878 qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk");
879 g_free(nodename);
880}
881
882static DeviceState *gpio_key_dev;
883static void virt_powerdown_req(Notifier *n, void *opaque)
884{
885 VirtMachineState *s = container_of(n, VirtMachineState, powerdown_notifier);
886
887 if (s->acpi_dev) {
888 acpi_send_event(s->acpi_dev, ACPI_POWER_DOWN_STATUS);
889 } else {
890
891 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1);
892 }
893}
894
895static void create_gpio_keys(char *fdt, DeviceState *pl061_dev,
896 uint32_t phandle)
897{
898 gpio_key_dev = sysbus_create_simple("gpio-key", -1,
899 qdev_get_gpio_in(pl061_dev, 3));
900
901 qemu_fdt_add_subnode(fdt, "/gpio-keys");
902 qemu_fdt_setprop_string(fdt, "/gpio-keys", "compatible", "gpio-keys");
903 qemu_fdt_setprop_cell(fdt, "/gpio-keys", "#size-cells", 0);
904 qemu_fdt_setprop_cell(fdt, "/gpio-keys", "#address-cells", 1);
905
906 qemu_fdt_add_subnode(fdt, "/gpio-keys/poweroff");
907 qemu_fdt_setprop_string(fdt, "/gpio-keys/poweroff",
908 "label", "GPIO Key Poweroff");
909 qemu_fdt_setprop_cell(fdt, "/gpio-keys/poweroff", "linux,code",
910 KEY_POWER);
911 qemu_fdt_setprop_cells(fdt, "/gpio-keys/poweroff",
912 "gpios", phandle, 3, 0);
913}
914
915#define SECURE_GPIO_POWEROFF 0
916#define SECURE_GPIO_RESET 1
917
918static void create_secure_gpio_pwr(char *fdt, DeviceState *pl061_dev,
919 uint32_t phandle)
920{
921 DeviceState *gpio_pwr_dev;
922
923
924 gpio_pwr_dev = sysbus_create_simple("gpio-pwr", -1, NULL);
925
926
927 qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_RESET,
928 qdev_get_gpio_in_named(gpio_pwr_dev, "reset", 0));
929 qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_POWEROFF,
930 qdev_get_gpio_in_named(gpio_pwr_dev, "shutdown", 0));
931
932 qemu_fdt_add_subnode(fdt, "/gpio-poweroff");
933 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "compatible",
934 "gpio-poweroff");
935 qemu_fdt_setprop_cells(fdt, "/gpio-poweroff",
936 "gpios", phandle, SECURE_GPIO_POWEROFF, 0);
937 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "status", "disabled");
938 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "secure-status",
939 "okay");
940
941 qemu_fdt_add_subnode(fdt, "/gpio-restart");
942 qemu_fdt_setprop_string(fdt, "/gpio-restart", "compatible",
943 "gpio-restart");
944 qemu_fdt_setprop_cells(fdt, "/gpio-restart",
945 "gpios", phandle, SECURE_GPIO_RESET, 0);
946 qemu_fdt_setprop_string(fdt, "/gpio-restart", "status", "disabled");
947 qemu_fdt_setprop_string(fdt, "/gpio-restart", "secure-status",
948 "okay");
949}
950
951static void create_gpio_devices(const VirtMachineState *vms, int gpio,
952 MemoryRegion *mem)
953{
954 char *nodename;
955 DeviceState *pl061_dev;
956 hwaddr base = vms->memmap[gpio].base;
957 hwaddr size = vms->memmap[gpio].size;
958 int irq = vms->irqmap[gpio];
959 const char compat[] = "arm,pl061\0arm,primecell";
960 SysBusDevice *s;
961 MachineState *ms = MACHINE(vms);
962
963 pl061_dev = qdev_new("pl061");
964
965 qdev_prop_set_uint32(pl061_dev, "pullups", 0);
966 qdev_prop_set_uint32(pl061_dev, "pulldowns", 0xff);
967 s = SYS_BUS_DEVICE(pl061_dev);
968 sysbus_realize_and_unref(s, &error_fatal);
969 memory_region_add_subregion(mem, base, sysbus_mmio_get_region(s, 0));
970 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq));
971
972 uint32_t phandle = qemu_fdt_alloc_phandle(ms->fdt);
973 nodename = g_strdup_printf("/pl061@%" PRIx64, base);
974 qemu_fdt_add_subnode(ms->fdt, nodename);
975 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
976 2, base, 2, size);
977 qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat));
978 qemu_fdt_setprop_cell(ms->fdt, nodename, "#gpio-cells", 2);
979 qemu_fdt_setprop(ms->fdt, nodename, "gpio-controller", NULL, 0);
980 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
981 GIC_FDT_IRQ_TYPE_SPI, irq,
982 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
983 qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle);
984 qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk");
985 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", phandle);
986
987 if (gpio != VIRT_GPIO) {
988
989 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled");
990 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay");
991 }
992 g_free(nodename);
993
994
995 if (gpio == VIRT_GPIO) {
996 create_gpio_keys(ms->fdt, pl061_dev, phandle);
997 } else {
998 create_secure_gpio_pwr(ms->fdt, pl061_dev, phandle);
999 }
1000}
1001
1002static void create_virtio_devices(const VirtMachineState *vms)
1003{
1004 int i;
1005 hwaddr size = vms->memmap[VIRT_MMIO].size;
1006 MachineState *ms = MACHINE(vms);
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) {
1036 int irq = vms->irqmap[VIRT_MMIO] + i;
1037 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size;
1038
1039 sysbus_create_simple("virtio-mmio", base,
1040 qdev_get_gpio_in(vms->gic, irq));
1041 }
1042
1043
1044
1045
1046
1047
1048
1049
1050 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) {
1051 char *nodename;
1052 int irq = vms->irqmap[VIRT_MMIO] + i;
1053 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size;
1054
1055 nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base);
1056 qemu_fdt_add_subnode(ms->fdt, nodename);
1057 qemu_fdt_setprop_string(ms->fdt, nodename,
1058 "compatible", "virtio,mmio");
1059 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1060 2, base, 2, size);
1061 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
1062 GIC_FDT_IRQ_TYPE_SPI, irq,
1063 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI);
1064 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
1065 g_free(nodename);
1066 }
1067}
1068
1069#define VIRT_FLASH_SECTOR_SIZE (256 * KiB)
1070
1071static PFlashCFI01 *virt_flash_create1(VirtMachineState *vms,
1072 const char *name,
1073 const char *alias_prop_name)
1074{
1075
1076
1077
1078
1079 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01);
1080
1081 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE);
1082 qdev_prop_set_uint8(dev, "width", 4);
1083 qdev_prop_set_uint8(dev, "device-width", 2);
1084 qdev_prop_set_bit(dev, "big-endian", false);
1085 qdev_prop_set_uint16(dev, "id0", 0x89);
1086 qdev_prop_set_uint16(dev, "id1", 0x18);
1087 qdev_prop_set_uint16(dev, "id2", 0x00);
1088 qdev_prop_set_uint16(dev, "id3", 0x00);
1089 qdev_prop_set_string(dev, "name", name);
1090 object_property_add_child(OBJECT(vms), name, OBJECT(dev));
1091 object_property_add_alias(OBJECT(vms), alias_prop_name,
1092 OBJECT(dev), "drive");
1093 return PFLASH_CFI01(dev);
1094}
1095
1096static void virt_flash_create(VirtMachineState *vms)
1097{
1098 vms->flash[0] = virt_flash_create1(vms, "virt.flash0", "pflash0");
1099 vms->flash[1] = virt_flash_create1(vms, "virt.flash1", "pflash1");
1100}
1101
1102static void virt_flash_map1(PFlashCFI01 *flash,
1103 hwaddr base, hwaddr size,
1104 MemoryRegion *sysmem)
1105{
1106 DeviceState *dev = DEVICE(flash);
1107
1108 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE));
1109 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX);
1110 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE);
1111 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1112
1113 memory_region_add_subregion(sysmem, base,
1114 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev),
1115 0));
1116}
1117
1118static void virt_flash_map(VirtMachineState *vms,
1119 MemoryRegion *sysmem,
1120 MemoryRegion *secure_sysmem)
1121{
1122
1123
1124
1125
1126
1127
1128
1129
1130 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2;
1131 hwaddr flashbase = vms->memmap[VIRT_FLASH].base;
1132
1133 virt_flash_map1(vms->flash[0], flashbase, flashsize,
1134 secure_sysmem);
1135 virt_flash_map1(vms->flash[1], flashbase + flashsize, flashsize,
1136 sysmem);
1137}
1138
1139static void virt_flash_fdt(VirtMachineState *vms,
1140 MemoryRegion *sysmem,
1141 MemoryRegion *secure_sysmem)
1142{
1143 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2;
1144 hwaddr flashbase = vms->memmap[VIRT_FLASH].base;
1145 MachineState *ms = MACHINE(vms);
1146 char *nodename;
1147
1148 if (sysmem == secure_sysmem) {
1149
1150 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase);
1151 qemu_fdt_add_subnode(ms->fdt, nodename);
1152 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash");
1153 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1154 2, flashbase, 2, flashsize,
1155 2, flashbase + flashsize, 2, flashsize);
1156 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4);
1157 g_free(nodename);
1158 } else {
1159
1160
1161
1162
1163 nodename = g_strdup_printf("/secflash@%" PRIx64, flashbase);
1164 qemu_fdt_add_subnode(ms->fdt, nodename);
1165 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash");
1166 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1167 2, flashbase, 2, flashsize);
1168 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4);
1169 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled");
1170 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay");
1171 g_free(nodename);
1172
1173 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase);
1174 qemu_fdt_add_subnode(ms->fdt, nodename);
1175 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash");
1176 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1177 2, flashbase + flashsize, 2, flashsize);
1178 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4);
1179 g_free(nodename);
1180 }
1181}
1182
1183static bool virt_firmware_init(VirtMachineState *vms,
1184 MemoryRegion *sysmem,
1185 MemoryRegion *secure_sysmem)
1186{
1187 int i;
1188 const char *bios_name;
1189 BlockBackend *pflash_blk0;
1190
1191
1192 for (i = 0; i < ARRAY_SIZE(vms->flash); i++) {
1193 pflash_cfi01_legacy_drive(vms->flash[i],
1194 drive_get(IF_PFLASH, 0, i));
1195 }
1196
1197 virt_flash_map(vms, sysmem, secure_sysmem);
1198
1199 pflash_blk0 = pflash_cfi01_get_blk(vms->flash[0]);
1200
1201 bios_name = MACHINE(vms)->firmware;
1202 if (bios_name) {
1203 char *fname;
1204 MemoryRegion *mr;
1205 int image_size;
1206
1207 if (pflash_blk0) {
1208 error_report("The contents of the first flash device may be "
1209 "specified with -bios or with -drive if=pflash... "
1210 "but you cannot use both options at once");
1211 exit(1);
1212 }
1213
1214
1215
1216 fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
1217 if (!fname) {
1218 error_report("Could not find ROM image '%s'", bios_name);
1219 exit(1);
1220 }
1221 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(vms->flash[0]), 0);
1222 image_size = load_image_mr(fname, mr);
1223 g_free(fname);
1224 if (image_size < 0) {
1225 error_report("Could not load ROM image '%s'", bios_name);
1226 exit(1);
1227 }
1228 }
1229
1230 return pflash_blk0 || bios_name;
1231}
1232
1233static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as)
1234{
1235 MachineState *ms = MACHINE(vms);
1236 hwaddr base = vms->memmap[VIRT_FW_CFG].base;
1237 hwaddr size = vms->memmap[VIRT_FW_CFG].size;
1238 FWCfgState *fw_cfg;
1239 char *nodename;
1240
1241 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as);
1242 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus);
1243
1244 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
1245 qemu_fdt_add_subnode(ms->fdt, nodename);
1246 qemu_fdt_setprop_string(ms->fdt, nodename,
1247 "compatible", "qemu,fw-cfg-mmio");
1248 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1249 2, base, 2, size);
1250 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
1251 g_free(nodename);
1252 return fw_cfg;
1253}
1254
1255static void create_pcie_irq_map(const MachineState *ms,
1256 uint32_t gic_phandle,
1257 int first_irq, const char *nodename)
1258{
1259 int devfn, pin;
1260 uint32_t full_irq_map[4 * 4 * 10] = { 0 };
1261 uint32_t *irq_map = full_irq_map;
1262
1263 for (devfn = 0; devfn <= 0x18; devfn += 0x8) {
1264 for (pin = 0; pin < 4; pin++) {
1265 int irq_type = GIC_FDT_IRQ_TYPE_SPI;
1266 int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS);
1267 int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
1268 int i;
1269
1270 uint32_t map[] = {
1271 devfn << 8, 0, 0,
1272 pin + 1,
1273 gic_phandle, 0, 0, irq_type, irq_nr, irq_level };
1274
1275
1276 for (i = 0; i < 10; i++) {
1277 irq_map[i] = cpu_to_be32(map[i]);
1278 }
1279 irq_map += 10;
1280 }
1281 }
1282
1283 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-map",
1284 full_irq_map, sizeof(full_irq_map));
1285
1286 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupt-map-mask",
1287 cpu_to_be16(PCI_DEVFN(3, 0)),
1288 0, 0,
1289 0x7 );
1290}
1291
1292static void create_smmu(const VirtMachineState *vms,
1293 PCIBus *bus)
1294{
1295 char *node;
1296 const char compat[] = "arm,smmu-v3";
1297 int irq = vms->irqmap[VIRT_SMMU];
1298 int i;
1299 hwaddr base = vms->memmap[VIRT_SMMU].base;
1300 hwaddr size = vms->memmap[VIRT_SMMU].size;
1301 const char irq_names[] = "eventq\0priq\0cmdq-sync\0gerror";
1302 DeviceState *dev;
1303 MachineState *ms = MACHINE(vms);
1304
1305 if (vms->iommu != VIRT_IOMMU_SMMUV3 || !vms->iommu_phandle) {
1306 return;
1307 }
1308
1309 dev = qdev_new("arm-smmuv3");
1310
1311 object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus),
1312 &error_abort);
1313 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1314 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
1315 for (i = 0; i < NUM_SMMU_IRQS; i++) {
1316 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
1317 qdev_get_gpio_in(vms->gic, irq + i));
1318 }
1319
1320 node = g_strdup_printf("/smmuv3@%" PRIx64, base);
1321 qemu_fdt_add_subnode(ms->fdt, node);
1322 qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat));
1323 qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg", 2, base, 2, size);
1324
1325 qemu_fdt_setprop_cells(ms->fdt, node, "interrupts",
1326 GIC_FDT_IRQ_TYPE_SPI, irq , GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
1327 GIC_FDT_IRQ_TYPE_SPI, irq + 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
1328 GIC_FDT_IRQ_TYPE_SPI, irq + 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
1329 GIC_FDT_IRQ_TYPE_SPI, irq + 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI);
1330
1331 qemu_fdt_setprop(ms->fdt, node, "interrupt-names", irq_names,
1332 sizeof(irq_names));
1333
1334 qemu_fdt_setprop_cell(ms->fdt, node, "clocks", vms->clock_phandle);
1335 qemu_fdt_setprop_string(ms->fdt, node, "clock-names", "apb_pclk");
1336 qemu_fdt_setprop(ms->fdt, node, "dma-coherent", NULL, 0);
1337
1338 qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1);
1339
1340 qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle);
1341 g_free(node);
1342}
1343
1344static void create_virtio_iommu_dt_bindings(VirtMachineState *vms)
1345{
1346 const char compat[] = "virtio,pci-iommu";
1347 uint16_t bdf = vms->virtio_iommu_bdf;
1348 MachineState *ms = MACHINE(vms);
1349 char *node;
1350
1351 vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt);
1352
1353 node = g_strdup_printf("%s/virtio_iommu@%d", vms->pciehb_nodename, bdf);
1354 qemu_fdt_add_subnode(ms->fdt, node);
1355 qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat));
1356 qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg",
1357 1, bdf << 8, 1, 0, 1, 0,
1358 1, 0, 1, 0);
1359
1360 qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1);
1361 qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle);
1362 g_free(node);
1363
1364 qemu_fdt_setprop_cells(ms->fdt, vms->pciehb_nodename, "iommu-map",
1365 0x0, vms->iommu_phandle, 0x0, bdf,
1366 bdf + 1, vms->iommu_phandle, bdf + 1, 0xffff - bdf);
1367}
1368
1369static void create_pcie(VirtMachineState *vms)
1370{
1371 hwaddr base_mmio = vms->memmap[VIRT_PCIE_MMIO].base;
1372 hwaddr size_mmio = vms->memmap[VIRT_PCIE_MMIO].size;
1373 hwaddr base_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].base;
1374 hwaddr size_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].size;
1375 hwaddr base_pio = vms->memmap[VIRT_PCIE_PIO].base;
1376 hwaddr size_pio = vms->memmap[VIRT_PCIE_PIO].size;
1377 hwaddr base_ecam, size_ecam;
1378 hwaddr base = base_mmio;
1379 int nr_pcie_buses;
1380 int irq = vms->irqmap[VIRT_PCIE];
1381 MemoryRegion *mmio_alias;
1382 MemoryRegion *mmio_reg;
1383 MemoryRegion *ecam_alias;
1384 MemoryRegion *ecam_reg;
1385 DeviceState *dev;
1386 char *nodename;
1387 int i, ecam_id;
1388 PCIHostState *pci;
1389 MachineState *ms = MACHINE(vms);
1390
1391 dev = qdev_new(TYPE_GPEX_HOST);
1392 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1393
1394 ecam_id = VIRT_ECAM_ID(vms->highmem_ecam);
1395 base_ecam = vms->memmap[ecam_id].base;
1396 size_ecam = vms->memmap[ecam_id].size;
1397 nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN;
1398
1399 ecam_alias = g_new0(MemoryRegion, 1);
1400 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
1401 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
1402 ecam_reg, 0, size_ecam);
1403 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias);
1404
1405
1406
1407
1408
1409
1410 mmio_alias = g_new0(MemoryRegion, 1);
1411 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
1412 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio",
1413 mmio_reg, base_mmio, size_mmio);
1414 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias);
1415
1416 if (vms->highmem) {
1417
1418 MemoryRegion *high_mmio_alias = g_new0(MemoryRegion, 1);
1419
1420 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high",
1421 mmio_reg, base_mmio_high, size_mmio_high);
1422 memory_region_add_subregion(get_system_memory(), base_mmio_high,
1423 high_mmio_alias);
1424 }
1425
1426
1427 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio);
1428
1429 for (i = 0; i < GPEX_NUM_IRQS; i++) {
1430 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
1431 qdev_get_gpio_in(vms->gic, irq + i));
1432 gpex_set_irq_num(GPEX_HOST(dev), i, irq + i);
1433 }
1434
1435 pci = PCI_HOST_BRIDGE(dev);
1436 pci->bypass_iommu = vms->default_bus_bypass_iommu;
1437 vms->bus = pci->bus;
1438 if (vms->bus) {
1439 for (i = 0; i < nb_nics; i++) {
1440 NICInfo *nd = &nd_table[i];
1441
1442 if (!nd->model) {
1443 nd->model = g_strdup("virtio");
1444 }
1445
1446 pci_nic_init_nofail(nd, pci->bus, nd->model, NULL);
1447 }
1448 }
1449
1450 nodename = vms->pciehb_nodename = g_strdup_printf("/pcie@%" PRIx64, base);
1451 qemu_fdt_add_subnode(ms->fdt, nodename);
1452 qemu_fdt_setprop_string(ms->fdt, nodename,
1453 "compatible", "pci-host-ecam-generic");
1454 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "pci");
1455 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 3);
1456 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 2);
1457 qemu_fdt_setprop_cell(ms->fdt, nodename, "linux,pci-domain", 0);
1458 qemu_fdt_setprop_cells(ms->fdt, nodename, "bus-range", 0,
1459 nr_pcie_buses - 1);
1460 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
1461
1462 if (vms->msi_phandle) {
1463 qemu_fdt_setprop_cells(ms->fdt, nodename, "msi-parent",
1464 vms->msi_phandle);
1465 }
1466
1467 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1468 2, base_ecam, 2, size_ecam);
1469
1470 if (vms->highmem) {
1471 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges",
1472 1, FDT_PCI_RANGE_IOPORT, 2, 0,
1473 2, base_pio, 2, size_pio,
1474 1, FDT_PCI_RANGE_MMIO, 2, base_mmio,
1475 2, base_mmio, 2, size_mmio,
1476 1, FDT_PCI_RANGE_MMIO_64BIT,
1477 2, base_mmio_high,
1478 2, base_mmio_high, 2, size_mmio_high);
1479 } else {
1480 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges",
1481 1, FDT_PCI_RANGE_IOPORT, 2, 0,
1482 2, base_pio, 2, size_pio,
1483 1, FDT_PCI_RANGE_MMIO, 2, base_mmio,
1484 2, base_mmio, 2, size_mmio);
1485 }
1486
1487 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 1);
1488 create_pcie_irq_map(ms, vms->gic_phandle, irq, nodename);
1489
1490 if (vms->iommu) {
1491 vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt);
1492
1493 switch (vms->iommu) {
1494 case VIRT_IOMMU_SMMUV3:
1495 create_smmu(vms, vms->bus);
1496 qemu_fdt_setprop_cells(ms->fdt, nodename, "iommu-map",
1497 0x0, vms->iommu_phandle, 0x0, 0x10000);
1498 break;
1499 default:
1500 g_assert_not_reached();
1501 }
1502 }
1503}
1504
1505static void create_platform_bus(VirtMachineState *vms)
1506{
1507 DeviceState *dev;
1508 SysBusDevice *s;
1509 int i;
1510 MemoryRegion *sysmem = get_system_memory();
1511
1512 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE);
1513 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE);
1514 qdev_prop_set_uint32(dev, "num_irqs", PLATFORM_BUS_NUM_IRQS);
1515 qdev_prop_set_uint32(dev, "mmio_size", vms->memmap[VIRT_PLATFORM_BUS].size);
1516 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1517 vms->platform_bus_dev = dev;
1518
1519 s = SYS_BUS_DEVICE(dev);
1520 for (i = 0; i < PLATFORM_BUS_NUM_IRQS; i++) {
1521 int irq = vms->irqmap[VIRT_PLATFORM_BUS] + i;
1522 sysbus_connect_irq(s, i, qdev_get_gpio_in(vms->gic, irq));
1523 }
1524
1525 memory_region_add_subregion(sysmem,
1526 vms->memmap[VIRT_PLATFORM_BUS].base,
1527 sysbus_mmio_get_region(s, 0));
1528}
1529
1530static void create_tag_ram(MemoryRegion *tag_sysmem,
1531 hwaddr base, hwaddr size,
1532 const char *name)
1533{
1534 MemoryRegion *tagram = g_new(MemoryRegion, 1);
1535
1536 memory_region_init_ram(tagram, NULL, name, size / 32, &error_fatal);
1537 memory_region_add_subregion(tag_sysmem, base / 32, tagram);
1538}
1539
1540static void create_secure_ram(VirtMachineState *vms,
1541 MemoryRegion *secure_sysmem,
1542 MemoryRegion *secure_tag_sysmem)
1543{
1544 MemoryRegion *secram = g_new(MemoryRegion, 1);
1545 char *nodename;
1546 hwaddr base = vms->memmap[VIRT_SECURE_MEM].base;
1547 hwaddr size = vms->memmap[VIRT_SECURE_MEM].size;
1548 MachineState *ms = MACHINE(vms);
1549
1550 memory_region_init_ram(secram, NULL, "virt.secure-ram", size,
1551 &error_fatal);
1552 memory_region_add_subregion(secure_sysmem, base, secram);
1553
1554 nodename = g_strdup_printf("/secram@%" PRIx64, base);
1555 qemu_fdt_add_subnode(ms->fdt, nodename);
1556 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "memory");
1557 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 2, size);
1558 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled");
1559 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay");
1560
1561 if (secure_tag_sysmem) {
1562 create_tag_ram(secure_tag_sysmem, base, size, "mach-virt.secure-tag");
1563 }
1564
1565 g_free(nodename);
1566}
1567
1568static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size)
1569{
1570 const VirtMachineState *board = container_of(binfo, VirtMachineState,
1571 bootinfo);
1572 MachineState *ms = MACHINE(board);
1573
1574
1575 *fdt_size = board->fdt_size;
1576 return ms->fdt;
1577}
1578
1579static void virt_build_smbios(VirtMachineState *vms)
1580{
1581 MachineClass *mc = MACHINE_GET_CLASS(vms);
1582 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
1583 uint8_t *smbios_tables, *smbios_anchor;
1584 size_t smbios_tables_len, smbios_anchor_len;
1585 const char *product = "QEMU Virtual Machine";
1586
1587 if (kvm_enabled()) {
1588 product = "KVM Virtual Machine";
1589 }
1590
1591 smbios_set_defaults("QEMU", product,
1592 vmc->smbios_old_sys_ver ? "1.0" : mc->name, false,
1593 true, SMBIOS_ENTRY_POINT_30);
1594
1595 smbios_get_tables(MACHINE(vms), NULL, 0,
1596 &smbios_tables, &smbios_tables_len,
1597 &smbios_anchor, &smbios_anchor_len,
1598 &error_fatal);
1599
1600 if (smbios_anchor) {
1601 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-tables",
1602 smbios_tables, smbios_tables_len);
1603 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-anchor",
1604 smbios_anchor, smbios_anchor_len);
1605 }
1606}
1607
1608static
1609void virt_machine_done(Notifier *notifier, void *data)
1610{
1611 VirtMachineState *vms = container_of(notifier, VirtMachineState,
1612 machine_done);
1613 MachineState *ms = MACHINE(vms);
1614 ARMCPU *cpu = ARM_CPU(first_cpu);
1615 struct arm_boot_info *info = &vms->bootinfo;
1616 AddressSpace *as = arm_boot_address_space(cpu, info);
1617
1618
1619
1620
1621
1622
1623
1624
1625 if (info->dtb_filename == NULL) {
1626 platform_bus_add_all_fdt_nodes(ms->fdt, "/intc",
1627 vms->memmap[VIRT_PLATFORM_BUS].base,
1628 vms->memmap[VIRT_PLATFORM_BUS].size,
1629 vms->irqmap[VIRT_PLATFORM_BUS]);
1630 }
1631 if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms) < 0) {
1632 exit(1);
1633 }
1634
1635 fw_cfg_add_extra_pci_roots(vms->bus, vms->fw_cfg);
1636
1637 virt_acpi_setup(vms);
1638 virt_build_smbios(vms);
1639}
1640
1641static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx)
1642{
1643 uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER;
1644 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
1645
1646 if (!vmc->disallow_affinity_adjustment) {
1647
1648
1649
1650
1651
1652
1653
1654
1655 if (vms->gic_version == VIRT_GIC_VERSION_3) {
1656 clustersz = GICV3_TARGETLIST_BITS;
1657 } else {
1658 clustersz = GIC_TARGETLIST_BITS;
1659 }
1660 }
1661 return arm_cpu_mp_affinity(idx, clustersz);
1662}
1663
1664static void virt_set_memmap(VirtMachineState *vms)
1665{
1666 MachineState *ms = MACHINE(vms);
1667 hwaddr base, device_memory_base, device_memory_size;
1668 int i;
1669
1670 vms->memmap = extended_memmap;
1671
1672 for (i = 0; i < ARRAY_SIZE(base_memmap); i++) {
1673 vms->memmap[i] = base_memmap[i];
1674 }
1675
1676 if (ms->ram_slots > ACPI_MAX_RAM_SLOTS) {
1677 error_report("unsupported number of memory slots: %"PRIu64,
1678 ms->ram_slots);
1679 exit(EXIT_FAILURE);
1680 }
1681
1682
1683
1684
1685
1686
1687
1688
1689 device_memory_base =
1690 ROUND_UP(vms->memmap[VIRT_MEM].base + ms->ram_size, GiB);
1691 device_memory_size = ms->maxram_size - ms->ram_size + ms->ram_slots * GiB;
1692
1693
1694 base = device_memory_base + ROUND_UP(device_memory_size, GiB);
1695 if (base < device_memory_base) {
1696 error_report("maxmem/slots too huge");
1697 exit(EXIT_FAILURE);
1698 }
1699 if (base < vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES) {
1700 base = vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES;
1701 }
1702
1703 for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) {
1704 hwaddr size = extended_memmap[i].size;
1705
1706 base = ROUND_UP(base, size);
1707 vms->memmap[i].base = base;
1708 vms->memmap[i].size = size;
1709 base += size;
1710 }
1711 vms->highest_gpa = base - 1;
1712 if (device_memory_size > 0) {
1713 ms->device_memory = g_malloc0(sizeof(*ms->device_memory));
1714 ms->device_memory->base = device_memory_base;
1715 memory_region_init(&ms->device_memory->mr, OBJECT(vms),
1716 "device-memory", device_memory_size);
1717 }
1718}
1719
1720
1721
1722
1723
1724
1725
1726static void finalize_gic_version(VirtMachineState *vms)
1727{
1728 unsigned int max_cpus = MACHINE(vms)->smp.max_cpus;
1729
1730 if (kvm_enabled()) {
1731 int probe_bitmap;
1732
1733 if (!kvm_irqchip_in_kernel()) {
1734 switch (vms->gic_version) {
1735 case VIRT_GIC_VERSION_HOST:
1736 warn_report(
1737 "gic-version=host not relevant with kernel-irqchip=off "
1738 "as only userspace GICv2 is supported. Using v2 ...");
1739 return;
1740 case VIRT_GIC_VERSION_MAX:
1741 case VIRT_GIC_VERSION_NOSEL:
1742 vms->gic_version = VIRT_GIC_VERSION_2;
1743 return;
1744 case VIRT_GIC_VERSION_2:
1745 return;
1746 case VIRT_GIC_VERSION_3:
1747 error_report(
1748 "gic-version=3 is not supported with kernel-irqchip=off");
1749 exit(1);
1750 }
1751 }
1752
1753 probe_bitmap = kvm_arm_vgic_probe();
1754 if (!probe_bitmap) {
1755 error_report("Unable to determine GIC version supported by host");
1756 exit(1);
1757 }
1758
1759 switch (vms->gic_version) {
1760 case VIRT_GIC_VERSION_HOST:
1761 case VIRT_GIC_VERSION_MAX:
1762 if (probe_bitmap & KVM_ARM_VGIC_V3) {
1763 vms->gic_version = VIRT_GIC_VERSION_3;
1764 } else {
1765 vms->gic_version = VIRT_GIC_VERSION_2;
1766 }
1767 return;
1768 case VIRT_GIC_VERSION_NOSEL:
1769 if ((probe_bitmap & KVM_ARM_VGIC_V2) && max_cpus <= GIC_NCPU) {
1770 vms->gic_version = VIRT_GIC_VERSION_2;
1771 } else if (probe_bitmap & KVM_ARM_VGIC_V3) {
1772
1773
1774
1775
1776
1777 vms->gic_version = VIRT_GIC_VERSION_3;
1778 } else if (max_cpus > GIC_NCPU) {
1779 error_report("host only supports in-kernel GICv2 emulation "
1780 "but more than 8 vcpus are requested");
1781 exit(1);
1782 }
1783 break;
1784 case VIRT_GIC_VERSION_2:
1785 case VIRT_GIC_VERSION_3:
1786 break;
1787 }
1788
1789
1790 if (vms->gic_version == VIRT_GIC_VERSION_2 &&
1791 !(probe_bitmap & KVM_ARM_VGIC_V2)) {
1792 error_report("host does not support in-kernel GICv2 emulation");
1793 exit(1);
1794 } else if (vms->gic_version == VIRT_GIC_VERSION_3 &&
1795 !(probe_bitmap & KVM_ARM_VGIC_V3)) {
1796 error_report("host does not support in-kernel GICv3 emulation");
1797 exit(1);
1798 }
1799 return;
1800 }
1801
1802
1803 switch (vms->gic_version) {
1804 case VIRT_GIC_VERSION_NOSEL:
1805 vms->gic_version = VIRT_GIC_VERSION_2;
1806 break;
1807 case VIRT_GIC_VERSION_MAX:
1808 vms->gic_version = VIRT_GIC_VERSION_3;
1809 break;
1810 case VIRT_GIC_VERSION_HOST:
1811 error_report("gic-version=host requires KVM");
1812 exit(1);
1813 case VIRT_GIC_VERSION_2:
1814 case VIRT_GIC_VERSION_3:
1815 break;
1816 }
1817}
1818
1819
1820
1821
1822
1823static void virt_cpu_post_init(VirtMachineState *vms, MemoryRegion *sysmem)
1824{
1825 int max_cpus = MACHINE(vms)->smp.max_cpus;
1826 bool aarch64, pmu, steal_time;
1827 CPUState *cpu;
1828
1829 aarch64 = object_property_get_bool(OBJECT(first_cpu), "aarch64", NULL);
1830 pmu = object_property_get_bool(OBJECT(first_cpu), "pmu", NULL);
1831 steal_time = object_property_get_bool(OBJECT(first_cpu),
1832 "kvm-steal-time", NULL);
1833
1834 if (kvm_enabled()) {
1835 hwaddr pvtime_reg_base = vms->memmap[VIRT_PVTIME].base;
1836 hwaddr pvtime_reg_size = vms->memmap[VIRT_PVTIME].size;
1837
1838 if (steal_time) {
1839 MemoryRegion *pvtime = g_new(MemoryRegion, 1);
1840 hwaddr pvtime_size = max_cpus * PVTIME_SIZE_PER_CPU;
1841
1842
1843 pvtime_size = REAL_HOST_PAGE_ALIGN(pvtime_size);
1844
1845 if (pvtime_size > pvtime_reg_size) {
1846 error_report("pvtime requires a %" HWADDR_PRId
1847 " byte memory region for %d CPUs,"
1848 " but only %" HWADDR_PRId " has been reserved",
1849 pvtime_size, max_cpus, pvtime_reg_size);
1850 exit(1);
1851 }
1852
1853 memory_region_init_ram(pvtime, NULL, "pvtime", pvtime_size, NULL);
1854 memory_region_add_subregion(sysmem, pvtime_reg_base, pvtime);
1855 }
1856
1857 CPU_FOREACH(cpu) {
1858 if (pmu) {
1859 assert(arm_feature(&ARM_CPU(cpu)->env, ARM_FEATURE_PMU));
1860 if (kvm_irqchip_in_kernel()) {
1861 kvm_arm_pmu_set_irq(cpu, PPI(VIRTUAL_PMU_IRQ));
1862 }
1863 kvm_arm_pmu_init(cpu);
1864 }
1865 if (steal_time) {
1866 kvm_arm_pvtime_init(cpu, pvtime_reg_base +
1867 cpu->cpu_index * PVTIME_SIZE_PER_CPU);
1868 }
1869 }
1870 } else {
1871 if (aarch64 && vms->highmem) {
1872 int requested_pa_size = 64 - clz64(vms->highest_gpa);
1873 int pamax = arm_pamax(ARM_CPU(first_cpu));
1874
1875 if (pamax < requested_pa_size) {
1876 error_report("VCPU supports less PA bits (%d) than "
1877 "requested by the memory map (%d)",
1878 pamax, requested_pa_size);
1879 exit(1);
1880 }
1881 }
1882 }
1883}
1884
1885static void machvirt_init(MachineState *machine)
1886{
1887 VirtMachineState *vms = VIRT_MACHINE(machine);
1888 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(machine);
1889 MachineClass *mc = MACHINE_GET_CLASS(machine);
1890 const CPUArchIdList *possible_cpus;
1891 MemoryRegion *sysmem = get_system_memory();
1892 MemoryRegion *secure_sysmem = NULL;
1893 MemoryRegion *tag_sysmem = NULL;
1894 MemoryRegion *secure_tag_sysmem = NULL;
1895 int n, virt_max_cpus;
1896 bool firmware_loaded;
1897 bool aarch64 = true;
1898 bool has_ged = !vmc->no_ged;
1899 unsigned int smp_cpus = machine->smp.cpus;
1900 unsigned int max_cpus = machine->smp.max_cpus;
1901
1902
1903
1904
1905
1906 if (!vms->memmap) {
1907 virt_set_memmap(vms);
1908 }
1909
1910
1911
1912
1913 finalize_gic_version(vms);
1914
1915 if (!cpu_type_valid(machine->cpu_type)) {
1916 error_report("mach-virt: CPU type %s not supported", machine->cpu_type);
1917 exit(1);
1918 }
1919
1920 if (vms->secure) {
1921
1922
1923
1924
1925
1926
1927 secure_sysmem = g_new(MemoryRegion, 1);
1928 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory",
1929 UINT64_MAX);
1930 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1);
1931 }
1932
1933 firmware_loaded = virt_firmware_init(vms, sysmem,
1934 secure_sysmem ?: sysmem);
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944
1945
1946 if (vms->secure && firmware_loaded) {
1947 vms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED;
1948 } else if (vms->virt) {
1949 vms->psci_conduit = QEMU_PSCI_CONDUIT_SMC;
1950 } else {
1951 vms->psci_conduit = QEMU_PSCI_CONDUIT_HVC;
1952 }
1953
1954
1955
1956
1957 if (vms->gic_version == VIRT_GIC_VERSION_3) {
1958 virt_max_cpus =
1959 vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE;
1960 virt_max_cpus +=
1961 vms->memmap[VIRT_HIGH_GIC_REDIST2].size / GICV3_REDIST_SIZE;
1962 } else {
1963 virt_max_cpus = GIC_NCPU;
1964 }
1965
1966 if (max_cpus > virt_max_cpus) {
1967 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs "
1968 "supported by machine 'mach-virt' (%d)",
1969 max_cpus, virt_max_cpus);
1970 exit(1);
1971 }
1972
1973 if (vms->virt && (kvm_enabled() || hvf_enabled())) {
1974 error_report("mach-virt: %s does not support providing "
1975 "Virtualization extensions to the guest CPU",
1976 kvm_enabled() ? "KVM" : "HVF");
1977 exit(1);
1978 }
1979
1980 if (vms->mte && (kvm_enabled() || hvf_enabled())) {
1981 error_report("mach-virt: %s does not support providing "
1982 "MTE to the guest CPU",
1983 kvm_enabled() ? "KVM" : "HVF");
1984 exit(1);
1985 }
1986
1987 create_fdt(vms);
1988
1989 possible_cpus = mc->possible_cpu_arch_ids(machine);
1990 assert(possible_cpus->len == max_cpus);
1991 for (n = 0; n < possible_cpus->len; n++) {
1992 Object *cpuobj;
1993 CPUState *cs;
1994
1995 if (n >= smp_cpus) {
1996 break;
1997 }
1998
1999 cpuobj = object_new(possible_cpus->cpus[n].type);
2000 object_property_set_int(cpuobj, "mp-affinity",
2001 possible_cpus->cpus[n].arch_id, NULL);
2002
2003 cs = CPU(cpuobj);
2004 cs->cpu_index = n;
2005
2006 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj),
2007 &error_fatal);
2008
2009 aarch64 &= object_property_get_bool(cpuobj, "aarch64", NULL);
2010
2011 if (!vms->secure) {
2012 object_property_set_bool(cpuobj, "has_el3", false, NULL);
2013 }
2014
2015 if (!vms->virt && object_property_find(cpuobj, "has_el2")) {
2016 object_property_set_bool(cpuobj, "has_el2", false, NULL);
2017 }
2018
2019 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED) {
2020 object_property_set_int(cpuobj, "psci-conduit", vms->psci_conduit,
2021 NULL);
2022
2023
2024 if (n > 0) {
2025 object_property_set_bool(cpuobj, "start-powered-off", true,
2026 NULL);
2027 }
2028 }
2029
2030 if (vmc->kvm_no_adjvtime &&
2031 object_property_find(cpuobj, "kvm-no-adjvtime")) {
2032 object_property_set_bool(cpuobj, "kvm-no-adjvtime", true, NULL);
2033 }
2034
2035 if (vmc->no_kvm_steal_time &&
2036 object_property_find(cpuobj, "kvm-steal-time")) {
2037 object_property_set_bool(cpuobj, "kvm-steal-time", false, NULL);
2038 }
2039
2040 if (vmc->no_pmu && object_property_find(cpuobj, "pmu")) {
2041 object_property_set_bool(cpuobj, "pmu", false, NULL);
2042 }
2043
2044 if (object_property_find(cpuobj, "reset-cbar")) {
2045 object_property_set_int(cpuobj, "reset-cbar",
2046 vms->memmap[VIRT_CPUPERIPHS].base,
2047 &error_abort);
2048 }
2049
2050 object_property_set_link(cpuobj, "memory", OBJECT(sysmem),
2051 &error_abort);
2052 if (vms->secure) {
2053 object_property_set_link(cpuobj, "secure-memory",
2054 OBJECT(secure_sysmem), &error_abort);
2055 }
2056
2057 if (vms->mte) {
2058
2059 if (!tag_sysmem) {
2060
2061
2062
2063
2064 if (!object_property_find(cpuobj, "tag-memory")) {
2065 error_report("MTE requested, but not supported "
2066 "by the guest CPU");
2067 exit(1);
2068 }
2069
2070 tag_sysmem = g_new(MemoryRegion, 1);
2071 memory_region_init(tag_sysmem, OBJECT(machine),
2072 "tag-memory", UINT64_MAX / 32);
2073
2074 if (vms->secure) {
2075 secure_tag_sysmem = g_new(MemoryRegion, 1);
2076 memory_region_init(secure_tag_sysmem, OBJECT(machine),
2077 "secure-tag-memory", UINT64_MAX / 32);
2078
2079
2080 memory_region_add_subregion_overlap(secure_tag_sysmem, 0,
2081 tag_sysmem, -1);
2082 }
2083 }
2084
2085 object_property_set_link(cpuobj, "tag-memory", OBJECT(tag_sysmem),
2086 &error_abort);
2087 if (vms->secure) {
2088 object_property_set_link(cpuobj, "secure-tag-memory",
2089 OBJECT(secure_tag_sysmem),
2090 &error_abort);
2091 }
2092 }
2093
2094 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
2095 object_unref(cpuobj);
2096 }
2097 fdt_add_timer_nodes(vms);
2098 fdt_add_cpu_nodes(vms);
2099
2100 memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base,
2101 machine->ram);
2102 if (machine->device_memory) {
2103 memory_region_add_subregion(sysmem, machine->device_memory->base,
2104 &machine->device_memory->mr);
2105 }
2106
2107 virt_flash_fdt(vms, sysmem, secure_sysmem ?: sysmem);
2108
2109 create_gic(vms, sysmem);
2110
2111 virt_cpu_post_init(vms, sysmem);
2112
2113 fdt_add_pmu_nodes(vms);
2114
2115 create_uart(vms, VIRT_UART, sysmem, serial_hd(0));
2116
2117 if (vms->secure) {
2118 create_secure_ram(vms, secure_sysmem, secure_tag_sysmem);
2119 create_uart(vms, VIRT_SECURE_UART, secure_sysmem, serial_hd(1));
2120 }
2121
2122 if (tag_sysmem) {
2123 create_tag_ram(tag_sysmem, vms->memmap[VIRT_MEM].base,
2124 machine->ram_size, "mach-virt.tag");
2125 }
2126
2127 vms->highmem_ecam &= vms->highmem && (!firmware_loaded || aarch64);
2128
2129 create_rtc(vms);
2130
2131 create_pcie(vms);
2132
2133 if (has_ged && aarch64 && firmware_loaded && virt_is_acpi_enabled(vms)) {
2134 vms->acpi_dev = create_acpi_ged(vms);
2135 } else {
2136 create_gpio_devices(vms, VIRT_GPIO, sysmem);
2137 }
2138
2139 if (vms->secure && !vmc->no_secure_gpio) {
2140 create_gpio_devices(vms, VIRT_SECURE_GPIO, secure_sysmem);
2141 }
2142
2143
2144 vms->powerdown_notifier.notify = virt_powerdown_req;
2145 qemu_register_powerdown_notifier(&vms->powerdown_notifier);
2146
2147
2148
2149
2150
2151 create_virtio_devices(vms);
2152
2153 vms->fw_cfg = create_fw_cfg(vms, &address_space_memory);
2154 rom_set_fw(vms->fw_cfg);
2155
2156 create_platform_bus(vms);
2157
2158 if (machine->nvdimms_state->is_enabled) {
2159 const struct AcpiGenericAddress arm_virt_nvdimm_acpi_dsmio = {
2160 .space_id = AML_AS_SYSTEM_MEMORY,
2161 .address = vms->memmap[VIRT_NVDIMM_ACPI].base,
2162 .bit_width = NVDIMM_ACPI_IO_LEN << 3
2163 };
2164
2165 nvdimm_init_acpi_state(machine->nvdimms_state, sysmem,
2166 arm_virt_nvdimm_acpi_dsmio,
2167 vms->fw_cfg, OBJECT(vms));
2168 }
2169
2170 vms->bootinfo.ram_size = machine->ram_size;
2171 vms->bootinfo.nb_cpus = smp_cpus;
2172 vms->bootinfo.board_id = -1;
2173 vms->bootinfo.loader_start = vms->memmap[VIRT_MEM].base;
2174 vms->bootinfo.get_dtb = machvirt_dtb;
2175 vms->bootinfo.skip_dtb_autoload = true;
2176 vms->bootinfo.firmware_loaded = firmware_loaded;
2177 arm_load_kernel(ARM_CPU(first_cpu), machine, &vms->bootinfo);
2178
2179 vms->machine_done.notify = virt_machine_done;
2180 qemu_add_machine_init_done_notifier(&vms->machine_done);
2181}
2182
2183static bool virt_get_secure(Object *obj, Error **errp)
2184{
2185 VirtMachineState *vms = VIRT_MACHINE(obj);
2186
2187 return vms->secure;
2188}
2189
2190static void virt_set_secure(Object *obj, bool value, Error **errp)
2191{
2192 VirtMachineState *vms = VIRT_MACHINE(obj);
2193
2194 vms->secure = value;
2195}
2196
2197static bool virt_get_virt(Object *obj, Error **errp)
2198{
2199 VirtMachineState *vms = VIRT_MACHINE(obj);
2200
2201 return vms->virt;
2202}
2203
2204static void virt_set_virt(Object *obj, bool value, Error **errp)
2205{
2206 VirtMachineState *vms = VIRT_MACHINE(obj);
2207
2208 vms->virt = value;
2209}
2210
2211static bool virt_get_highmem(Object *obj, Error **errp)
2212{
2213 VirtMachineState *vms = VIRT_MACHINE(obj);
2214
2215 return vms->highmem;
2216}
2217
2218static void virt_set_highmem(Object *obj, bool value, Error **errp)
2219{
2220 VirtMachineState *vms = VIRT_MACHINE(obj);
2221
2222 vms->highmem = value;
2223}
2224
2225static bool virt_get_its(Object *obj, Error **errp)
2226{
2227 VirtMachineState *vms = VIRT_MACHINE(obj);
2228
2229 return vms->its;
2230}
2231
2232static void virt_set_its(Object *obj, bool value, Error **errp)
2233{
2234 VirtMachineState *vms = VIRT_MACHINE(obj);
2235
2236 vms->its = value;
2237}
2238
2239static char *virt_get_oem_id(Object *obj, Error **errp)
2240{
2241 VirtMachineState *vms = VIRT_MACHINE(obj);
2242
2243 return g_strdup(vms->oem_id);
2244}
2245
2246static void virt_set_oem_id(Object *obj, const char *value, Error **errp)
2247{
2248 VirtMachineState *vms = VIRT_MACHINE(obj);
2249 size_t len = strlen(value);
2250
2251 if (len > 6) {
2252 error_setg(errp,
2253 "User specified oem-id value is bigger than 6 bytes in size");
2254 return;
2255 }
2256
2257 strncpy(vms->oem_id, value, 6);
2258}
2259
2260static char *virt_get_oem_table_id(Object *obj, Error **errp)
2261{
2262 VirtMachineState *vms = VIRT_MACHINE(obj);
2263
2264 return g_strdup(vms->oem_table_id);
2265}
2266
2267static void virt_set_oem_table_id(Object *obj, const char *value,
2268 Error **errp)
2269{
2270 VirtMachineState *vms = VIRT_MACHINE(obj);
2271 size_t len = strlen(value);
2272
2273 if (len > 8) {
2274 error_setg(errp,
2275 "User specified oem-table-id value is bigger than 8 bytes in size");
2276 return;
2277 }
2278 strncpy(vms->oem_table_id, value, 8);
2279}
2280
2281
2282bool virt_is_acpi_enabled(VirtMachineState *vms)
2283{
2284 if (vms->acpi == ON_OFF_AUTO_OFF) {
2285 return false;
2286 }
2287 return true;
2288}
2289
2290static void virt_get_acpi(Object *obj, Visitor *v, const char *name,
2291 void *opaque, Error **errp)
2292{
2293 VirtMachineState *vms = VIRT_MACHINE(obj);
2294 OnOffAuto acpi = vms->acpi;
2295
2296 visit_type_OnOffAuto(v, name, &acpi, errp);
2297}
2298
2299static void virt_set_acpi(Object *obj, Visitor *v, const char *name,
2300 void *opaque, Error **errp)
2301{
2302 VirtMachineState *vms = VIRT_MACHINE(obj);
2303
2304 visit_type_OnOffAuto(v, name, &vms->acpi, errp);
2305}
2306
2307static bool virt_get_ras(Object *obj, Error **errp)
2308{
2309 VirtMachineState *vms = VIRT_MACHINE(obj);
2310
2311 return vms->ras;
2312}
2313
2314static void virt_set_ras(Object *obj, bool value, Error **errp)
2315{
2316 VirtMachineState *vms = VIRT_MACHINE(obj);
2317
2318 vms->ras = value;
2319}
2320
2321static bool virt_get_mte(Object *obj, Error **errp)
2322{
2323 VirtMachineState *vms = VIRT_MACHINE(obj);
2324
2325 return vms->mte;
2326}
2327
2328static void virt_set_mte(Object *obj, bool value, Error **errp)
2329{
2330 VirtMachineState *vms = VIRT_MACHINE(obj);
2331
2332 vms->mte = value;
2333}
2334
2335static char *virt_get_gic_version(Object *obj, Error **errp)
2336{
2337 VirtMachineState *vms = VIRT_MACHINE(obj);
2338 const char *val = vms->gic_version == VIRT_GIC_VERSION_3 ? "3" : "2";
2339
2340 return g_strdup(val);
2341}
2342
2343static void virt_set_gic_version(Object *obj, const char *value, Error **errp)
2344{
2345 VirtMachineState *vms = VIRT_MACHINE(obj);
2346
2347 if (!strcmp(value, "3")) {
2348 vms->gic_version = VIRT_GIC_VERSION_3;
2349 } else if (!strcmp(value, "2")) {
2350 vms->gic_version = VIRT_GIC_VERSION_2;
2351 } else if (!strcmp(value, "host")) {
2352 vms->gic_version = VIRT_GIC_VERSION_HOST;
2353 } else if (!strcmp(value, "max")) {
2354 vms->gic_version = VIRT_GIC_VERSION_MAX;
2355 } else {
2356 error_setg(errp, "Invalid gic-version value");
2357 error_append_hint(errp, "Valid values are 3, 2, host, max.\n");
2358 }
2359}
2360
2361static char *virt_get_iommu(Object *obj, Error **errp)
2362{
2363 VirtMachineState *vms = VIRT_MACHINE(obj);
2364
2365 switch (vms->iommu) {
2366 case VIRT_IOMMU_NONE:
2367 return g_strdup("none");
2368 case VIRT_IOMMU_SMMUV3:
2369 return g_strdup("smmuv3");
2370 default:
2371 g_assert_not_reached();
2372 }
2373}
2374
2375static void virt_set_iommu(Object *obj, const char *value, Error **errp)
2376{
2377 VirtMachineState *vms = VIRT_MACHINE(obj);
2378
2379 if (!strcmp(value, "smmuv3")) {
2380 vms->iommu = VIRT_IOMMU_SMMUV3;
2381 } else if (!strcmp(value, "none")) {
2382 vms->iommu = VIRT_IOMMU_NONE;
2383 } else {
2384 error_setg(errp, "Invalid iommu value");
2385 error_append_hint(errp, "Valid values are none, smmuv3.\n");
2386 }
2387}
2388
2389static bool virt_get_default_bus_bypass_iommu(Object *obj, Error **errp)
2390{
2391 VirtMachineState *vms = VIRT_MACHINE(obj);
2392
2393 return vms->default_bus_bypass_iommu;
2394}
2395
2396static void virt_set_default_bus_bypass_iommu(Object *obj, bool value,
2397 Error **errp)
2398{
2399 VirtMachineState *vms = VIRT_MACHINE(obj);
2400
2401 vms->default_bus_bypass_iommu = value;
2402}
2403
2404static CpuInstanceProperties
2405virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
2406{
2407 MachineClass *mc = MACHINE_GET_CLASS(ms);
2408 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms);
2409
2410 assert(cpu_index < possible_cpus->len);
2411 return possible_cpus->cpus[cpu_index].props;
2412}
2413
2414static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx)
2415{
2416 return idx % ms->numa_state->num_nodes;
2417}
2418
2419static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
2420{
2421 int n;
2422 unsigned int max_cpus = ms->smp.max_cpus;
2423 VirtMachineState *vms = VIRT_MACHINE(ms);
2424
2425 if (ms->possible_cpus) {
2426 assert(ms->possible_cpus->len == max_cpus);
2427 return ms->possible_cpus;
2428 }
2429
2430 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
2431 sizeof(CPUArchId) * max_cpus);
2432 ms->possible_cpus->len = max_cpus;
2433 for (n = 0; n < ms->possible_cpus->len; n++) {
2434 ms->possible_cpus->cpus[n].type = ms->cpu_type;
2435 ms->possible_cpus->cpus[n].arch_id =
2436 virt_cpu_mp_affinity(vms, n);
2437 ms->possible_cpus->cpus[n].props.has_thread_id = true;
2438 ms->possible_cpus->cpus[n].props.thread_id = n;
2439 }
2440 return ms->possible_cpus;
2441}
2442
2443static void virt_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
2444 Error **errp)
2445{
2446 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2447 const MachineState *ms = MACHINE(hotplug_dev);
2448 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
2449
2450 if (!vms->acpi_dev) {
2451 error_setg(errp,
2452 "memory hotplug is not enabled: missing acpi-ged device");
2453 return;
2454 }
2455
2456 if (vms->mte) {
2457 error_setg(errp, "memory hotplug is not enabled: MTE is enabled");
2458 return;
2459 }
2460
2461 if (is_nvdimm && !ms->nvdimms_state->is_enabled) {
2462 error_setg(errp, "nvdimm is not enabled: add 'nvdimm=on' to '-M'");
2463 return;
2464 }
2465
2466 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), NULL, errp);
2467}
2468
2469static void virt_memory_plug(HotplugHandler *hotplug_dev,
2470 DeviceState *dev, Error **errp)
2471{
2472 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2473 MachineState *ms = MACHINE(hotplug_dev);
2474 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
2475
2476 pc_dimm_plug(PC_DIMM(dev), MACHINE(vms));
2477
2478 if (is_nvdimm) {
2479 nvdimm_plug(ms->nvdimms_state);
2480 }
2481
2482 hotplug_handler_plug(HOTPLUG_HANDLER(vms->acpi_dev),
2483 dev, &error_abort);
2484}
2485
2486static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
2487 DeviceState *dev, Error **errp)
2488{
2489 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2490
2491 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2492 virt_memory_pre_plug(hotplug_dev, dev, errp);
2493 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
2494 hwaddr db_start = 0, db_end = 0;
2495 char *resv_prop_str;
2496
2497 switch (vms->msi_controller) {
2498 case VIRT_MSI_CTRL_NONE:
2499 return;
2500 case VIRT_MSI_CTRL_ITS:
2501
2502 db_start = base_memmap[VIRT_GIC_ITS].base + 0x10000;
2503 db_end = base_memmap[VIRT_GIC_ITS].base +
2504 base_memmap[VIRT_GIC_ITS].size - 1;
2505 break;
2506 case VIRT_MSI_CTRL_GICV2M:
2507
2508 db_start = base_memmap[VIRT_GIC_V2M].base;
2509 db_end = db_start + base_memmap[VIRT_GIC_V2M].size - 1;
2510 break;
2511 }
2512 resv_prop_str = g_strdup_printf("0x%"PRIx64":0x%"PRIx64":%u",
2513 db_start, db_end,
2514 VIRTIO_IOMMU_RESV_MEM_T_MSI);
2515
2516 qdev_prop_set_uint32(dev, "len-reserved-regions", 1);
2517 qdev_prop_set_string(dev, "reserved-regions[0]", resv_prop_str);
2518 g_free(resv_prop_str);
2519 }
2520}
2521
2522static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev,
2523 DeviceState *dev, Error **errp)
2524{
2525 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2526
2527 if (vms->platform_bus_dev) {
2528 MachineClass *mc = MACHINE_GET_CLASS(vms);
2529
2530 if (device_is_dynamic_sysbus(mc, dev)) {
2531 platform_bus_link_device(PLATFORM_BUS_DEVICE(vms->platform_bus_dev),
2532 SYS_BUS_DEVICE(dev));
2533 }
2534 }
2535 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2536 virt_memory_plug(hotplug_dev, dev, errp);
2537 }
2538 if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
2539 PCIDevice *pdev = PCI_DEVICE(dev);
2540
2541 vms->iommu = VIRT_IOMMU_VIRTIO;
2542 vms->virtio_iommu_bdf = pci_get_bdf(pdev);
2543 create_virtio_iommu_dt_bindings(vms);
2544 }
2545}
2546
2547static void virt_dimm_unplug_request(HotplugHandler *hotplug_dev,
2548 DeviceState *dev, Error **errp)
2549{
2550 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2551 Error *local_err = NULL;
2552
2553 if (!vms->acpi_dev) {
2554 error_setg(&local_err,
2555 "memory hotplug is not enabled: missing acpi-ged device");
2556 goto out;
2557 }
2558
2559 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
2560 error_setg(&local_err,
2561 "nvdimm device hot unplug is not supported yet.");
2562 goto out;
2563 }
2564
2565 hotplug_handler_unplug_request(HOTPLUG_HANDLER(vms->acpi_dev), dev,
2566 &local_err);
2567out:
2568 error_propagate(errp, local_err);
2569}
2570
2571static void virt_dimm_unplug(HotplugHandler *hotplug_dev,
2572 DeviceState *dev, Error **errp)
2573{
2574 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2575 Error *local_err = NULL;
2576
2577 hotplug_handler_unplug(HOTPLUG_HANDLER(vms->acpi_dev), dev, &local_err);
2578 if (local_err) {
2579 goto out;
2580 }
2581
2582 pc_dimm_unplug(PC_DIMM(dev), MACHINE(vms));
2583 qdev_unrealize(dev);
2584
2585out:
2586 error_propagate(errp, local_err);
2587}
2588
2589static void virt_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev,
2590 DeviceState *dev, Error **errp)
2591{
2592 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2593 virt_dimm_unplug_request(hotplug_dev, dev, errp);
2594 } else {
2595 error_setg(errp, "device unplug request for unsupported device"
2596 " type: %s", object_get_typename(OBJECT(dev)));
2597 }
2598}
2599
2600static void virt_machine_device_unplug_cb(HotplugHandler *hotplug_dev,
2601 DeviceState *dev, Error **errp)
2602{
2603 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2604 virt_dimm_unplug(hotplug_dev, dev, errp);
2605 } else {
2606 error_setg(errp, "virt: device unplug for unsupported device"
2607 " type: %s", object_get_typename(OBJECT(dev)));
2608 }
2609}
2610
2611static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine,
2612 DeviceState *dev)
2613{
2614 MachineClass *mc = MACHINE_GET_CLASS(machine);
2615
2616 if (device_is_dynamic_sysbus(mc, dev) ||
2617 (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM))) {
2618 return HOTPLUG_HANDLER(machine);
2619 }
2620 if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
2621 VirtMachineState *vms = VIRT_MACHINE(machine);
2622
2623 if (!vms->bootinfo.firmware_loaded || !virt_is_acpi_enabled(vms)) {
2624 return HOTPLUG_HANDLER(machine);
2625 }
2626 }
2627 return NULL;
2628}
2629
2630
2631
2632
2633
2634static int virt_kvm_type(MachineState *ms, const char *type_str)
2635{
2636 VirtMachineState *vms = VIRT_MACHINE(ms);
2637 int max_vm_pa_size, requested_pa_size;
2638 bool fixed_ipa;
2639
2640 max_vm_pa_size = kvm_arm_get_max_vm_ipa_size(ms, &fixed_ipa);
2641
2642
2643 virt_set_memmap(vms);
2644
2645 requested_pa_size = 64 - clz64(vms->highest_gpa);
2646
2647
2648
2649
2650 if (requested_pa_size < 32) {
2651 requested_pa_size = 32;
2652 }
2653
2654 if (requested_pa_size > max_vm_pa_size) {
2655 error_report("-m and ,maxmem option values "
2656 "require an IPA range (%d bits) larger than "
2657 "the one supported by the host (%d bits)",
2658 requested_pa_size, max_vm_pa_size);
2659 exit(1);
2660 }
2661
2662
2663
2664
2665
2666 return fixed_ipa ? 0 : requested_pa_size;
2667}
2668
2669static void virt_machine_class_init(ObjectClass *oc, void *data)
2670{
2671 MachineClass *mc = MACHINE_CLASS(oc);
2672 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
2673
2674 mc->init = machvirt_init;
2675
2676
2677
2678
2679 mc->max_cpus = 512;
2680 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_CALXEDA_XGMAC);
2681 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_AMD_XGBE);
2682 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
2683 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_PLATFORM);
2684#ifdef CONFIG_TPM
2685 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS);
2686#endif
2687 mc->block_default_type = IF_VIRTIO;
2688 mc->no_cdrom = 1;
2689 mc->pci_allow_0_address = true;
2690
2691 mc->minimum_page_bits = 12;
2692 mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids;
2693 mc->cpu_index_to_instance_props = virt_cpu_index_to_props;
2694 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
2695 mc->get_default_cpu_node_id = virt_get_default_cpu_node_id;
2696 mc->kvm_type = virt_kvm_type;
2697 assert(!mc->get_hotplug_handler);
2698 mc->get_hotplug_handler = virt_machine_get_hotplug_handler;
2699 hc->pre_plug = virt_machine_device_pre_plug_cb;
2700 hc->plug = virt_machine_device_plug_cb;
2701 hc->unplug_request = virt_machine_device_unplug_request_cb;
2702 hc->unplug = virt_machine_device_unplug_cb;
2703 mc->nvdimm_supported = true;
2704 mc->auto_enable_numa_with_memhp = true;
2705 mc->auto_enable_numa_with_memdev = true;
2706 mc->default_ram_id = "mach-virt.ram";
2707
2708 object_class_property_add(oc, "acpi", "OnOffAuto",
2709 virt_get_acpi, virt_set_acpi,
2710 NULL, NULL);
2711 object_class_property_set_description(oc, "acpi",
2712 "Enable ACPI");
2713 object_class_property_add_bool(oc, "secure", virt_get_secure,
2714 virt_set_secure);
2715 object_class_property_set_description(oc, "secure",
2716 "Set on/off to enable/disable the ARM "
2717 "Security Extensions (TrustZone)");
2718
2719 object_class_property_add_bool(oc, "virtualization", virt_get_virt,
2720 virt_set_virt);
2721 object_class_property_set_description(oc, "virtualization",
2722 "Set on/off to enable/disable emulating a "
2723 "guest CPU which implements the ARM "
2724 "Virtualization Extensions");
2725
2726 object_class_property_add_bool(oc, "highmem", virt_get_highmem,
2727 virt_set_highmem);
2728 object_class_property_set_description(oc, "highmem",
2729 "Set on/off to enable/disable using "
2730 "physical address space above 32 bits");
2731
2732 object_class_property_add_str(oc, "gic-version", virt_get_gic_version,
2733 virt_set_gic_version);
2734 object_class_property_set_description(oc, "gic-version",
2735 "Set GIC version. "
2736 "Valid values are 2, 3, host and max");
2737
2738 object_class_property_add_str(oc, "iommu", virt_get_iommu, virt_set_iommu);
2739 object_class_property_set_description(oc, "iommu",
2740 "Set the IOMMU type. "
2741 "Valid values are none and smmuv3");
2742
2743 object_class_property_add_bool(oc, "default-bus-bypass-iommu",
2744 virt_get_default_bus_bypass_iommu,
2745 virt_set_default_bus_bypass_iommu);
2746 object_class_property_set_description(oc, "default-bus-bypass-iommu",
2747 "Set on/off to enable/disable "
2748 "bypass_iommu for default root bus");
2749
2750 object_class_property_add_bool(oc, "ras", virt_get_ras,
2751 virt_set_ras);
2752 object_class_property_set_description(oc, "ras",
2753 "Set on/off to enable/disable reporting host memory errors "
2754 "to a KVM guest using ACPI and guest external abort exceptions");
2755
2756 object_class_property_add_bool(oc, "mte", virt_get_mte, virt_set_mte);
2757 object_class_property_set_description(oc, "mte",
2758 "Set on/off to enable/disable emulating a "
2759 "guest CPU which implements the ARM "
2760 "Memory Tagging Extension");
2761
2762 object_class_property_add_bool(oc, "its", virt_get_its,
2763 virt_set_its);
2764 object_class_property_set_description(oc, "its",
2765 "Set on/off to enable/disable "
2766 "ITS instantiation");
2767
2768 object_class_property_add_str(oc, "x-oem-id",
2769 virt_get_oem_id,
2770 virt_set_oem_id);
2771 object_class_property_set_description(oc, "x-oem-id",
2772 "Override the default value of field OEMID "
2773 "in ACPI table header."
2774 "The string may be up to 6 bytes in size");
2775
2776
2777 object_class_property_add_str(oc, "x-oem-table-id",
2778 virt_get_oem_table_id,
2779 virt_set_oem_table_id);
2780 object_class_property_set_description(oc, "x-oem-table-id",
2781 "Override the default value of field OEM Table ID "
2782 "in ACPI table header."
2783 "The string may be up to 8 bytes in size");
2784
2785}
2786
2787static void virt_instance_init(Object *obj)
2788{
2789 VirtMachineState *vms = VIRT_MACHINE(obj);
2790 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
2791
2792
2793
2794
2795
2796 vms->secure = false;
2797
2798
2799 vms->virt = false;
2800
2801
2802 vms->highmem = true;
2803 vms->gic_version = VIRT_GIC_VERSION_NOSEL;
2804
2805 vms->highmem_ecam = !vmc->no_highmem_ecam;
2806
2807 if (vmc->no_its) {
2808 vms->its = false;
2809 } else {
2810
2811 vms->its = true;
2812
2813 if (vmc->no_tcg_its) {
2814 vms->tcg_its = false;
2815 } else {
2816 vms->tcg_its = true;
2817 }
2818 }
2819
2820
2821 vms->iommu = VIRT_IOMMU_NONE;
2822
2823
2824 vms->default_bus_bypass_iommu = false;
2825
2826
2827 vms->ras = false;
2828
2829
2830 vms->mte = false;
2831
2832 vms->irqmap = a15irqmap;
2833
2834 virt_flash_create(vms);
2835
2836 vms->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6);
2837 vms->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8);
2838}
2839
2840static const TypeInfo virt_machine_info = {
2841 .name = TYPE_VIRT_MACHINE,
2842 .parent = TYPE_MACHINE,
2843 .abstract = true,
2844 .instance_size = sizeof(VirtMachineState),
2845 .class_size = sizeof(VirtMachineClass),
2846 .class_init = virt_machine_class_init,
2847 .instance_init = virt_instance_init,
2848 .interfaces = (InterfaceInfo[]) {
2849 { TYPE_HOTPLUG_HANDLER },
2850 { }
2851 },
2852};
2853
2854static void machvirt_machine_init(void)
2855{
2856 type_register_static(&virt_machine_info);
2857}
2858type_init(machvirt_machine_init);
2859
2860static void virt_machine_6_2_options(MachineClass *mc)
2861{
2862}
2863DEFINE_VIRT_MACHINE_AS_LATEST(6, 2)
2864
2865static void virt_machine_6_1_options(MachineClass *mc)
2866{
2867 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2868
2869 virt_machine_6_2_options(mc);
2870 compat_props_add(mc->compat_props, hw_compat_6_1, hw_compat_6_1_len);
2871 mc->smp_props.prefer_sockets = true;
2872 vmc->no_cpu_topology = true;
2873
2874
2875 vmc->no_tcg_its = true;
2876}
2877DEFINE_VIRT_MACHINE(6, 1)
2878
2879static void virt_machine_6_0_options(MachineClass *mc)
2880{
2881 virt_machine_6_1_options(mc);
2882 compat_props_add(mc->compat_props, hw_compat_6_0, hw_compat_6_0_len);
2883}
2884DEFINE_VIRT_MACHINE(6, 0)
2885
2886static void virt_machine_5_2_options(MachineClass *mc)
2887{
2888 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2889
2890 virt_machine_6_0_options(mc);
2891 compat_props_add(mc->compat_props, hw_compat_5_2, hw_compat_5_2_len);
2892 vmc->no_secure_gpio = true;
2893}
2894DEFINE_VIRT_MACHINE(5, 2)
2895
2896static void virt_machine_5_1_options(MachineClass *mc)
2897{
2898 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2899
2900 virt_machine_5_2_options(mc);
2901 compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len);
2902 vmc->no_kvm_steal_time = true;
2903}
2904DEFINE_VIRT_MACHINE(5, 1)
2905
2906static void virt_machine_5_0_options(MachineClass *mc)
2907{
2908 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2909
2910 virt_machine_5_1_options(mc);
2911 compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len);
2912 mc->numa_mem_supported = true;
2913 vmc->acpi_expose_flash = true;
2914 mc->auto_enable_numa_with_memdev = false;
2915}
2916DEFINE_VIRT_MACHINE(5, 0)
2917
2918static void virt_machine_4_2_options(MachineClass *mc)
2919{
2920 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2921
2922 virt_machine_5_0_options(mc);
2923 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len);
2924 vmc->kvm_no_adjvtime = true;
2925}
2926DEFINE_VIRT_MACHINE(4, 2)
2927
2928static void virt_machine_4_1_options(MachineClass *mc)
2929{
2930 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2931
2932 virt_machine_4_2_options(mc);
2933 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len);
2934 vmc->no_ged = true;
2935 mc->auto_enable_numa_with_memhp = false;
2936}
2937DEFINE_VIRT_MACHINE(4, 1)
2938
2939static void virt_machine_4_0_options(MachineClass *mc)
2940{
2941 virt_machine_4_1_options(mc);
2942 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len);
2943}
2944DEFINE_VIRT_MACHINE(4, 0)
2945
2946static void virt_machine_3_1_options(MachineClass *mc)
2947{
2948 virt_machine_4_0_options(mc);
2949 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len);
2950}
2951DEFINE_VIRT_MACHINE(3, 1)
2952
2953static void virt_machine_3_0_options(MachineClass *mc)
2954{
2955 virt_machine_3_1_options(mc);
2956 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len);
2957}
2958DEFINE_VIRT_MACHINE(3, 0)
2959
2960static void virt_machine_2_12_options(MachineClass *mc)
2961{
2962 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2963
2964 virt_machine_3_0_options(mc);
2965 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len);
2966 vmc->no_highmem_ecam = true;
2967 mc->max_cpus = 255;
2968}
2969DEFINE_VIRT_MACHINE(2, 12)
2970
2971static void virt_machine_2_11_options(MachineClass *mc)
2972{
2973 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2974
2975 virt_machine_2_12_options(mc);
2976 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len);
2977 vmc->smbios_old_sys_ver = true;
2978}
2979DEFINE_VIRT_MACHINE(2, 11)
2980
2981static void virt_machine_2_10_options(MachineClass *mc)
2982{
2983 virt_machine_2_11_options(mc);
2984 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len);
2985
2986 mc->ignore_memory_transaction_failures = true;
2987}
2988DEFINE_VIRT_MACHINE(2, 10)
2989
2990static void virt_machine_2_9_options(MachineClass *mc)
2991{
2992 virt_machine_2_10_options(mc);
2993 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len);
2994}
2995DEFINE_VIRT_MACHINE(2, 9)
2996
2997static void virt_machine_2_8_options(MachineClass *mc)
2998{
2999 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3000
3001 virt_machine_2_9_options(mc);
3002 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len);
3003
3004
3005
3006 vmc->claim_edge_triggered_timers = true;
3007}
3008DEFINE_VIRT_MACHINE(2, 8)
3009
3010static void virt_machine_2_7_options(MachineClass *mc)
3011{
3012 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3013
3014 virt_machine_2_8_options(mc);
3015 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len);
3016
3017 vmc->no_its = true;
3018
3019 mc->minimum_page_bits = 0;
3020}
3021DEFINE_VIRT_MACHINE(2, 7)
3022
3023static void virt_machine_2_6_options(MachineClass *mc)
3024{
3025 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3026
3027 virt_machine_2_7_options(mc);
3028 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len);
3029 vmc->disallow_affinity_adjustment = true;
3030
3031 vmc->no_pmu = true;
3032}
3033DEFINE_VIRT_MACHINE(2, 6)
3034