1/* 2 * ATI VGA register definitions 3 * 4 * based on: 5 * linux/include/video/aty128.h 6 * Register definitions for ATI Rage128 boards 7 * Anthony Tong <atong@uiuc.edu>, 1999 8 * Brad Douglas <brad@neruo.com>, 2000 9 * 10 * and linux/include/video/radeon.h 11 * 12 * This work is licensed under the GNU GPL license version 2. 13 */ 14 15/* 16 * Register mapping: 17 * 0x0000-0x00ff Misc regs also accessible via io and mmio space 18 * 0x0100-0x0eff Misc regs only accessible via mmio 19 * 0x0f00-0x0fff Read-only copy of PCI config regs 20 * 0x1000-0x13ff Concurrent Command Engine (CCE) regs 21 * 0x1400-0x1fff GUI (drawing engine) regs 22 */ 23 24#ifndef ATI_REGS_H 25#define ATI_REGS_H 26 27#undef DEFAULT_PITCH /* needed for mingw builds */ 28 29#define MM_INDEX 0x0000 30#define MM_DATA 0x0004 31#define CLOCK_CNTL_INDEX 0x0008 32#define CLOCK_CNTL_DATA 0x000c 33#define BIOS_0_SCRATCH 0x0010 34#define BUS_CNTL 0x0030 35#define BUS_CNTL1 0x0034 36#define GEN_INT_CNTL 0x0040 37#define GEN_INT_STATUS 0x0044 38#define CRTC_GEN_CNTL 0x0050 39#define CRTC_EXT_CNTL 0x0054 40#define DAC_CNTL 0x0058 41#define GPIO_VGA_DDC 0x0060 42#define GPIO_DVI_DDC 0x0064 43#define GPIO_MONID 0x0068 44#define I2C_CNTL_1 0x0094 45#define AMCGPIO_MASK_MIR 0x009c 46#define AMCGPIO_A_MIR 0x00a0 47#define AMCGPIO_Y_MIR 0x00a4 48#define AMCGPIO_EN_MIR 0x00a8 49#define PALETTE_INDEX 0x00b0 50#define PALETTE_DATA 0x00b4 51#define CNFG_CNTL 0x00e0 52#define GEN_RESET_CNTL 0x00f0 53#define CNFG_MEMSIZE 0x00f8 54#define CONFIG_APER_0_BASE 0x0100 55#define CONFIG_APER_1_BASE 0x0104 56#define CONFIG_APER_SIZE 0x0108 57#define CONFIG_REG_1_BASE 0x010c 58#define CONFIG_REG_APER_SIZE 0x0110 59#define MEM_CNTL 0x0140 60#define MC_FB_LOCATION 0x0148 61#define MC_AGP_LOCATION 0x014C 62#define MC_STATUS 0x0150 63#define MEM_SDRAM_MODE_REG 0x0158 64#define MEM_POWER_MISC 0x015c 65#define AGP_BASE 0x0170 66#define AGP_CNTL 0x0174 67#define AGP_APER_OFFSET 0x0178 68#define PCI_GART_PAGE 0x017c 69#define PC_NGUI_MODE 0x0180 70#define PC_NGUI_CTLSTAT 0x0184 71#define MPP_TB_CONFIG 0x01C0 72#define MPP_GP_CONFIG 0x01C8 73#define VIPH_CONTROL 0x01D0 74#define CRTC_H_TOTAL_DISP 0x0200 75#define CRTC_H_SYNC_STRT_WID 0x0204 76#define CRTC_V_TOTAL_DISP 0x0208 77#define CRTC_V_SYNC_STRT_WID 0x020c 78#define CRTC_VLINE_CRNT_VLINE 0x0210 79#define CRTC_CRNT_FRAME 0x0214 80#define CRTC_GUI_TRIG_VLINE 0x0218 81#define CRTC_OFFSET 0x0224 82#define CRTC_OFFSET_CNTL 0x0228 83#define CRTC_PITCH 0x022c 84#define OVR_CLR 0x0230 85#define OVR_WID_LEFT_RIGHT 0x0234 86#define OVR_WID_TOP_BOTTOM 0x0238 87#define CUR_OFFSET 0x0260 88#define CUR_HORZ_VERT_POSN 0x0264 89#define CUR_HORZ_VERT_OFF 0x0268 90#define CUR_CLR0 0x026c 91#define CUR_CLR1 0x0270 92#define LVDS_GEN_CNTL 0x02d0 93#define DDA_CONFIG 0x02e0 94#define DDA_ON_OFF 0x02e4 95#define VGA_DDA_CONFIG 0x02e8 96#define VGA_DDA_ON_OFF 0x02ec 97#define CRTC2_H_TOTAL_DISP 0x0300 98#define CRTC2_H_SYNC_STRT_WID 0x0304 99#define CRTC2_V_TOTAL_DISP 0x0308 100#define CRTC2_V_SYNC_STRT_WID 0x030c 101#define CRTC2_VLINE_CRNT_VLINE 0x0310 102#define CRTC2_CRNT_FRAME 0x0314 103#define CRTC2_GUI_TRIG_VLINE 0x0318 104#define CRTC2_OFFSET 0x0324 105#define CRTC2_OFFSET_CNTL 0x0328 106#define CRTC2_PITCH 0x032c 107#define DDA2_CONFIG 0x03e0 108#define DDA2_ON_OFF 0x03e4 109#define CRTC2_GEN_CNTL 0x03f8 110#define CRTC2_STATUS 0x03fc 111#define OV0_SCALE_CNTL 0x0420 112#define SUBPIC_CNTL 0x0540 113#define PM4_BUFFER_OFFSET 0x0700 114#define PM4_BUFFER_CNTL 0x0704 115#define PM4_BUFFER_WM_CNTL 0x0708 116#define PM4_BUFFER_DL_RPTR_ADDR 0x070c 117#define PM4_BUFFER_DL_RPTR 0x0710 118#define PM4_BUFFER_DL_WPTR 0x0714 119#define PM4_VC_FPU_SETUP 0x071c 120#define PM4_FPU_CNTL 0x0720 121#define PM4_VC_FORMAT 0x0724 122#define PM4_VC_CNTL 0x0728 123#define PM4_VC_I01 0x072c 124#define PM4_VC_VLOFF 0x0730 125#define PM4_VC_VLSIZE 0x0734 126#define PM4_IW_INDOFF 0x0738 127#define PM4_IW_INDSIZE 0x073c 128#define PM4_FPU_FPX0 0x0740 129#define PM4_FPU_FPY0 0x0744 130#define PM4_FPU_FPX1 0x0748 131#define PM4_FPU_FPY1 0x074c 132#define PM4_FPU_FPX2 0x0750 133#define PM4_FPU_FPY2 0x0754 134#define PM4_FPU_FPY3 0x0758 135#define PM4_FPU_FPY4 0x075c 136#define PM4_FPU_FPY5 0x0760 137#define PM4_FPU_FPY6 0x0764 138#define PM4_FPU_FPR 0x0768 139#define PM4_FPU_FPG 0x076c 140#define PM4_FPU_FPB 0x0770 141#define PM4_FPU_FPA 0x0774 142#define PM4_FPU_INTXY0 0x0780 143#define PM4_FPU_INTXY1 0x0784 144#define PM4_FPU_INTXY2 0x0788 145#define PM4_FPU_INTARGB 0x078c 146#define PM4_FPU_FPTWICEAREA 0x0790 147#define PM4_FPU_DMAJOR01 0x0794 148#define PM4_FPU_DMAJOR12 0x0798 149#define PM4_FPU_DMAJOR02 0x079c 150#define PM4_FPU_STAT 0x07a0 151#define PM4_STAT 0x07b8 152#define PM4_TEST_CNTL 0x07d0 153#define PM4_MICROCODE_ADDR 0x07d4 154#define PM4_MICROCODE_RADDR 0x07d8 155#define PM4_MICROCODE_DATAH 0x07dc 156#define PM4_MICROCODE_DATAL 0x07e0 157#define PM4_CMDFIFO_ADDR 0x07e4 158#define PM4_CMDFIFO_DATAH 0x07e8 159#define PM4_CMDFIFO_DATAL 0x07ec 160#define PM4_BUFFER_ADDR 0x07f0 161#define PM4_BUFFER_DATAH 0x07f4 162#define PM4_BUFFER_DATAL 0x07f8 163#define PM4_MICRO_CNTL 0x07fc 164#define CAP0_TRIG_CNTL 0x0950 165#define CAP1_TRIG_CNTL 0x09c0 166 167#define RBBM_STATUS 0x0e40 168 169/* 170 * GUI Block Memory Mapped Registers 171 * These registers are FIFOed. 172 */ 173#define PM4_FIFO_DATA_EVEN 0x1000 174#define PM4_FIFO_DATA_ODD 0x1004 175 176#define DST_OFFSET 0x1404 177#define DST_PITCH 0x1408 178#define DST_WIDTH 0x140c 179#define DST_HEIGHT 0x1410 180#define SRC_X 0x1414 181#define SRC_Y 0x1418 182#define DST_X 0x141c 183#define DST_Y 0x1420 184#define SRC_PITCH_OFFSET 0x1428 185#define DST_PITCH_OFFSET 0x142c 186#define SRC_Y_X 0x1434 187#define DST_Y_X 0x1438 188#define DST_HEIGHT_WIDTH 0x143c 189#define DP_GUI_MASTER_CNTL 0x146c 190#define BRUSH_SCALE 0x1470 191#define BRUSH_Y_X 0x1474 192#define DP_BRUSH_BKGD_CLR 0x1478 193#define DP_BRUSH_FRGD_CLR 0x147c 194#define DST_WIDTH_X 0x1588 195#define DST_HEIGHT_WIDTH_8 0x158c 196#define SRC_X_Y 0x1590 197#define DST_X_Y 0x1594 198#define DST_WIDTH_HEIGHT 0x1598 199#define DST_WIDTH_X_INCY 0x159c 200#define DST_HEIGHT_Y 0x15a0 201#define DST_X_SUB 0x15a4 202#define DST_Y_SUB 0x15a8 203#define SRC_OFFSET 0x15ac 204#define SRC_PITCH 0x15b0 205#define DST_HEIGHT_WIDTH_BW 0x15b4 206#define CLR_CMP_CNTL 0x15c0 207#define CLR_CMP_CLR_SRC 0x15c4 208#define CLR_CMP_CLR_DST 0x15c8 209#define CLR_CMP_MASK 0x15cc 210#define DP_SRC_FRGD_CLR 0x15d8 211#define DP_SRC_BKGD_CLR 0x15dc 212#define DST_BRES_ERR 0x1628 213#define DST_BRES_INC 0x162c 214#define DST_BRES_DEC 0x1630 215#define DST_BRES_LNTH 0x1634 216#define DST_BRES_LNTH_SUB 0x1638 217#define SC_LEFT 0x1640 218#define SC_RIGHT 0x1644 219#define SC_TOP 0x1648 220#define SC_BOTTOM 0x164c 221#define SRC_SC_RIGHT 0x1654 222#define SRC_SC_BOTTOM 0x165c 223#define GUI_DEBUG0 0x16a0 224#define GUI_DEBUG1 0x16a4 225#define GUI_TIMEOUT 0x16b0 226#define GUI_TIMEOUT0 0x16b4 227#define GUI_TIMEOUT1 0x16b8 228#define GUI_PROBE 0x16bc 229#define DP_CNTL 0x16c0 230#define DP_DATATYPE 0x16c4 231#define DP_MIX 0x16c8 232#define DP_WRITE_MASK 0x16cc 233#define DP_CNTL_XDIR_YDIR_YMAJOR 0x16d0 234#define DEFAULT_OFFSET 0x16e0 235#define DEFAULT_PITCH 0x16e4 236#define DEFAULT_SC_BOTTOM_RIGHT 0x16e8 237#define SC_TOP_LEFT 0x16ec 238#define SC_BOTTOM_RIGHT 0x16f0 239#define SRC_SC_BOTTOM_RIGHT 0x16f4 240#define DST_TILE 0x1700 241#define WAIT_UNTIL 0x1720 242#define CACHE_CNTL 0x1724 243#define GUI_STAT 0x1740 244#define PC_GUI_MODE 0x1744 245#define PC_GUI_CTLSTAT 0x1748 246#define PC_DEBUG_MODE 0x1760 247#define BRES_DST_ERR_DEC 0x1780 248#define TRAIL_BRES_T12_ERR_DEC 0x1784 249#define TRAIL_BRES_T12_INC 0x1788 250#define DP_T12_CNTL 0x178c 251#define DST_BRES_T1_LNTH 0x1790 252#define DST_BRES_T2_LNTH 0x1794 253#define SCALE_SRC_HEIGHT_WIDTH 0x1994 254#define SCALE_OFFSET_0 0x1998 255#define SCALE_PITCH 0x199c 256#define SCALE_X_INC 0x19a0 257#define SCALE_Y_INC 0x19a4 258#define SCALE_HACC 0x19a8 259#define SCALE_VACC 0x19ac 260#define SCALE_DST_X_Y 0x19b0 261#define SCALE_DST_HEIGHT_WIDTH 0x19b4 262#define SCALE_3D_CNTL 0x1a00 263#define SCALE_3D_DATATYPE 0x1a20 264#define SETUP_CNTL 0x1bc4 265#define SOLID_COLOR 0x1bc8 266#define WINDOW_XY_OFFSET 0x1bcc 267#define DRAW_LINE_POINT 0x1bd0 268#define SETUP_CNTL_PM4 0x1bd4 269#define DST_PITCH_OFFSET_C 0x1c80 270#define DP_GUI_MASTER_CNTL_C 0x1c84 271#define SC_TOP_LEFT_C 0x1c88 272#define SC_BOTTOM_RIGHT_C 0x1c8c 273 274#define CLR_CMP_MASK_3D 0x1A28 275#define MISC_3D_STATE_CNTL_REG 0x1CA0 276#define MC_SRC1_CNTL 0x19D8 277#define TEX_CNTL 0x1800 278 279/* CONSTANTS */ 280#define GUI_ACTIVE 0x80000000 281#define ENGINE_IDLE 0x0 282 283#define PLL_WR_EN 0x00000080 284 285#define CLK_PIN_CNTL 0x01 286#define PPLL_CNTL 0x02 287#define PPLL_REF_DIV 0x03 288#define PPLL_DIV_0 0x04 289#define PPLL_DIV_1 0x05 290#define PPLL_DIV_2 0x06 291#define PPLL_DIV_3 0x07 292#define VCLK_ECP_CNTL 0x08 293#define HTOTAL_CNTL 0x09 294#define X_MPLL_REF_FB_DIV 0x0a 295#define XPLL_CNTL 0x0b 296#define XDLL_CNTL 0x0c 297#define XCLK_CNTL 0x0d 298#define MPLL_CNTL 0x0e 299#define MCLK_CNTL 0x0f 300#define AGP_PLL_CNTL 0x10 301#define FCP_CNTL 0x12 302#define PLL_TEST_CNTL 0x13 303#define P2PLL_CNTL 0x2a 304#define P2PLL_REF_DIV 0x2b 305#define P2PLL_DIV_0 0x2b 306#define POWER_MANAGEMENT 0x2f 307 308#define PPLL_RESET 0x00000001 309#define PPLL_ATOMIC_UPDATE_EN 0x00010000 310#define PPLL_VGA_ATOMIC_UPDATE_EN 0x00020000 311#define PPLL_REF_DIV_MASK 0x000003FF 312#define PPLL_FB3_DIV_MASK 0x000007FF 313#define PPLL_POST3_DIV_MASK 0x00070000 314#define PPLL_ATOMIC_UPDATE_R 0x00008000 315#define PPLL_ATOMIC_UPDATE_W 0x00008000 316#define MEM_CFG_TYPE_MASK 0x00000003 317#define XCLK_SRC_SEL_MASK 0x00000007 318#define XPLL_FB_DIV_MASK 0x0000FF00 319#define X_MPLL_REF_DIV_MASK 0x000000FF 320 321/* GEN_INT_CNTL) */ 322#define CRTC_VBLANK_INT 0x00000001 323#define CRTC_VLINE_INT 0x00000002 324#define CRTC_VSYNC_INT 0x00000004 325 326/* Config control values (CONFIG_CNTL) */ 327#define APER_0_ENDIAN 0x00000003 328#define APER_1_ENDIAN 0x0000000c 329#define CFG_VGA_IO_DIS 0x00000400 330 331/* CRTC control values (CRTC_GEN_CNTL) */ 332#define CRTC_CSYNC_EN 0x00000010 333 334#define CRTC2_DBL_SCAN_EN 0x00000001 335#define CRTC2_DISPLAY_DIS 0x00800000 336#define CRTC2_FIFO_EXTSENSE 0x00200000 337#define CRTC2_ICON_EN 0x00100000 338#define CRTC2_CUR_EN 0x00010000 339#define CRTC2_EXT_DISP_EN 0x01000000 340#define CRTC2_EN 0x02000000 341#define CRTC2_DISP_REQ_EN_B 0x04000000 342 343#define CRTC_PIX_WIDTH_MASK 0x00000700 344#define CRTC_PIX_WIDTH_4BPP 0x00000100 345#define CRTC_PIX_WIDTH_8BPP 0x00000200 346#define CRTC_PIX_WIDTH_15BPP 0x00000300 347#define CRTC_PIX_WIDTH_16BPP 0x00000400 348#define CRTC_PIX_WIDTH_24BPP 0x00000500 349#define CRTC_PIX_WIDTH_32BPP 0x00000600 350 351/* DAC_CNTL bit constants */ 352#define DAC_8BIT_EN 0x00000100 353#define DAC_MASK 0xFF000000 354#define DAC_BLANKING 0x00000004 355#define DAC_RANGE_CNTL 0x00000003 356#define DAC_CLK_SEL 0x00000010 357#define DAC_PALETTE_ACCESS_CNTL 0x00000020 358#define DAC_PALETTE2_SNOOP_EN 0x00000040 359#define DAC_PDWN 0x00008000 360 361/* CRTC_EXT_CNTL */ 362#define CRT_CRTC_DISPLAY_DIS 0x00000400 363#define CRT_CRTC_ON 0x00008000 364 365/* GEN_RESET_CNTL bit constants */ 366#define SOFT_RESET_GUI 0x00000001 367#define SOFT_RESET_VCLK 0x00000100 368#define SOFT_RESET_PCLK 0x00000200 369#define SOFT_RESET_ECP 0x00000400 370#define SOFT_RESET_DISPENG_XCLK 0x00000800 371 372/* PC_GUI_CTLSTAT bit constants */ 373#define PC_BUSY_INIT 0x10000000 374#define PC_BUSY_GUI 0x20000000 375#define PC_BUSY_NGUI 0x40000000 376#define PC_BUSY 0x80000000 377 378#define BUS_MASTER_DIS 0x00000040 379#define PM4_BUFFER_CNTL_NONPM4 0x00000000 380 381/* DP_DATATYPE bit constants */ 382#define DST_8BPP 0x00000002 383#define DST_15BPP 0x00000003 384#define DST_16BPP 0x00000004 385#define DST_24BPP 0x00000005 386#define DST_32BPP 0x00000006 387 388#define BRUSH_SOLIDCOLOR 0x00000d00 389 390/* DP_GUI_MASTER_CNTL bit constants */ 391#define GMC_SRC_PITCH_OFFSET_CNTL 0x00000001 392#define GMC_DST_PITCH_OFFSET_CNTL 0x00000002 393#define GMC_SRC_CLIP_DEFAULT 0x00000000 394#define GMC_DST_CLIP_DEFAULT 0x00000000 395#define GMC_BRUSH_SOLIDCOLOR 0x000000d0 396#define GMC_SRC_DSTCOLOR 0x00003000 397#define GMC_BYTE_ORDER_MSB_TO_LSB 0x00000000 398#define GMC_DP_SRC_RECT 0x02000000 399#define GMC_3D_FCN_EN_CLR 0x00000000 400#define GMC_AUX_CLIP_CLEAR 0x20000000 401#define GMC_DST_CLR_CMP_FCN_CLEAR 0x10000000 402#define GMC_WRITE_MASK_SET 0x40000000 403#define GMC_DP_CONVERSION_TEMP_6500 0x00000000 404 405/* DP_GUI_MASTER_CNTL ROP3 named constants */ 406#define GMC_ROP3_MASK 0x00ff0000 407#define ROP3_BLACKNESS 0x00000000 408#define ROP3_SRCCOPY 0x00cc0000 409#define ROP3_PATCOPY 0x00f00000 410#define ROP3_WHITENESS 0x00ff0000 411 412#define SRC_DSTCOLOR 0x00030000 413 414/* DP_CNTL bit constants */ 415#define DST_X_RIGHT_TO_LEFT 0x00000000 416#define DST_X_LEFT_TO_RIGHT 0x00000001 417#define DST_Y_BOTTOM_TO_TOP 0x00000000 418#define DST_Y_TOP_TO_BOTTOM 0x00000002 419#define DST_X_MAJOR 0x00000000 420#define DST_Y_MAJOR 0x00000004 421#define DST_X_TILE 0x00000008 422#define DST_Y_TILE 0x00000010 423#define DST_LAST_PEL 0x00000020 424#define DST_TRAIL_X_RIGHT_TO_LEFT 0x00000000 425#define DST_TRAIL_X_LEFT_TO_RIGHT 0x00000040 426#define DST_TRAP_FILL_RIGHT_TO_LEFT 0x00000000 427#define DST_TRAP_FILL_LEFT_TO_RIGHT 0x00000080 428#define DST_BRES_SIGN 0x00000100 429#define DST_HOST_BIG_ENDIAN_EN 0x00000200 430#define DST_POLYLINE_NONLAST 0x00008000 431#define DST_RASTER_STALL 0x00010000 432#define DST_POLY_EDGE 0x00040000 433 434/* DP_MIX bit constants */ 435#define DP_SRC_RECT 0x00000200 436#define DP_SRC_HOST 0x00000300 437#define DP_SRC_HOST_BYTEALIGN 0x00000400 438 439/* LVDS_GEN_CNTL constants */ 440#define LVDS_BL_MOD_LEVEL_MASK 0x0000ff00 441#define LVDS_BL_MOD_LEVEL_SHIFT 8 442#define LVDS_BL_MOD_EN 0x00010000 443#define LVDS_DIGION 0x00040000 444#define LVDS_BLON 0x00080000 445#define LVDS_ON 0x00000001 446#define LVDS_DISPLAY_DIS 0x00000002 447#define LVDS_PANEL_TYPE_2PIX_PER_CLK 0x00000004 448#define LVDS_PANEL_24BITS_TFT 0x00000008 449#define LVDS_FRAME_MOD_NO 0x00000000 450#define LVDS_FRAME_MOD_2_LEVELS 0x00000010 451#define LVDS_FRAME_MOD_4_LEVELS 0x00000020 452#define LVDS_RST_FM 0x00000040 453#define LVDS_EN 0x00000080 454 455/* CRTC2_GEN_CNTL constants */ 456#define CRTC2_EN 0x02000000 457 458/* POWER_MANAGEMENT constants */ 459#define PWR_MGT_ON 0x00000001 460#define PWR_MGT_MODE_MASK 0x00000006 461#define PWR_MGT_MODE_PIN 0x00000000 462#define PWR_MGT_MODE_REGISTER 0x00000002 463#define PWR_MGT_MODE_TIMER 0x00000004 464#define PWR_MGT_MODE_PCI 0x00000006 465#define PWR_MGT_AUTO_PWR_UP_EN 0x00000008 466#define PWR_MGT_ACTIVITY_PIN_ON 0x00000010 467#define PWR_MGT_STANDBY_POL 0x00000020 468#define PWR_MGT_SUSPEND_POL 0x00000040 469#define PWR_MGT_SELF_REFRESH 0x00000080 470#define PWR_MGT_ACTIVITY_PIN_EN 0x00000100 471#define PWR_MGT_KEYBD_SNOOP 0x00000200 472#define PWR_MGT_TRISTATE_MEM_EN 0x00000800 473#define PWR_MGT_SELW4MS 0x00001000 474#define PWR_MGT_SLOWDOWN_MCLK 0x00002000 475 476#define PMI_PMSCR_REG 0x60 477 478/* used by ATI bug fix for hardware ROM */ 479#define RAGE128_MPP_TB_CONFIG 0x01c0 480 481#endif /* ATI_REGS_H */ 482