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25#include "qemu/osdep.h"
26#include "qapi/error.h"
27#include "qemu/error-report.h"
28#include "qemu/log.h"
29#include "qemu/module.h"
30#include "hw/display/xlnx_dp.h"
31#include "hw/irq.h"
32#include "migration/vmstate.h"
33
34#ifndef DEBUG_DP
35#define DEBUG_DP 0
36#endif
37
38#define DPRINTF(fmt, ...) do { \
39 if (DEBUG_DP) { \
40 qemu_log("xlnx_dp: " fmt , ## __VA_ARGS__); \
41 } \
42} while (0)
43
44
45
46
47#define DP_LINK_BW_SET (0x0000 >> 2)
48#define DP_LANE_COUNT_SET (0x0004 >> 2)
49#define DP_ENHANCED_FRAME_EN (0x0008 >> 2)
50#define DP_TRAINING_PATTERN_SET (0x000C >> 2)
51#define DP_LINK_QUAL_PATTERN_SET (0x0010 >> 2)
52#define DP_SCRAMBLING_DISABLE (0x0014 >> 2)
53#define DP_DOWNSPREAD_CTRL (0x0018 >> 2)
54#define DP_SOFTWARE_RESET (0x001C >> 2)
55#define DP_TRANSMITTER_ENABLE (0x0080 >> 2)
56#define DP_MAIN_STREAM_ENABLE (0x0084 >> 2)
57#define DP_FORCE_SCRAMBLER_RESET (0x00C0 >> 2)
58#define DP_VERSION_REGISTER (0x00F8 >> 2)
59#define DP_CORE_ID (0x00FC >> 2)
60
61#define DP_AUX_COMMAND_REGISTER (0x0100 >> 2)
62#define AUX_ADDR_ONLY_MASK (0x1000)
63#define AUX_COMMAND_MASK (0x0F00)
64#define AUX_COMMAND_SHIFT (8)
65#define AUX_COMMAND_NBYTES (0x000F)
66
67#define DP_AUX_WRITE_FIFO (0x0104 >> 2)
68#define DP_AUX_ADDRESS (0x0108 >> 2)
69#define DP_AUX_CLOCK_DIVIDER (0x010C >> 2)
70#define DP_TX_USER_FIFO_OVERFLOW (0x0110 >> 2)
71#define DP_INTERRUPT_SIGNAL_STATE (0x0130 >> 2)
72#define DP_AUX_REPLY_DATA (0x0134 >> 2)
73#define DP_AUX_REPLY_CODE (0x0138 >> 2)
74#define DP_AUX_REPLY_COUNT (0x013C >> 2)
75#define DP_REPLY_DATA_COUNT (0x0148 >> 2)
76#define DP_REPLY_STATUS (0x014C >> 2)
77#define DP_HPD_DURATION (0x0150 >> 2)
78#define DP_MAIN_STREAM_HTOTAL (0x0180 >> 2)
79#define DP_MAIN_STREAM_VTOTAL (0x0184 >> 2)
80#define DP_MAIN_STREAM_POLARITY (0x0188 >> 2)
81#define DP_MAIN_STREAM_HSWIDTH (0x018C >> 2)
82#define DP_MAIN_STREAM_VSWIDTH (0x0190 >> 2)
83#define DP_MAIN_STREAM_HRES (0x0194 >> 2)
84#define DP_MAIN_STREAM_VRES (0x0198 >> 2)
85#define DP_MAIN_STREAM_HSTART (0x019C >> 2)
86#define DP_MAIN_STREAM_VSTART (0x01A0 >> 2)
87#define DP_MAIN_STREAM_MISC0 (0x01A4 >> 2)
88#define DP_MAIN_STREAM_MISC1 (0x01A8 >> 2)
89#define DP_MAIN_STREAM_M_VID (0x01AC >> 2)
90#define DP_MSA_TRANSFER_UNIT_SIZE (0x01B0 >> 2)
91#define DP_MAIN_STREAM_N_VID (0x01B4 >> 2)
92#define DP_USER_DATA_COUNT_PER_LANE (0x01BC >> 2)
93#define DP_MIN_BYTES_PER_TU (0x01C4 >> 2)
94#define DP_FRAC_BYTES_PER_TU (0x01C8 >> 2)
95#define DP_INIT_WAIT (0x01CC >> 2)
96#define DP_PHY_RESET (0x0200 >> 2)
97#define DP_PHY_VOLTAGE_DIFF_LANE_0 (0x0220 >> 2)
98#define DP_PHY_VOLTAGE_DIFF_LANE_1 (0x0224 >> 2)
99#define DP_TRANSMIT_PRBS7 (0x0230 >> 2)
100#define DP_PHY_CLOCK_SELECT (0x0234 >> 2)
101#define DP_TX_PHY_POWER_DOWN (0x0238 >> 2)
102#define DP_PHY_PRECURSOR_LANE_0 (0x023C >> 2)
103#define DP_PHY_PRECURSOR_LANE_1 (0x0240 >> 2)
104#define DP_PHY_POSTCURSOR_LANE_0 (0x024C >> 2)
105#define DP_PHY_POSTCURSOR_LANE_1 (0x0250 >> 2)
106#define DP_PHY_STATUS (0x0280 >> 2)
107
108#define DP_TX_AUDIO_CONTROL (0x0300 >> 2)
109#define DP_TX_AUD_CTRL (1)
110
111#define DP_TX_AUDIO_CHANNELS (0x0304 >> 2)
112#define DP_TX_AUDIO_INFO_DATA(n) ((0x0308 + 4 * n) >> 2)
113#define DP_TX_M_AUD (0x0328 >> 2)
114#define DP_TX_N_AUD (0x032C >> 2)
115#define DP_TX_AUDIO_EXT_DATA(n) ((0x0330 + 4 * n) >> 2)
116#define DP_INT_STATUS (0x03A0 >> 2)
117#define DP_INT_MASK (0x03A4 >> 2)
118#define DP_INT_EN (0x03A8 >> 2)
119#define DP_INT_DS (0x03AC >> 2)
120
121
122
123
124#define V_BLEND_OFFSET (0xA000)
125#define V_BLEND_BG_CLR_0 (0x0000 >> 2)
126#define V_BLEND_BG_CLR_1 (0x0004 >> 2)
127#define V_BLEND_BG_CLR_2 (0x0008 >> 2)
128#define V_BLEND_SET_GLOBAL_ALPHA_REG (0x000C >> 2)
129#define V_BLEND_OUTPUT_VID_FORMAT (0x0014 >> 2)
130#define V_BLEND_LAYER0_CONTROL (0x0018 >> 2)
131#define V_BLEND_LAYER1_CONTROL (0x001C >> 2)
132
133#define V_BLEND_RGB2YCBCR_COEFF(n) ((0x0020 + 4 * n) >> 2)
134#define V_BLEND_IN1CSC_COEFF(n) ((0x0044 + 4 * n) >> 2)
135
136#define V_BLEND_LUMA_IN1CSC_OFFSET (0x0068 >> 2)
137#define V_BLEND_CR_IN1CSC_OFFSET (0x006C >> 2)
138#define V_BLEND_CB_IN1CSC_OFFSET (0x0070 >> 2)
139#define V_BLEND_LUMA_OUTCSC_OFFSET (0x0074 >> 2)
140#define V_BLEND_CR_OUTCSC_OFFSET (0x0078 >> 2)
141#define V_BLEND_CB_OUTCSC_OFFSET (0x007C >> 2)
142
143#define V_BLEND_IN2CSC_COEFF(n) ((0x0080 + 4 * n) >> 2)
144
145#define V_BLEND_LUMA_IN2CSC_OFFSET (0x00A4 >> 2)
146#define V_BLEND_CR_IN2CSC_OFFSET (0x00A8 >> 2)
147#define V_BLEND_CB_IN2CSC_OFFSET (0x00AC >> 2)
148#define V_BLEND_CHROMA_KEY_ENABLE (0x01D0 >> 2)
149#define V_BLEND_CHROMA_KEY_COMP1 (0x01D4 >> 2)
150#define V_BLEND_CHROMA_KEY_COMP2 (0x01D8 >> 2)
151#define V_BLEND_CHROMA_KEY_COMP3 (0x01DC >> 2)
152
153
154
155
156#define AV_BUF_MANAGER_OFFSET (0xB000)
157#define AV_BUF_FORMAT (0x0000 >> 2)
158#define AV_BUF_NON_LIVE_LATENCY (0x0008 >> 2)
159#define AV_CHBUF0 (0x0010 >> 2)
160#define AV_CHBUF1 (0x0014 >> 2)
161#define AV_CHBUF2 (0x0018 >> 2)
162#define AV_CHBUF3 (0x001C >> 2)
163#define AV_CHBUF4 (0x0020 >> 2)
164#define AV_CHBUF5 (0x0024 >> 2)
165#define AV_BUF_STC_CONTROL (0x002C >> 2)
166#define AV_BUF_STC_INIT_VALUE0 (0x0030 >> 2)
167#define AV_BUF_STC_INIT_VALUE1 (0x0034 >> 2)
168#define AV_BUF_STC_ADJ (0x0038 >> 2)
169#define AV_BUF_STC_VIDEO_VSYNC_TS_REG0 (0x003C >> 2)
170#define AV_BUF_STC_VIDEO_VSYNC_TS_REG1 (0x0040 >> 2)
171#define AV_BUF_STC_EXT_VSYNC_TS_REG0 (0x0044 >> 2)
172#define AV_BUF_STC_EXT_VSYNC_TS_REG1 (0x0048 >> 2)
173#define AV_BUF_STC_CUSTOM_EVENT_TS_REG0 (0x004C >> 2)
174#define AV_BUF_STC_CUSTOM_EVENT_TS_REG1 (0x0050 >> 2)
175#define AV_BUF_STC_CUSTOM_EVENT2_TS_REG0 (0x0054 >> 2)
176#define AV_BUF_STC_CUSTOM_EVENT2_TS_REG1 (0x0058 >> 2)
177#define AV_BUF_STC_SNAPSHOT0 (0x0060 >> 2)
178#define AV_BUF_STC_SNAPSHOT1 (0x0064 >> 2)
179#define AV_BUF_OUTPUT_AUDIO_VIDEO_SELECT (0x0070 >> 2)
180#define AV_BUF_HCOUNT_VCOUNT_INT0 (0x0074 >> 2)
181#define AV_BUF_HCOUNT_VCOUNT_INT1 (0x0078 >> 2)
182#define AV_BUF_DITHER_CONFIG (0x007C >> 2)
183#define AV_BUF_DITHER_CONFIG_MAX (0x008C >> 2)
184#define AV_BUF_DITHER_CONFIG_MIN (0x0090 >> 2)
185#define AV_BUF_PATTERN_GEN_SELECT (0x0100 >> 2)
186#define AV_BUF_AUD_VID_CLK_SOURCE (0x0120 >> 2)
187#define AV_BUF_SRST_REG (0x0124 >> 2)
188#define AV_BUF_AUDIO_RDY_INTERVAL (0x0128 >> 2)
189#define AV_BUF_AUDIO_CH_CONFIG (0x012C >> 2)
190
191#define AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(n)((0x0200 + 4 * n) >> 2)
192
193#define AV_BUF_VIDEO_COMP_SCALE_FACTOR(n) ((0x020C + 4 * n) >> 2)
194
195#define AV_BUF_LIVE_VIDEO_COMP_SF(n) ((0x0218 + 4 * n) >> 2)
196
197#define AV_BUF_LIVE_VID_CONFIG (0x0224 >> 2)
198
199#define AV_BUF_LIVE_GFX_COMP_SF(n) ((0x0228 + 4 * n) >> 2)
200
201#define AV_BUF_LIVE_GFX_CONFIG (0x0234 >> 2)
202
203#define AUDIO_MIXER_REGISTER_OFFSET (0xC000)
204#define AUDIO_MIXER_VOLUME_CONTROL (0x0000 >> 2)
205#define AUDIO_MIXER_META_DATA (0x0004 >> 2)
206#define AUD_CH_STATUS_REG(n) ((0x0008 + 4 * n) >> 2)
207#define AUD_CH_A_DATA_REG(n) ((0x0020 + 4 * n) >> 2)
208#define AUD_CH_B_DATA_REG(n) ((0x0038 + 4 * n) >> 2)
209
210#define DP_AUDIO_DMA_CHANNEL(n) (4 + n)
211#define DP_GRAPHIC_DMA_CHANNEL (3)
212#define DP_VIDEO_DMA_CHANNEL (0)
213
214enum DPGraphicFmt {
215 DP_GRAPHIC_RGBA8888 = 0 << 8,
216 DP_GRAPHIC_ABGR8888 = 1 << 8,
217 DP_GRAPHIC_RGB888 = 2 << 8,
218 DP_GRAPHIC_BGR888 = 3 << 8,
219 DP_GRAPHIC_RGBA5551 = 4 << 8,
220 DP_GRAPHIC_RGBA4444 = 5 << 8,
221 DP_GRAPHIC_RGB565 = 6 << 8,
222 DP_GRAPHIC_8BPP = 7 << 8,
223 DP_GRAPHIC_4BPP = 8 << 8,
224 DP_GRAPHIC_2BPP = 9 << 8,
225 DP_GRAPHIC_1BPP = 10 << 8,
226 DP_GRAPHIC_MASK = 0xF << 8
227};
228
229enum DPVideoFmt {
230 DP_NL_VID_CB_Y0_CR_Y1 = 0,
231 DP_NL_VID_CR_Y0_CB_Y1 = 1,
232 DP_NL_VID_Y0_CR_Y1_CB = 2,
233 DP_NL_VID_Y0_CB_Y1_CR = 3,
234 DP_NL_VID_YV16 = 4,
235 DP_NL_VID_YV24 = 5,
236 DP_NL_VID_YV16CL = 6,
237 DP_NL_VID_MONO = 7,
238 DP_NL_VID_YV16CL2 = 8,
239 DP_NL_VID_YUV444 = 9,
240 DP_NL_VID_RGB888 = 10,
241 DP_NL_VID_RGBA8880 = 11,
242 DP_NL_VID_RGB888_10BPC = 12,
243 DP_NL_VID_YUV444_10BPC = 13,
244 DP_NL_VID_YV16CL2_10BPC = 14,
245 DP_NL_VID_YV16CL_10BPC = 15,
246 DP_NL_VID_YV16_10BPC = 16,
247 DP_NL_VID_YV24_10BPC = 17,
248 DP_NL_VID_Y_ONLY_10BPC = 18,
249 DP_NL_VID_YV16_420 = 19,
250 DP_NL_VID_YV16CL_420 = 20,
251 DP_NL_VID_YV16CL2_420 = 21,
252 DP_NL_VID_YV16_420_10BPC = 22,
253 DP_NL_VID_YV16CL_420_10BPC = 23,
254 DP_NL_VID_YV16CL2_420_10BPC = 24,
255 DP_NL_VID_FMT_MASK = 0x1F
256};
257
258typedef enum DPGraphicFmt DPGraphicFmt;
259typedef enum DPVideoFmt DPVideoFmt;
260
261static const VMStateDescription vmstate_dp = {
262 .name = TYPE_XLNX_DP,
263 .version_id = 1,
264 .fields = (VMStateField[]){
265 VMSTATE_UINT32_ARRAY(core_registers, XlnxDPState,
266 DP_CORE_REG_ARRAY_SIZE),
267 VMSTATE_UINT32_ARRAY(avbufm_registers, XlnxDPState,
268 DP_AVBUF_REG_ARRAY_SIZE),
269 VMSTATE_UINT32_ARRAY(vblend_registers, XlnxDPState,
270 DP_VBLEND_REG_ARRAY_SIZE),
271 VMSTATE_UINT32_ARRAY(audio_registers, XlnxDPState,
272 DP_AUDIO_REG_ARRAY_SIZE),
273 VMSTATE_END_OF_LIST()
274 }
275};
276
277static void xlnx_dp_update_irq(XlnxDPState *s);
278
279static uint64_t xlnx_dp_audio_read(void *opaque, hwaddr offset, unsigned size)
280{
281 XlnxDPState *s = XLNX_DP(opaque);
282
283 offset = offset >> 2;
284 return s->audio_registers[offset];
285}
286
287static void xlnx_dp_audio_write(void *opaque, hwaddr offset, uint64_t value,
288 unsigned size)
289{
290 XlnxDPState *s = XLNX_DP(opaque);
291
292 offset = offset >> 2;
293
294 switch (offset) {
295 case AUDIO_MIXER_META_DATA:
296 s->audio_registers[offset] = value & 0x00000001;
297 break;
298 default:
299 s->audio_registers[offset] = value;
300 break;
301 }
302}
303
304static const MemoryRegionOps audio_ops = {
305 .read = xlnx_dp_audio_read,
306 .write = xlnx_dp_audio_write,
307 .endianness = DEVICE_NATIVE_ENDIAN,
308};
309
310static inline uint32_t xlnx_dp_audio_get_volume(XlnxDPState *s,
311 uint8_t channel)
312{
313 switch (channel) {
314 case 0:
315 return extract32(s->audio_registers[AUDIO_MIXER_VOLUME_CONTROL], 0, 16);
316 case 1:
317 return extract32(s->audio_registers[AUDIO_MIXER_VOLUME_CONTROL], 16,
318 16);
319 default:
320 return 0;
321 }
322}
323
324static inline void xlnx_dp_audio_activate(XlnxDPState *s)
325{
326 bool activated = ((s->core_registers[DP_TX_AUDIO_CONTROL]
327 & DP_TX_AUD_CTRL) != 0);
328 AUD_set_active_out(s->amixer_output_stream, activated);
329 xlnx_dpdma_set_host_data_location(s->dpdma, DP_AUDIO_DMA_CHANNEL(0),
330 &s->audio_buffer_0);
331 xlnx_dpdma_set_host_data_location(s->dpdma, DP_AUDIO_DMA_CHANNEL(1),
332 &s->audio_buffer_1);
333}
334
335static inline void xlnx_dp_audio_mix_buffer(XlnxDPState *s)
336{
337
338
339
340
341
342
343
344 int i;
345
346 if ((s->audio_data_available[0]) && (xlnx_dp_audio_get_volume(s, 0))) {
347 for (i = 0; i < s->audio_data_available[0] / 2; i++) {
348 s->temp_buffer[i] = (int64_t)(s->audio_buffer_0[i])
349 * xlnx_dp_audio_get_volume(s, 0) / 8192;
350 }
351 s->byte_left = s->audio_data_available[0];
352 } else {
353 memset(s->temp_buffer, 0, s->audio_data_available[1] / 2);
354 }
355
356 if ((s->audio_data_available[1]) && (xlnx_dp_audio_get_volume(s, 1))) {
357 if ((s->audio_data_available[0] == 0)
358 || (s->audio_data_available[1] == s->audio_data_available[0])) {
359 for (i = 0; i < s->audio_data_available[1] / 2; i++) {
360 s->temp_buffer[i] += (int64_t)(s->audio_buffer_1[i])
361 * xlnx_dp_audio_get_volume(s, 1) / 8192;
362 }
363 s->byte_left = s->audio_data_available[1];
364 }
365 }
366
367 for (i = 0; i < s->byte_left / 2; i++) {
368 s->out_buffer[i] = MAX(-32767, MIN(s->temp_buffer[i], 32767));
369 }
370
371 s->data_ptr = 0;
372}
373
374static void xlnx_dp_audio_callback(void *opaque, int avail)
375{
376
377
378
379
380 XlnxDPState *s = XLNX_DP(opaque);
381 size_t written = 0;
382
383
384 if (s->byte_left == 0) {
385 s->audio_data_available[0] = xlnx_dpdma_start_operation(s->dpdma, 4,
386 true);
387 s->audio_data_available[1] = xlnx_dpdma_start_operation(s->dpdma, 5,
388 true);
389 xlnx_dp_audio_mix_buffer(s);
390 }
391
392
393 if (s->byte_left <= MAX_QEMU_BUFFER_SIZE) {
394 if (s->byte_left != 0) {
395 written = AUD_write(s->amixer_output_stream,
396 &s->out_buffer[s->data_ptr], s->byte_left);
397 } else {
398 int len_to_copy;
399
400
401
402
403 written = 0;
404 while (avail) {
405 len_to_copy = MIN(AUD_CHBUF_MAX_DEPTH, avail);
406 memset(s->out_buffer, 0, len_to_copy);
407 avail -= AUD_write(s->amixer_output_stream, s->out_buffer,
408 len_to_copy);
409 }
410 }
411 } else {
412 written = AUD_write(s->amixer_output_stream,
413 &s->out_buffer[s->data_ptr], MAX_QEMU_BUFFER_SIZE);
414 }
415 s->byte_left -= written;
416 s->data_ptr += written;
417}
418
419
420
421
422static void xlnx_dp_aux_clear_rx_fifo(XlnxDPState *s)
423{
424 fifo8_reset(&s->rx_fifo);
425}
426
427static void xlnx_dp_aux_push_rx_fifo(XlnxDPState *s, uint8_t *buf, size_t len)
428{
429 DPRINTF("Push %u data in rx_fifo\n", (unsigned)len);
430 fifo8_push_all(&s->rx_fifo, buf, len);
431}
432
433static uint8_t xlnx_dp_aux_pop_rx_fifo(XlnxDPState *s)
434{
435 uint8_t ret;
436
437 if (fifo8_is_empty(&s->rx_fifo)) {
438 qemu_log_mask(LOG_GUEST_ERROR,
439 "%s: Reading empty RX_FIFO\n",
440 __func__);
441
442
443
444
445 ret = 0;
446 } else {
447 ret = fifo8_pop(&s->rx_fifo);
448 DPRINTF("pop 0x%" PRIX8 " from rx_fifo.\n", ret);
449 }
450 return ret;
451}
452
453static void xlnx_dp_aux_clear_tx_fifo(XlnxDPState *s)
454{
455 fifo8_reset(&s->tx_fifo);
456}
457
458static void xlnx_dp_aux_push_tx_fifo(XlnxDPState *s, uint8_t *buf, size_t len)
459{
460 DPRINTF("Push %u data in tx_fifo\n", (unsigned)len);
461 fifo8_push_all(&s->tx_fifo, buf, len);
462}
463
464static uint8_t xlnx_dp_aux_pop_tx_fifo(XlnxDPState *s)
465{
466 uint8_t ret;
467
468 if (fifo8_is_empty(&s->tx_fifo)) {
469 error_report("%s: TX_FIFO underflow", __func__);
470 abort();
471 }
472 ret = fifo8_pop(&s->tx_fifo);
473 DPRINTF("pop 0x%2.2X from tx_fifo.\n", ret);
474 return ret;
475}
476
477static uint32_t xlnx_dp_aux_get_address(XlnxDPState *s)
478{
479 return s->core_registers[DP_AUX_ADDRESS];
480}
481
482
483
484
485static void xlnx_dp_aux_set_command(XlnxDPState *s, uint32_t value)
486{
487 bool address_only = (value & AUX_ADDR_ONLY_MASK) != 0;
488 AUXCommand cmd = (value & AUX_COMMAND_MASK) >> AUX_COMMAND_SHIFT;
489 uint8_t nbytes = (value & AUX_COMMAND_NBYTES) + 1;
490 uint8_t buf[16];
491 int i;
492
493
494
495
496
497 if (address_only) {
498 nbytes = 0;
499 }
500
501 switch (cmd) {
502 case READ_AUX:
503 case READ_I2C:
504 case READ_I2C_MOT:
505 s->core_registers[DP_AUX_REPLY_CODE] = aux_request(s->aux_bus, cmd,
506 xlnx_dp_aux_get_address(s),
507 nbytes, buf);
508 s->core_registers[DP_REPLY_DATA_COUNT] = nbytes;
509
510 if (s->core_registers[DP_AUX_REPLY_CODE] == AUX_I2C_ACK) {
511 xlnx_dp_aux_push_rx_fifo(s, buf, nbytes);
512 }
513 break;
514 case WRITE_AUX:
515 case WRITE_I2C:
516 case WRITE_I2C_MOT:
517 for (i = 0; i < nbytes; i++) {
518 buf[i] = xlnx_dp_aux_pop_tx_fifo(s);
519 }
520 s->core_registers[DP_AUX_REPLY_CODE] = aux_request(s->aux_bus, cmd,
521 xlnx_dp_aux_get_address(s),
522 nbytes, buf);
523 xlnx_dp_aux_clear_tx_fifo(s);
524 break;
525 case WRITE_I2C_STATUS:
526 qemu_log_mask(LOG_UNIMP, "xlnx_dp: Write i2c status not implemented\n");
527 break;
528 default:
529 error_report("%s: invalid command: %u", __func__, cmd);
530 abort();
531 }
532
533 s->core_registers[DP_INTERRUPT_SIGNAL_STATE] |= 0x04;
534}
535
536static void xlnx_dp_set_dpdma(const Object *obj, const char *name, Object *val,
537 Error **errp)
538{
539 XlnxDPState *s = XLNX_DP(obj);
540 if (s->console) {
541 DisplaySurface *surface = qemu_console_surface(s->console);
542 XlnxDPDMAState *dma = XLNX_DPDMA(val);
543 xlnx_dpdma_set_host_data_location(dma, DP_GRAPHIC_DMA_CHANNEL,
544 surface_data(surface));
545 }
546}
547
548static inline uint8_t xlnx_dp_global_alpha_value(XlnxDPState *s)
549{
550 return (s->vblend_registers[V_BLEND_SET_GLOBAL_ALPHA_REG] & 0x1FE) >> 1;
551}
552
553static inline bool xlnx_dp_global_alpha_enabled(XlnxDPState *s)
554{
555
556
557
558
559 return ((xlnx_dp_global_alpha_value(s) != 0xFF) &&
560 ((s->vblend_registers[V_BLEND_SET_GLOBAL_ALPHA_REG] & 0x01) != 0));
561}
562
563static void xlnx_dp_recreate_surface(XlnxDPState *s)
564{
565
566
567
568
569 uint16_t width = s->core_registers[DP_MAIN_STREAM_HRES];
570 uint16_t height = s->core_registers[DP_MAIN_STREAM_VRES];
571 DisplaySurface *current_console_surface = qemu_console_surface(s->console);
572
573 if ((width != 0) && (height != 0)) {
574
575
576
577
578
579 if (s->bout_plane.surface != current_console_surface) {
580 qemu_free_displaysurface(s->bout_plane.surface);
581 }
582 if (s->v_plane.surface != current_console_surface) {
583 qemu_free_displaysurface(s->v_plane.surface);
584 }
585 if (s->g_plane.surface != current_console_surface) {
586 qemu_free_displaysurface(s->g_plane.surface);
587 }
588
589 s->g_plane.surface
590 = qemu_create_displaysurface_from(width, height,
591 s->g_plane.format, 0, NULL);
592 s->v_plane.surface
593 = qemu_create_displaysurface_from(width, height,
594 s->v_plane.format, 0, NULL);
595 if (xlnx_dp_global_alpha_enabled(s)) {
596 s->bout_plane.surface =
597 qemu_create_displaysurface_from(width,
598 height,
599 s->g_plane.format,
600 0, NULL);
601 dpy_gfx_replace_surface(s->console, s->bout_plane.surface);
602 } else {
603 s->bout_plane.surface = NULL;
604 dpy_gfx_replace_surface(s->console, s->g_plane.surface);
605 }
606
607 xlnx_dpdma_set_host_data_location(s->dpdma, DP_GRAPHIC_DMA_CHANNEL,
608 surface_data(s->g_plane.surface));
609 xlnx_dpdma_set_host_data_location(s->dpdma, DP_VIDEO_DMA_CHANNEL,
610 surface_data(s->v_plane.surface));
611 }
612}
613
614
615
616
617static void xlnx_dp_change_graphic_fmt(XlnxDPState *s)
618{
619 switch (s->avbufm_registers[AV_BUF_FORMAT] & DP_GRAPHIC_MASK) {
620 case DP_GRAPHIC_RGBA8888:
621 s->g_plane.format = PIXMAN_r8g8b8a8;
622 break;
623 case DP_GRAPHIC_ABGR8888:
624 s->g_plane.format = PIXMAN_a8b8g8r8;
625 break;
626 case DP_GRAPHIC_RGB565:
627 s->g_plane.format = PIXMAN_r5g6b5;
628 break;
629 case DP_GRAPHIC_RGB888:
630 s->g_plane.format = PIXMAN_r8g8b8;
631 break;
632 case DP_GRAPHIC_BGR888:
633 s->g_plane.format = PIXMAN_b8g8r8;
634 break;
635 default:
636 error_report("%s: unsupported graphic format %u", __func__,
637 s->avbufm_registers[AV_BUF_FORMAT] & DP_GRAPHIC_MASK);
638 abort();
639 }
640
641 switch (s->avbufm_registers[AV_BUF_FORMAT] & DP_NL_VID_FMT_MASK) {
642 case 0:
643 s->v_plane.format = PIXMAN_x8b8g8r8;
644 break;
645 case DP_NL_VID_Y0_CB_Y1_CR:
646 s->v_plane.format = PIXMAN_yuy2;
647 break;
648 case DP_NL_VID_RGBA8880:
649 s->v_plane.format = PIXMAN_x8b8g8r8;
650 break;
651 default:
652 error_report("%s: unsupported video format %u", __func__,
653 s->avbufm_registers[AV_BUF_FORMAT] & DP_NL_VID_FMT_MASK);
654 abort();
655 }
656
657 xlnx_dp_recreate_surface(s);
658}
659
660static void xlnx_dp_update_irq(XlnxDPState *s)
661{
662 uint32_t flags;
663
664 flags = s->core_registers[DP_INT_STATUS] & ~s->core_registers[DP_INT_MASK];
665 DPRINTF("update IRQ value = %" PRIx32 "\n", flags);
666 qemu_set_irq(s->irq, flags != 0);
667}
668
669static uint64_t xlnx_dp_read(void *opaque, hwaddr offset, unsigned size)
670{
671 XlnxDPState *s = XLNX_DP(opaque);
672 uint64_t ret = 0;
673
674 offset = offset >> 2;
675
676 switch (offset) {
677 case DP_TX_USER_FIFO_OVERFLOW:
678
679 ret = s->core_registers[DP_TX_USER_FIFO_OVERFLOW];
680 s->core_registers[DP_TX_USER_FIFO_OVERFLOW] = 0;
681 break;
682 case DP_AUX_REPLY_DATA:
683 ret = xlnx_dp_aux_pop_rx_fifo(s);
684 break;
685 case DP_INTERRUPT_SIGNAL_STATE:
686
687
688
689
690
691 ret = s->core_registers[DP_INTERRUPT_SIGNAL_STATE];
692 s->core_registers[DP_INTERRUPT_SIGNAL_STATE] &= ~0x04;
693 break;
694 case DP_AUX_WRITE_FIFO:
695 case DP_TX_AUDIO_INFO_DATA(0):
696 case DP_TX_AUDIO_INFO_DATA(1):
697 case DP_TX_AUDIO_INFO_DATA(2):
698 case DP_TX_AUDIO_INFO_DATA(3):
699 case DP_TX_AUDIO_INFO_DATA(4):
700 case DP_TX_AUDIO_INFO_DATA(5):
701 case DP_TX_AUDIO_INFO_DATA(6):
702 case DP_TX_AUDIO_INFO_DATA(7):
703 case DP_TX_AUDIO_EXT_DATA(0):
704 case DP_TX_AUDIO_EXT_DATA(1):
705 case DP_TX_AUDIO_EXT_DATA(2):
706 case DP_TX_AUDIO_EXT_DATA(3):
707 case DP_TX_AUDIO_EXT_DATA(4):
708 case DP_TX_AUDIO_EXT_DATA(5):
709 case DP_TX_AUDIO_EXT_DATA(6):
710 case DP_TX_AUDIO_EXT_DATA(7):
711 case DP_TX_AUDIO_EXT_DATA(8):
712
713 ret = 0;
714 break;
715 default:
716 assert(offset <= (0x3AC >> 2));
717 if (offset == (0x3A8 >> 2) || offset == (0x3AC >> 2)) {
718 ret = s->core_registers[DP_INT_MASK];
719 } else {
720 ret = s->core_registers[offset];
721 }
722 break;
723 }
724
725 DPRINTF("core read @%" PRIx64 " = 0x%8.8" PRIX64 "\n", offset << 2, ret);
726 return ret;
727}
728
729static void xlnx_dp_write(void *opaque, hwaddr offset, uint64_t value,
730 unsigned size)
731{
732 XlnxDPState *s = XLNX_DP(opaque);
733
734 DPRINTF("core write @%" PRIx64 " = 0x%8.8" PRIX64 "\n", offset, value);
735
736 offset = offset >> 2;
737
738 switch (offset) {
739
740
741
742 case DP_LINK_BW_SET:
743 s->core_registers[offset] = value & 0x000000FF;
744 break;
745 case DP_LANE_COUNT_SET:
746 case DP_MAIN_STREAM_MISC0:
747 s->core_registers[offset] = value & 0x0000000F;
748 break;
749 case DP_TRAINING_PATTERN_SET:
750 case DP_LINK_QUAL_PATTERN_SET:
751 case DP_MAIN_STREAM_POLARITY:
752 case DP_PHY_VOLTAGE_DIFF_LANE_0:
753 case DP_PHY_VOLTAGE_DIFF_LANE_1:
754 s->core_registers[offset] = value & 0x00000003;
755 break;
756 case DP_ENHANCED_FRAME_EN:
757 case DP_SCRAMBLING_DISABLE:
758 case DP_DOWNSPREAD_CTRL:
759 case DP_MAIN_STREAM_ENABLE:
760 case DP_TRANSMIT_PRBS7:
761 s->core_registers[offset] = value & 0x00000001;
762 break;
763 case DP_PHY_CLOCK_SELECT:
764 s->core_registers[offset] = value & 0x00000007;
765 break;
766 case DP_SOFTWARE_RESET:
767
768
769
770
771
772
773 break;
774 case DP_TRANSMITTER_ENABLE:
775 s->core_registers[offset] = value & 0x01;
776 break;
777 case DP_FORCE_SCRAMBLER_RESET:
778
779
780
781
782
783
784 break;
785 case DP_AUX_COMMAND_REGISTER:
786 s->core_registers[offset] = value & 0x00001F0F;
787 xlnx_dp_aux_set_command(s, s->core_registers[offset]);
788 break;
789 case DP_MAIN_STREAM_HTOTAL:
790 case DP_MAIN_STREAM_VTOTAL:
791 case DP_MAIN_STREAM_HSTART:
792 case DP_MAIN_STREAM_VSTART:
793 s->core_registers[offset] = value & 0x0000FFFF;
794 break;
795 case DP_MAIN_STREAM_HRES:
796 case DP_MAIN_STREAM_VRES:
797 s->core_registers[offset] = value & 0x0000FFFF;
798 xlnx_dp_recreate_surface(s);
799 break;
800 case DP_MAIN_STREAM_HSWIDTH:
801 case DP_MAIN_STREAM_VSWIDTH:
802 s->core_registers[offset] = value & 0x00007FFF;
803 break;
804 case DP_MAIN_STREAM_MISC1:
805 s->core_registers[offset] = value & 0x00000086;
806 break;
807 case DP_MAIN_STREAM_M_VID:
808 case DP_MAIN_STREAM_N_VID:
809 s->core_registers[offset] = value & 0x00FFFFFF;
810 break;
811 case DP_MSA_TRANSFER_UNIT_SIZE:
812 case DP_MIN_BYTES_PER_TU:
813 case DP_INIT_WAIT:
814 s->core_registers[offset] = value & 0x00000007;
815 break;
816 case DP_USER_DATA_COUNT_PER_LANE:
817 s->core_registers[offset] = value & 0x0003FFFF;
818 break;
819 case DP_FRAC_BYTES_PER_TU:
820 s->core_registers[offset] = value & 0x000003FF;
821 break;
822 case DP_PHY_RESET:
823 s->core_registers[offset] = value & 0x00010003;
824
825
826
827 break;
828 case DP_TX_PHY_POWER_DOWN:
829 s->core_registers[offset] = value & 0x0000000F;
830
831
832
833 break;
834 case DP_AUX_WRITE_FIFO: {
835 uint8_t c = value;
836 xlnx_dp_aux_push_tx_fifo(s, &c, 1);
837 break;
838 }
839 case DP_AUX_CLOCK_DIVIDER:
840 break;
841 case DP_AUX_REPLY_COUNT:
842
843
844
845 s->core_registers[offset] = 0x00000000;
846 break;
847 case DP_AUX_ADDRESS:
848 s->core_registers[offset] = value & 0x000FFFFF;
849 break;
850 case DP_VERSION_REGISTER:
851 case DP_CORE_ID:
852 case DP_TX_USER_FIFO_OVERFLOW:
853 case DP_AUX_REPLY_DATA:
854 case DP_AUX_REPLY_CODE:
855 case DP_REPLY_DATA_COUNT:
856 case DP_REPLY_STATUS:
857 case DP_HPD_DURATION:
858
859
860
861 break;
862 case DP_TX_AUDIO_CONTROL:
863 s->core_registers[offset] = value & 0x00000001;
864 xlnx_dp_audio_activate(s);
865 break;
866 case DP_TX_AUDIO_CHANNELS:
867 s->core_registers[offset] = value & 0x00000007;
868 xlnx_dp_audio_activate(s);
869 break;
870 case DP_INT_STATUS:
871 s->core_registers[DP_INT_STATUS] &= ~value;
872 xlnx_dp_update_irq(s);
873 break;
874 case DP_INT_EN:
875 s->core_registers[DP_INT_MASK] &= ~value;
876 xlnx_dp_update_irq(s);
877 break;
878 case DP_INT_DS:
879 s->core_registers[DP_INT_MASK] |= ~value;
880 xlnx_dp_update_irq(s);
881 break;
882 default:
883 assert(offset <= (0x504C >> 2));
884 s->core_registers[offset] = value;
885 break;
886 }
887}
888
889static const MemoryRegionOps dp_ops = {
890 .read = xlnx_dp_read,
891 .write = xlnx_dp_write,
892 .endianness = DEVICE_NATIVE_ENDIAN,
893 .valid = {
894 .min_access_size = 4,
895 .max_access_size = 4,
896 },
897 .impl = {
898 .min_access_size = 4,
899 .max_access_size = 4,
900 },
901};
902
903
904
905
906static void xlnx_dp_vblend_write(void *opaque, hwaddr offset,
907 uint64_t value, unsigned size)
908{
909 XlnxDPState *s = XLNX_DP(opaque);
910 bool alpha_was_enabled;
911
912 DPRINTF("vblend: write @0x%" HWADDR_PRIX " = 0x%" PRIX32 "\n", offset,
913 (uint32_t)value);
914 offset = offset >> 2;
915
916 switch (offset) {
917 case V_BLEND_BG_CLR_0:
918 case V_BLEND_BG_CLR_1:
919 case V_BLEND_BG_CLR_2:
920 s->vblend_registers[offset] = value & 0x00000FFF;
921 break;
922 case V_BLEND_SET_GLOBAL_ALPHA_REG:
923
924
925
926
927 alpha_was_enabled = xlnx_dp_global_alpha_enabled(s);
928 s->vblend_registers[offset] = value & 0x000001FF;
929 if (xlnx_dp_global_alpha_enabled(s) != alpha_was_enabled) {
930 xlnx_dp_recreate_surface(s);
931 }
932 break;
933 case V_BLEND_OUTPUT_VID_FORMAT:
934 s->vblend_registers[offset] = value & 0x00000017;
935 break;
936 case V_BLEND_LAYER0_CONTROL:
937 case V_BLEND_LAYER1_CONTROL:
938 s->vblend_registers[offset] = value & 0x00000103;
939 break;
940 case V_BLEND_RGB2YCBCR_COEFF(0):
941 case V_BLEND_RGB2YCBCR_COEFF(1):
942 case V_BLEND_RGB2YCBCR_COEFF(2):
943 case V_BLEND_RGB2YCBCR_COEFF(3):
944 case V_BLEND_RGB2YCBCR_COEFF(4):
945 case V_BLEND_RGB2YCBCR_COEFF(5):
946 case V_BLEND_RGB2YCBCR_COEFF(6):
947 case V_BLEND_RGB2YCBCR_COEFF(7):
948 case V_BLEND_RGB2YCBCR_COEFF(8):
949 case V_BLEND_IN1CSC_COEFF(0):
950 case V_BLEND_IN1CSC_COEFF(1):
951 case V_BLEND_IN1CSC_COEFF(2):
952 case V_BLEND_IN1CSC_COEFF(3):
953 case V_BLEND_IN1CSC_COEFF(4):
954 case V_BLEND_IN1CSC_COEFF(5):
955 case V_BLEND_IN1CSC_COEFF(6):
956 case V_BLEND_IN1CSC_COEFF(7):
957 case V_BLEND_IN1CSC_COEFF(8):
958 case V_BLEND_IN2CSC_COEFF(0):
959 case V_BLEND_IN2CSC_COEFF(1):
960 case V_BLEND_IN2CSC_COEFF(2):
961 case V_BLEND_IN2CSC_COEFF(3):
962 case V_BLEND_IN2CSC_COEFF(4):
963 case V_BLEND_IN2CSC_COEFF(5):
964 case V_BLEND_IN2CSC_COEFF(6):
965 case V_BLEND_IN2CSC_COEFF(7):
966 case V_BLEND_IN2CSC_COEFF(8):
967 s->vblend_registers[offset] = value & 0x0000FFFF;
968 break;
969 case V_BLEND_LUMA_IN1CSC_OFFSET:
970 case V_BLEND_CR_IN1CSC_OFFSET:
971 case V_BLEND_CB_IN1CSC_OFFSET:
972 case V_BLEND_LUMA_IN2CSC_OFFSET:
973 case V_BLEND_CR_IN2CSC_OFFSET:
974 case V_BLEND_CB_IN2CSC_OFFSET:
975 case V_BLEND_LUMA_OUTCSC_OFFSET:
976 case V_BLEND_CR_OUTCSC_OFFSET:
977 case V_BLEND_CB_OUTCSC_OFFSET:
978 s->vblend_registers[offset] = value & 0x3FFF7FFF;
979 break;
980 case V_BLEND_CHROMA_KEY_ENABLE:
981 s->vblend_registers[offset] = value & 0x00000003;
982 break;
983 case V_BLEND_CHROMA_KEY_COMP1:
984 case V_BLEND_CHROMA_KEY_COMP2:
985 case V_BLEND_CHROMA_KEY_COMP3:
986 s->vblend_registers[offset] = value & 0x0FFF0FFF;
987 break;
988 default:
989 s->vblend_registers[offset] = value;
990 break;
991 }
992}
993
994static uint64_t xlnx_dp_vblend_read(void *opaque, hwaddr offset,
995 unsigned size)
996{
997 XlnxDPState *s = XLNX_DP(opaque);
998
999 DPRINTF("vblend: read @0x%" HWADDR_PRIX " = 0x%" PRIX32 "\n", offset,
1000 s->vblend_registers[offset >> 2]);
1001 return s->vblend_registers[offset >> 2];
1002}
1003
1004static const MemoryRegionOps vblend_ops = {
1005 .read = xlnx_dp_vblend_read,
1006 .write = xlnx_dp_vblend_write,
1007 .endianness = DEVICE_NATIVE_ENDIAN,
1008 .valid = {
1009 .min_access_size = 4,
1010 .max_access_size = 4,
1011 },
1012 .impl = {
1013 .min_access_size = 4,
1014 .max_access_size = 4,
1015 },
1016};
1017
1018
1019
1020
1021static void xlnx_dp_avbufm_write(void *opaque, hwaddr offset, uint64_t value,
1022 unsigned size)
1023{
1024 XlnxDPState *s = XLNX_DP(opaque);
1025
1026 DPRINTF("avbufm: write @0x%" HWADDR_PRIX " = 0x%" PRIX32 "\n", offset,
1027 (uint32_t)value);
1028 offset = offset >> 2;
1029
1030 switch (offset) {
1031 case AV_BUF_FORMAT:
1032 s->avbufm_registers[offset] = value & 0x00000FFF;
1033 xlnx_dp_change_graphic_fmt(s);
1034 break;
1035 case AV_CHBUF0:
1036 case AV_CHBUF1:
1037 case AV_CHBUF2:
1038 case AV_CHBUF3:
1039 case AV_CHBUF4:
1040 case AV_CHBUF5:
1041 s->avbufm_registers[offset] = value & 0x0000007F;
1042 break;
1043 case AV_BUF_OUTPUT_AUDIO_VIDEO_SELECT:
1044 s->avbufm_registers[offset] = value & 0x0000007F;
1045 break;
1046 case AV_BUF_DITHER_CONFIG:
1047 s->avbufm_registers[offset] = value & 0x000007FF;
1048 break;
1049 case AV_BUF_DITHER_CONFIG_MAX:
1050 case AV_BUF_DITHER_CONFIG_MIN:
1051 s->avbufm_registers[offset] = value & 0x00000FFF;
1052 break;
1053 case AV_BUF_PATTERN_GEN_SELECT:
1054 s->avbufm_registers[offset] = value & 0xFFFFFF03;
1055 break;
1056 case AV_BUF_AUD_VID_CLK_SOURCE:
1057 s->avbufm_registers[offset] = value & 0x00000007;
1058 break;
1059 case AV_BUF_SRST_REG:
1060 s->avbufm_registers[offset] = value & 0x00000002;
1061 break;
1062 case AV_BUF_AUDIO_CH_CONFIG:
1063 s->avbufm_registers[offset] = value & 0x00000003;
1064 break;
1065 case AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(0):
1066 case AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(1):
1067 case AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(2):
1068 case AV_BUF_VIDEO_COMP_SCALE_FACTOR(0):
1069 case AV_BUF_VIDEO_COMP_SCALE_FACTOR(1):
1070 case AV_BUF_VIDEO_COMP_SCALE_FACTOR(2):
1071 s->avbufm_registers[offset] = value & 0x0000FFFF;
1072 break;
1073 case AV_BUF_LIVE_VIDEO_COMP_SF(0):
1074 case AV_BUF_LIVE_VIDEO_COMP_SF(1):
1075 case AV_BUF_LIVE_VIDEO_COMP_SF(2):
1076 case AV_BUF_LIVE_VID_CONFIG:
1077 case AV_BUF_LIVE_GFX_COMP_SF(0):
1078 case AV_BUF_LIVE_GFX_COMP_SF(1):
1079 case AV_BUF_LIVE_GFX_COMP_SF(2):
1080 case AV_BUF_LIVE_GFX_CONFIG:
1081 case AV_BUF_NON_LIVE_LATENCY:
1082 case AV_BUF_STC_CONTROL:
1083 case AV_BUF_STC_INIT_VALUE0:
1084 case AV_BUF_STC_INIT_VALUE1:
1085 case AV_BUF_STC_ADJ:
1086 case AV_BUF_STC_VIDEO_VSYNC_TS_REG0:
1087 case AV_BUF_STC_VIDEO_VSYNC_TS_REG1:
1088 case AV_BUF_STC_EXT_VSYNC_TS_REG0:
1089 case AV_BUF_STC_EXT_VSYNC_TS_REG1:
1090 case AV_BUF_STC_CUSTOM_EVENT_TS_REG0:
1091 case AV_BUF_STC_CUSTOM_EVENT_TS_REG1:
1092 case AV_BUF_STC_CUSTOM_EVENT2_TS_REG0:
1093 case AV_BUF_STC_CUSTOM_EVENT2_TS_REG1:
1094 case AV_BUF_STC_SNAPSHOT0:
1095 case AV_BUF_STC_SNAPSHOT1:
1096 case AV_BUF_HCOUNT_VCOUNT_INT0:
1097 case AV_BUF_HCOUNT_VCOUNT_INT1:
1098 qemu_log_mask(LOG_UNIMP, "avbufm: unimplemented register 0x%04"
1099 PRIx64 "\n",
1100 offset << 2);
1101 break;
1102 default:
1103 s->avbufm_registers[offset] = value;
1104 break;
1105 }
1106}
1107
1108static uint64_t xlnx_dp_avbufm_read(void *opaque, hwaddr offset,
1109 unsigned size)
1110{
1111 XlnxDPState *s = XLNX_DP(opaque);
1112
1113 offset = offset >> 2;
1114 return s->avbufm_registers[offset];
1115}
1116
1117static const MemoryRegionOps avbufm_ops = {
1118 .read = xlnx_dp_avbufm_read,
1119 .write = xlnx_dp_avbufm_write,
1120 .endianness = DEVICE_NATIVE_ENDIAN,
1121 .valid = {
1122 .min_access_size = 4,
1123 .max_access_size = 4,
1124 },
1125 .impl = {
1126 .min_access_size = 4,
1127 .max_access_size = 4,
1128 },
1129};
1130
1131
1132
1133
1134
1135
1136static inline void xlnx_dp_blend_surface(XlnxDPState *s)
1137{
1138 pixman_fixed_t alpha1[] = { pixman_double_to_fixed(1),
1139 pixman_double_to_fixed(1),
1140 pixman_double_to_fixed(1.0) };
1141 pixman_fixed_t alpha2[] = { pixman_double_to_fixed(1),
1142 pixman_double_to_fixed(1),
1143 pixman_double_to_fixed(1.0) };
1144
1145 if ((surface_width(s->g_plane.surface)
1146 != surface_width(s->v_plane.surface)) ||
1147 (surface_height(s->g_plane.surface)
1148 != surface_height(s->v_plane.surface))) {
1149 return;
1150 }
1151
1152 alpha1[2] = pixman_double_to_fixed((double)(xlnx_dp_global_alpha_value(s))
1153 / 256.0);
1154 alpha2[2] = pixman_double_to_fixed((255.0
1155 - (double)xlnx_dp_global_alpha_value(s))
1156 / 256.0);
1157
1158 pixman_image_set_filter(s->g_plane.surface->image,
1159 PIXMAN_FILTER_CONVOLUTION, alpha1, 3);
1160 pixman_image_composite(PIXMAN_OP_SRC, s->g_plane.surface->image, 0,
1161 s->bout_plane.surface->image, 0, 0, 0, 0, 0, 0,
1162 surface_width(s->g_plane.surface),
1163 surface_height(s->g_plane.surface));
1164 pixman_image_set_filter(s->v_plane.surface->image,
1165 PIXMAN_FILTER_CONVOLUTION, alpha2, 3);
1166 pixman_image_composite(PIXMAN_OP_ADD, s->v_plane.surface->image, 0,
1167 s->bout_plane.surface->image, 0, 0, 0, 0, 0, 0,
1168 surface_width(s->g_plane.surface),
1169 surface_height(s->g_plane.surface));
1170}
1171
1172static void xlnx_dp_update_display(void *opaque)
1173{
1174 XlnxDPState *s = XLNX_DP(opaque);
1175
1176 if ((s->core_registers[DP_TRANSMITTER_ENABLE] & 0x01) == 0) {
1177 return;
1178 }
1179
1180 s->core_registers[DP_INT_STATUS] |= (1 << 13);
1181 xlnx_dp_update_irq(s);
1182
1183 xlnx_dpdma_trigger_vsync_irq(s->dpdma);
1184
1185
1186
1187
1188 if (!xlnx_dpdma_start_operation(s->dpdma, 3, false)) {
1189
1190
1191
1192
1193 s->core_registers[DP_INT_STATUS] |= (1 << 21);
1194 xlnx_dp_update_irq(s);
1195 return;
1196 }
1197
1198 if (xlnx_dp_global_alpha_enabled(s)) {
1199 if (!xlnx_dpdma_start_operation(s->dpdma, 0, false)) {
1200 s->core_registers[DP_INT_STATUS] |= (1 << 21);
1201 xlnx_dp_update_irq(s);
1202 return;
1203 }
1204 xlnx_dp_blend_surface(s);
1205 }
1206
1207
1208
1209
1210 dpy_gfx_update_full(s->console);
1211}
1212
1213static const GraphicHwOps xlnx_dp_gfx_ops = {
1214 .gfx_update = xlnx_dp_update_display,
1215};
1216
1217static void xlnx_dp_init(Object *obj)
1218{
1219 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
1220 XlnxDPState *s = XLNX_DP(obj);
1221
1222 memory_region_init(&s->container, obj, TYPE_XLNX_DP, 0xC050);
1223
1224 memory_region_init_io(&s->core_iomem, obj, &dp_ops, s, TYPE_XLNX_DP
1225 ".core", 0x3AF);
1226 memory_region_add_subregion(&s->container, 0x0000, &s->core_iomem);
1227
1228 memory_region_init_io(&s->vblend_iomem, obj, &vblend_ops, s, TYPE_XLNX_DP
1229 ".v_blend", 0x1DF);
1230 memory_region_add_subregion(&s->container, 0xA000, &s->vblend_iomem);
1231
1232 memory_region_init_io(&s->avbufm_iomem, obj, &avbufm_ops, s, TYPE_XLNX_DP
1233 ".av_buffer_manager", 0x238);
1234 memory_region_add_subregion(&s->container, 0xB000, &s->avbufm_iomem);
1235
1236 memory_region_init_io(&s->audio_iomem, obj, &audio_ops, s, TYPE_XLNX_DP
1237 ".audio", sizeof(s->audio_registers));
1238 memory_region_add_subregion(&s->container, 0xC000, &s->audio_iomem);
1239
1240 sysbus_init_mmio(sbd, &s->container);
1241 sysbus_init_irq(sbd, &s->irq);
1242
1243 object_property_add_link(obj, "dpdma", TYPE_XLNX_DPDMA,
1244 (Object **) &s->dpdma,
1245 xlnx_dp_set_dpdma,
1246 OBJ_PROP_LINK_STRONG);
1247
1248
1249
1250
1251 s->aux_bus = aux_bus_init(DEVICE(obj), "aux");
1252
1253
1254
1255
1256 s->dpcd = DPCD(qdev_new("dpcd"));
1257 object_property_add_child(OBJECT(s), "dpcd", OBJECT(s->dpcd));
1258
1259 s->edid = I2CDDC(qdev_new("i2c-ddc"));
1260 i2c_slave_set_address(I2C_SLAVE(s->edid), 0x50);
1261 object_property_add_child(OBJECT(s), "edid", OBJECT(s->edid));
1262
1263 fifo8_create(&s->rx_fifo, 16);
1264 fifo8_create(&s->tx_fifo, 16);
1265}
1266
1267static void xlnx_dp_finalize(Object *obj)
1268{
1269 XlnxDPState *s = XLNX_DP(obj);
1270
1271 fifo8_destroy(&s->tx_fifo);
1272 fifo8_destroy(&s->rx_fifo);
1273}
1274
1275static void xlnx_dp_realize(DeviceState *dev, Error **errp)
1276{
1277 XlnxDPState *s = XLNX_DP(dev);
1278 DisplaySurface *surface;
1279 struct audsettings as;
1280
1281 aux_bus_realize(s->aux_bus);
1282
1283 qdev_realize(DEVICE(s->dpcd), BUS(s->aux_bus), &error_fatal);
1284 aux_map_slave(AUX_SLAVE(s->dpcd), 0x0000);
1285
1286 qdev_realize_and_unref(DEVICE(s->edid), BUS(aux_get_i2c_bus(s->aux_bus)),
1287 &error_fatal);
1288
1289 s->console = graphic_console_init(dev, 0, &xlnx_dp_gfx_ops, s);
1290 surface = qemu_console_surface(s->console);
1291 xlnx_dpdma_set_host_data_location(s->dpdma, DP_GRAPHIC_DMA_CHANNEL,
1292 surface_data(surface));
1293
1294 as.freq = 44100;
1295 as.nchannels = 2;
1296 as.fmt = AUDIO_FORMAT_S16;
1297 as.endianness = 0;
1298
1299 AUD_register_card("xlnx_dp.audio", &s->aud_card);
1300
1301 s->amixer_output_stream = AUD_open_out(&s->aud_card,
1302 s->amixer_output_stream,
1303 "xlnx_dp.audio.out",
1304 s,
1305 xlnx_dp_audio_callback,
1306 &as);
1307 AUD_set_volume_out(s->amixer_output_stream, 0, 255, 255);
1308 xlnx_dp_audio_activate(s);
1309}
1310
1311static void xlnx_dp_reset(DeviceState *dev)
1312{
1313 XlnxDPState *s = XLNX_DP(dev);
1314
1315 memset(s->core_registers, 0, sizeof(s->core_registers));
1316 s->core_registers[DP_VERSION_REGISTER] = 0x04010000;
1317 s->core_registers[DP_CORE_ID] = 0x01020000;
1318 s->core_registers[DP_REPLY_STATUS] = 0x00000010;
1319 s->core_registers[DP_MSA_TRANSFER_UNIT_SIZE] = 0x00000040;
1320 s->core_registers[DP_INIT_WAIT] = 0x00000020;
1321 s->core_registers[DP_PHY_RESET] = 0x00010003;
1322 s->core_registers[DP_INT_MASK] = 0xFFFFF03F;
1323 s->core_registers[DP_PHY_STATUS] = 0x00000043;
1324 s->core_registers[DP_INTERRUPT_SIGNAL_STATE] = 0x00000001;
1325
1326 s->vblend_registers[V_BLEND_RGB2YCBCR_COEFF(0)] = 0x00001000;
1327 s->vblend_registers[V_BLEND_RGB2YCBCR_COEFF(4)] = 0x00001000;
1328 s->vblend_registers[V_BLEND_RGB2YCBCR_COEFF(8)] = 0x00001000;
1329 s->vblend_registers[V_BLEND_IN1CSC_COEFF(0)] = 0x00001000;
1330 s->vblend_registers[V_BLEND_IN1CSC_COEFF(4)] = 0x00001000;
1331 s->vblend_registers[V_BLEND_IN1CSC_COEFF(8)] = 0x00001000;
1332 s->vblend_registers[V_BLEND_IN2CSC_COEFF(0)] = 0x00001000;
1333 s->vblend_registers[V_BLEND_IN2CSC_COEFF(4)] = 0x00001000;
1334 s->vblend_registers[V_BLEND_IN2CSC_COEFF(8)] = 0x00001000;
1335
1336 s->avbufm_registers[AV_BUF_NON_LIVE_LATENCY] = 0x00000180;
1337 s->avbufm_registers[AV_BUF_OUTPUT_AUDIO_VIDEO_SELECT] = 0x00000008;
1338 s->avbufm_registers[AV_BUF_DITHER_CONFIG_MAX] = 0x00000FFF;
1339 s->avbufm_registers[AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(0)] = 0x00010101;
1340 s->avbufm_registers[AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(1)] = 0x00010101;
1341 s->avbufm_registers[AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(2)] = 0x00010101;
1342 s->avbufm_registers[AV_BUF_VIDEO_COMP_SCALE_FACTOR(0)] = 0x00010101;
1343 s->avbufm_registers[AV_BUF_VIDEO_COMP_SCALE_FACTOR(1)] = 0x00010101;
1344 s->avbufm_registers[AV_BUF_VIDEO_COMP_SCALE_FACTOR(2)] = 0x00010101;
1345 s->avbufm_registers[AV_BUF_LIVE_VIDEO_COMP_SF(0)] = 0x00010101;
1346 s->avbufm_registers[AV_BUF_LIVE_VIDEO_COMP_SF(1)] = 0x00010101;
1347 s->avbufm_registers[AV_BUF_LIVE_VIDEO_COMP_SF(2)] = 0x00010101;
1348 s->avbufm_registers[AV_BUF_LIVE_GFX_COMP_SF(0)] = 0x00010101;
1349 s->avbufm_registers[AV_BUF_LIVE_GFX_COMP_SF(1)] = 0x00010101;
1350 s->avbufm_registers[AV_BUF_LIVE_GFX_COMP_SF(2)] = 0x00010101;
1351
1352 memset(s->audio_registers, 0, sizeof(s->audio_registers));
1353 s->byte_left = 0;
1354
1355 xlnx_dp_aux_clear_rx_fifo(s);
1356 xlnx_dp_change_graphic_fmt(s);
1357 xlnx_dp_update_irq(s);
1358}
1359
1360static void xlnx_dp_class_init(ObjectClass *oc, void *data)
1361{
1362 DeviceClass *dc = DEVICE_CLASS(oc);
1363
1364 dc->realize = xlnx_dp_realize;
1365 dc->vmsd = &vmstate_dp;
1366 dc->reset = xlnx_dp_reset;
1367}
1368
1369static const TypeInfo xlnx_dp_info = {
1370 .name = TYPE_XLNX_DP,
1371 .parent = TYPE_SYS_BUS_DEVICE,
1372 .instance_size = sizeof(XlnxDPState),
1373 .instance_init = xlnx_dp_init,
1374 .instance_finalize = xlnx_dp_finalize,
1375 .class_init = xlnx_dp_class_init,
1376};
1377
1378static void xlnx_dp_register_types(void)
1379{
1380 type_register_static(&xlnx_dp_info);
1381}
1382
1383type_init(xlnx_dp_register_types)
1384
