LXR qemu/hw/i386/fw

   1/*
   2 * QEMU fw_cfg helpers (X86 specific)
   3 *
   4 * Copyright (c) 2019 Red Hat, Inc.
   5 *
   6 * Author:
   7 *   Philippe Mathieu-Daudé <philmd@redhat.com>
   8 *
   9 * SPDX-License-Identifier: GPL-2.0-or-later
  10 *
  11 * This work is licensed under the terms of the GNU GPL, version 2 or later.
  12 * See the COPYING file in the top-level directory.
  13 */
  14
  15#include "qemu/osdep.h"
  16#include "sysemu/numa.h"
  17#include "hw/acpi/acpi.h"
  18#include "hw/acpi/aml-build.h"
  19#include "hw/firmware/smbios.h"
  20#include "hw/i386/fw_cfg.h"
  21#include "hw/timer/hpet.h"
  22#include "hw/nvram/fw_cfg.h"
  23#include "e820_memory_layout.h"
  24#include "kvm/kvm_i386.h"
  25#include "qapi/error.h"
  26#include CONFIG_DEVICES
  27
  28struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX};
  29
  30const char *fw_cfg_arch_key_name(uint16_t key)
  31{
  32    static const struct {
  33        uint16_t key;
  34        const char *name;
  35    } fw_cfg_arch_wellknown_keys[] = {
  36        {FW_CFG_ACPI_TABLES, "acpi_tables"},
  37        {FW_CFG_SMBIOS_ENTRIES, "smbios_entries"},
  38        {FW_CFG_IRQ0_OVERRIDE, "irq0_override"},
  39        {FW_CFG_E820_TABLE, "e820_table"},
  40        {FW_CFG_HPET, "hpet"},
  41    };
  42
  43    for (size_t i = 0; i < ARRAY_SIZE(fw_cfg_arch_wellknown_keys); i++) {
  44        if (fw_cfg_arch_wellknown_keys[i].key == key) {
  45            return fw_cfg_arch_wellknown_keys[i].name;
  46        }
  47    }
  48    return NULL;
  49}
  50
  51void fw_cfg_build_smbios(MachineState *ms, FWCfgState *fw_cfg)
  52{
  53#ifdef CONFIG_SMBIOS
  54    uint8_t *smbios_tables, *smbios_anchor;
  55    size_t smbios_tables_len, smbios_anchor_len;
  56    struct smbios_phys_mem_area *mem_array;
  57    unsigned i, array_count;
  58    X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu);
  59
  60    /* tell smbios about cpuid version and features */
  61    smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]);
  62
  63    smbios_tables = smbios_get_table_legacy(ms, &smbios_tables_len);
  64    if (smbios_tables) {
  65        fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
  66                         smbios_tables, smbios_tables_len);
  67    }
  68
  69    /* build the array of physical mem area from e820 table */
  70    mem_array = g_malloc0(sizeof(*mem_array) * e820_get_num_entries());
  71    for (i = 0, array_count = 0; i < e820_get_num_entries(); i++) {
  72        uint64_t addr, len;
  73
  74        if (e820_get_entry(i, E820_RAM, &addr, &len)) {
  75            mem_array[array_count].address = addr;
  76            mem_array[array_count].length = len;
  77            array_count++;
  78        }
  79    }
  80    smbios_get_tables(ms, mem_array, array_count,
  81                      &smbios_tables, &smbios_tables_len,
  82                      &smbios_anchor, &smbios_anchor_len,
  83                      &error_fatal);
  84    g_free(mem_array);
  85
  86    if (smbios_anchor) {
  87        fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-tables",
  88                        smbios_tables, smbios_tables_len);
  89        fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-anchor",
  90                        smbios_anchor, smbios_anchor_len);
  91    }
  92#endif
  93}
  94
  95FWCfgState *fw_cfg_arch_create(MachineState *ms,
  96                                      uint16_t boot_cpus,
  97                                      uint16_t apic_id_limit)
  98{
  99    FWCfgState *fw_cfg;
 100    uint64_t *numa_fw_cfg;
 101    int i;
 102    MachineClass *mc = MACHINE_GET_CLASS(ms);
 103    const CPUArchIdList *cpus = mc->possible_cpu_arch_ids(ms);
 104    int nb_numa_nodes = ms->numa_state->num_nodes;
 105
 106    fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4,
 107                                &address_space_memory);
 108    fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, boot_cpus);
 109
 110    /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86:
 111     *
 112     * For machine types prior to 1.8, SeaBIOS needs FW_CFG_MAX_CPUS for
 113     * building MPTable, ACPI MADT, ACPI CPU hotplug and ACPI SRAT table,
 114     * that tables are based on xAPIC ID and QEMU<->SeaBIOS interface
 115     * for CPU hotplug also uses APIC ID and not "CPU index".
 116     * This means that FW_CFG_MAX_CPUS is not the "maximum number of CPUs",
 117     * but the "limit to the APIC ID values SeaBIOS may see".
 118     *
 119     * So for compatibility reasons with old BIOSes we are stuck with
 120     * "etc/max-cpus" actually being apic_id_limit
 121     */
 122    fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, apic_id_limit);
 123    fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, ms->ram_size);
 124#ifdef CONFIG_ACPI
 125    fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES,
 126                     acpi_tables, acpi_tables_len);
 127#endif
 128    fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, 1);
 129
 130    fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE,
 131                     &e820_reserve, sizeof(e820_reserve));
 132    fw_cfg_add_file(fw_cfg, "etc/e820", e820_table,
 133                    sizeof(struct e820_entry) * e820_get_num_entries());
 134
 135    fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg));
 136    /* allocate memory for the NUMA channel: one (64bit) word for the number
 137     * of nodes, one word for each VCPU->node and one word for each node to
 138     * hold the amount of memory.
 139     */
 140    numa_fw_cfg = g_new0(uint64_t, 1 + apic_id_limit + nb_numa_nodes);
 141    numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
 142    for (i = 0; i < cpus->len; i++) {
 143        unsigned int apic_id = cpus->cpus[i].arch_id;
 144        assert(apic_id < apic_id_limit);
 145        numa_fw_cfg[apic_id + 1] = cpu_to_le64(cpus->cpus[i].props.node_id);
 146    }
 147    for (i = 0; i < nb_numa_nodes; i++) {
 148        numa_fw_cfg[apic_id_limit + 1 + i] =
 149            cpu_to_le64(ms->numa_state->nodes[i].node_mem);
 150    }
 151    fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg,
 152                     (1 + apic_id_limit + nb_numa_nodes) *
 153                     sizeof(*numa_fw_cfg));
 154
 155    return fw_cfg;
 156}
 157
 158void fw_cfg_build_feature_control(MachineState *ms, FWCfgState *fw_cfg)
 159{
 160    X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu);
 161    CPUX86State *env = &cpu->env;
 162    uint32_t unused, ebx, ecx, edx;
 163    uint64_t feature_control_bits = 0;
 164    uint64_t *val;
 165
 166    cpu_x86_cpuid(env, 1, 0, &unused, &unused, &ecx, &edx);
 167    if (ecx & CPUID_EXT_VMX) {
 168        feature_control_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
 169    }
 170
 171    if ((edx & (CPUID_EXT2_MCE | CPUID_EXT2_MCA)) ==
 172        (CPUID_EXT2_MCE | CPUID_EXT2_MCA) &&
 173        (env->mcg_cap & MCG_LMCE_P)) {
 174        feature_control_bits |= FEATURE_CONTROL_LMCE;
 175    }
 176
 177    if (env->cpuid_level >= 7) {
 178        cpu_x86_cpuid(env, 0x7, 0, &unused, &ebx, &ecx, &unused);
 179        if (ebx & CPUID_7_0_EBX_SGX) {
 180            feature_control_bits |= FEATURE_CONTROL_SGX;
 181        }
 182        if (ecx & CPUID_7_0_ECX_SGX_LC) {
 183            feature_control_bits |= FEATURE_CONTROL_SGX_LC;
 184        }
 185    }
 186
 187    if (!feature_control_bits) {
 188        return;
 189    }
 190
 191    val = g_malloc(sizeof(*val));
 192    *val = cpu_to_le64(feature_control_bits | FEATURE_CONTROL_LOCKED);
 193    fw_cfg_add_file(fw_cfg, "etc/msr_feature_control", val, sizeof(*val));
 194}
 195
 196void fw_cfg_add_acpi_dsdt(Aml *scope, FWCfgState *fw_cfg)
 197{
 198    /*
 199     * when using port i/o, the 8-bit data register *always* overlaps
 200     * with half of the 16-bit control register. Hence, the total size
 201     * of the i/o region used is FW_CFG_CTL_SIZE; when using DMA, the
 202     * DMA control register is located at FW_CFG_DMA_IO_BASE + 4
 203     */
 204    Object *obj = OBJECT(fw_cfg);
 205    uint8_t io_size = object_property_get_bool(obj, "dma_enabled", NULL) ?
 206        ROUND_UP(FW_CFG_CTL_SIZE, 4) + sizeof(dma_addr_t) :
 207        FW_CFG_CTL_SIZE;
 208    Aml *dev = aml_device("FWCF");
 209    Aml *crs = aml_resource_template();
 210
 211    aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002")));
 212
 213    /* device present, functioning, decoding, not shown in UI */
 214    aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
 215
 216    aml_append(crs,
 217        aml_io(AML_DECODE16, FW_CFG_IO_BASE, FW_CFG_IO_BASE, 0x01, io_size));
 218
 219    aml_append(dev, aml_name_decl("_CRS", crs));
 220    aml_append(scope, dev);
 221}
 222