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33#include "qemu/osdep.h"
34#include "qemu/cutils.h"
35#include "sysemu/device_tree.h"
36#include "hw/char/serial.h"
37#include "hw/i386/fw_cfg.h"
38#include "hw/rtc/mc146818rtc.h"
39#include "hw/sysbus.h"
40#include "hw/virtio/virtio-mmio.h"
41#include "hw/usb/xhci.h"
42
43#include "microvm-dt.h"
44
45static bool debug;
46
47static void dt_add_microvm_irq(MicrovmMachineState *mms,
48 const char *nodename, uint32_t irq)
49{
50 int index = 0;
51
52 if (irq >= IO_APIC_SECONDARY_IRQBASE) {
53 irq -= IO_APIC_SECONDARY_IRQBASE;
54 index++;
55 }
56
57 qemu_fdt_setprop_cell(mms->fdt, nodename, "interrupt-parent",
58 mms->ioapic_phandle[index]);
59 qemu_fdt_setprop_cells(mms->fdt, nodename, "interrupts", irq, 0);
60}
61
62static void dt_add_virtio(MicrovmMachineState *mms, VirtIOMMIOProxy *mmio)
63{
64 SysBusDevice *dev = SYS_BUS_DEVICE(mmio);
65 VirtioBusState *mmio_virtio_bus = &mmio->bus;
66 BusState *mmio_bus = &mmio_virtio_bus->parent_obj;
67 char *nodename;
68
69 if (QTAILQ_EMPTY(&mmio_bus->children)) {
70 return;
71 }
72
73 hwaddr base = dev->mmio[0].addr;
74 hwaddr size = 512;
75 unsigned index = (base - VIRTIO_MMIO_BASE) / size;
76 uint32_t irq = mms->virtio_irq_base + index;
77
78 nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base);
79 qemu_fdt_add_subnode(mms->fdt, nodename);
80 qemu_fdt_setprop_string(mms->fdt, nodename, "compatible", "virtio,mmio");
81 qemu_fdt_setprop_sized_cells(mms->fdt, nodename, "reg", 2, base, 2, size);
82 qemu_fdt_setprop(mms->fdt, nodename, "dma-coherent", NULL, 0);
83 dt_add_microvm_irq(mms, nodename, irq);
84 g_free(nodename);
85}
86
87static void dt_add_xhci(MicrovmMachineState *mms)
88{
89 const char compat[] = "generic-xhci";
90 uint32_t irq = MICROVM_XHCI_IRQ;
91 hwaddr base = MICROVM_XHCI_BASE;
92 hwaddr size = XHCI_LEN_REGS;
93 char *nodename;
94
95 nodename = g_strdup_printf("/usb@%" PRIx64, base);
96 qemu_fdt_add_subnode(mms->fdt, nodename);
97 qemu_fdt_setprop(mms->fdt, nodename, "compatible", compat, sizeof(compat));
98 qemu_fdt_setprop_sized_cells(mms->fdt, nodename, "reg", 2, base, 2, size);
99 qemu_fdt_setprop(mms->fdt, nodename, "dma-coherent", NULL, 0);
100 dt_add_microvm_irq(mms, nodename, irq);
101 g_free(nodename);
102}
103
104static void dt_add_pcie(MicrovmMachineState *mms)
105{
106 hwaddr base = PCIE_MMIO_BASE;
107 int nr_pcie_buses;
108 char *nodename;
109
110 nodename = g_strdup_printf("/pcie@%" PRIx64, base);
111 qemu_fdt_add_subnode(mms->fdt, nodename);
112 qemu_fdt_setprop_string(mms->fdt, nodename,
113 "compatible", "pci-host-ecam-generic");
114 qemu_fdt_setprop_string(mms->fdt, nodename, "device_type", "pci");
115 qemu_fdt_setprop_cell(mms->fdt, nodename, "#address-cells", 3);
116 qemu_fdt_setprop_cell(mms->fdt, nodename, "#size-cells", 2);
117 qemu_fdt_setprop_cell(mms->fdt, nodename, "linux,pci-domain", 0);
118 qemu_fdt_setprop(mms->fdt, nodename, "dma-coherent", NULL, 0);
119
120 qemu_fdt_setprop_sized_cells(mms->fdt, nodename, "reg",
121 2, PCIE_ECAM_BASE, 2, PCIE_ECAM_SIZE);
122 if (mms->gpex.mmio64.size) {
123 qemu_fdt_setprop_sized_cells(mms->fdt, nodename, "ranges",
124
125 1, FDT_PCI_RANGE_MMIO,
126 2, mms->gpex.mmio32.base,
127 2, mms->gpex.mmio32.base,
128 2, mms->gpex.mmio32.size,
129
130 1, FDT_PCI_RANGE_MMIO_64BIT,
131 2, mms->gpex.mmio64.base,
132 2, mms->gpex.mmio64.base,
133 2, mms->gpex.mmio64.size);
134 } else {
135 qemu_fdt_setprop_sized_cells(mms->fdt, nodename, "ranges",
136
137 1, FDT_PCI_RANGE_MMIO,
138 2, mms->gpex.mmio32.base,
139 2, mms->gpex.mmio32.base,
140 2, mms->gpex.mmio32.size);
141 }
142
143 nr_pcie_buses = PCIE_ECAM_SIZE / PCIE_MMCFG_SIZE_MIN;
144 qemu_fdt_setprop_cells(mms->fdt, nodename, "bus-range", 0,
145 nr_pcie_buses - 1);
146
147 g_free(nodename);
148}
149
150static void dt_add_ioapic(MicrovmMachineState *mms, SysBusDevice *dev)
151{
152 hwaddr base = dev->mmio[0].addr;
153 char *nodename;
154 uint32_t ph;
155 int index;
156
157 switch (base) {
158 case IO_APIC_DEFAULT_ADDRESS:
159 index = 0;
160 break;
161 case IO_APIC_SECONDARY_ADDRESS:
162 index = 1;
163 break;
164 default:
165 fprintf(stderr, "unknown ioapic @ %" PRIx64 "\n", base);
166 return;
167 }
168
169 nodename = g_strdup_printf("/ioapic%d@%" PRIx64, index + 1, base);
170 qemu_fdt_add_subnode(mms->fdt, nodename);
171 qemu_fdt_setprop_string(mms->fdt, nodename,
172 "compatible", "intel,ce4100-ioapic");
173 qemu_fdt_setprop(mms->fdt, nodename, "interrupt-controller", NULL, 0);
174 qemu_fdt_setprop_cell(mms->fdt, nodename, "#interrupt-cells", 0x2);
175 qemu_fdt_setprop_cell(mms->fdt, nodename, "#address-cells", 0x2);
176 qemu_fdt_setprop_sized_cells(mms->fdt, nodename, "reg",
177 2, base, 2, 0x1000);
178
179 ph = qemu_fdt_alloc_phandle(mms->fdt);
180 qemu_fdt_setprop_cell(mms->fdt, nodename, "phandle", ph);
181 qemu_fdt_setprop_cell(mms->fdt, nodename, "linux,phandle", ph);
182 mms->ioapic_phandle[index] = ph;
183
184 g_free(nodename);
185}
186
187static void dt_add_isa_serial(MicrovmMachineState *mms, ISADevice *dev)
188{
189 const char compat[] = "ns16550";
190 uint32_t irq = object_property_get_int(OBJECT(dev), "irq", NULL);
191 hwaddr base = object_property_get_int(OBJECT(dev), "iobase", NULL);
192 hwaddr size = 8;
193 char *nodename;
194
195 nodename = g_strdup_printf("/serial@%" PRIx64, base);
196 qemu_fdt_add_subnode(mms->fdt, nodename);
197 qemu_fdt_setprop(mms->fdt, nodename, "compatible", compat, sizeof(compat));
198 qemu_fdt_setprop_sized_cells(mms->fdt, nodename, "reg", 2, base, 2, size);
199 dt_add_microvm_irq(mms, nodename, irq);
200
201 if (base == 0x3f8 ) {
202 qemu_fdt_setprop_string(mms->fdt, "/chosen", "stdout-path", nodename);
203 }
204
205 g_free(nodename);
206}
207
208static void dt_add_isa_rtc(MicrovmMachineState *mms, ISADevice *dev)
209{
210 const char compat[] = "motorola,mc146818";
211 uint32_t irq = RTC_ISA_IRQ;
212 hwaddr base = RTC_ISA_BASE;
213 hwaddr size = 8;
214 char *nodename;
215
216 nodename = g_strdup_printf("/rtc@%" PRIx64, base);
217 qemu_fdt_add_subnode(mms->fdt, nodename);
218 qemu_fdt_setprop(mms->fdt, nodename, "compatible", compat, sizeof(compat));
219 qemu_fdt_setprop_sized_cells(mms->fdt, nodename, "reg", 2, base, 2, size);
220 dt_add_microvm_irq(mms, nodename, irq);
221 g_free(nodename);
222}
223
224static void dt_setup_isa_bus(MicrovmMachineState *mms, DeviceState *bridge)
225{
226 BusState *bus = qdev_get_child_bus(bridge, "isa.0");
227 BusChild *kid;
228 Object *obj;
229
230 QTAILQ_FOREACH(kid, &bus->children, sibling) {
231 DeviceState *dev = kid->child;
232
233
234 obj = object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL);
235 if (obj) {
236 dt_add_isa_serial(mms, ISA_DEVICE(obj));
237 continue;
238 }
239
240
241 obj = object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC);
242 if (obj) {
243 dt_add_isa_rtc(mms, ISA_DEVICE(obj));
244 continue;
245 }
246
247 if (debug) {
248 fprintf(stderr, "%s: unhandled: %s\n", __func__,
249 object_get_typename(OBJECT(dev)));
250 }
251 }
252}
253
254static void dt_setup_sys_bus(MicrovmMachineState *mms)
255{
256 BusState *bus;
257 BusChild *kid;
258 Object *obj;
259
260
261 bus = sysbus_get_default();
262 QTAILQ_FOREACH(kid, &bus->children, sibling) {
263 DeviceState *dev = kid->child;
264
265
266 obj = object_dynamic_cast(OBJECT(dev), TYPE_IOAPIC);
267 if (obj) {
268 dt_add_ioapic(mms, SYS_BUS_DEVICE(obj));
269 continue;
270 }
271 }
272
273 QTAILQ_FOREACH(kid, &bus->children, sibling) {
274 DeviceState *dev = kid->child;
275
276
277 obj = object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MMIO);
278 if (obj) {
279 dt_add_virtio(mms, VIRTIO_MMIO(obj));
280 continue;
281 }
282
283
284 obj = object_dynamic_cast(OBJECT(dev), TYPE_XHCI_SYSBUS);
285 if (obj) {
286 dt_add_xhci(mms);
287 continue;
288 }
289
290
291 obj = object_dynamic_cast(OBJECT(dev), TYPE_GPEX_HOST);
292 if (obj) {
293 dt_add_pcie(mms);
294 continue;
295 }
296
297
298 obj = object_dynamic_cast(OBJECT(dev), "isabus-bridge");
299 if (obj) {
300 dt_setup_isa_bus(mms, DEVICE(obj));
301 continue;
302 }
303
304 if (debug) {
305 obj = object_dynamic_cast(OBJECT(dev), TYPE_IOAPIC);
306 if (obj) {
307
308 continue;
309 }
310 fprintf(stderr, "%s: unhandled: %s\n", __func__,
311 object_get_typename(OBJECT(dev)));
312 }
313 }
314}
315
316void dt_setup_microvm(MicrovmMachineState *mms)
317{
318 X86MachineState *x86ms = X86_MACHINE(mms);
319 int size = 0;
320
321 mms->fdt = create_device_tree(&size);
322
323
324 qemu_fdt_setprop_string(mms->fdt, "/", "compatible", "linux,microvm");
325 qemu_fdt_setprop_cell(mms->fdt, "/", "#address-cells", 0x2);
326 qemu_fdt_setprop_cell(mms->fdt, "/", "#size-cells", 0x2);
327
328 qemu_fdt_add_subnode(mms->fdt, "/chosen");
329 dt_setup_sys_bus(mms);
330
331
332 if (debug) {
333 fprintf(stderr, "%s: add etc/fdt to fw_cfg\n", __func__);
334 }
335 fw_cfg_add_file(x86ms->fw_cfg, "etc/fdt", mms->fdt, size);
336
337 if (debug) {
338 fprintf(stderr, "%s: writing microvm.fdt\n", __func__);
339 if (!g_file_set_contents("microvm.fdt", mms->fdt, size, NULL)) {
340 fprintf(stderr, "%s: writing microvm.fdt failed\n", __func__);
341 return;
342 }
343 int ret = system("dtc -I dtb -O dts microvm.fdt");
344 if (ret != 0) {
345 fprintf(stderr, "%s: oops, dtc not installed?\n", __func__);
346 }
347 }
348}
349