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18#include "qemu/osdep.h"
19#include "qapi/error.h"
20#include "qemu/module.h"
21#include "hw/intc/arm_gicv3.h"
22#include "gicv3_internal.h"
23
24static bool irqbetter(GICv3CPUState *cs, int irq, uint8_t prio)
25{
26
27
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29
30
31
32
33 if (prio < cs->hppi.prio) {
34 return true;
35 }
36
37
38
39
40 if (prio == cs->hppi.prio && irq <= cs->hppi.irq) {
41 return true;
42 }
43 return false;
44}
45
46static uint32_t gicd_int_pending(GICv3State *s, int irq)
47{
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59
60 uint32_t pend, grpmask;
61 uint32_t pending = *gic_bmp_ptr32(s->pending, irq);
62 uint32_t edge_trigger = *gic_bmp_ptr32(s->edge_trigger, irq);
63 uint32_t level = *gic_bmp_ptr32(s->level, irq);
64 uint32_t group = *gic_bmp_ptr32(s->group, irq);
65 uint32_t grpmod = *gic_bmp_ptr32(s->grpmod, irq);
66 uint32_t enable = *gic_bmp_ptr32(s->enabled, irq);
67 uint32_t active = *gic_bmp_ptr32(s->active, irq);
68
69 pend = pending | (~edge_trigger & level);
70 pend &= enable;
71 pend &= ~active;
72
73 if (s->gicd_ctlr & GICD_CTLR_DS) {
74 grpmod = 0;
75 }
76
77 grpmask = 0;
78 if (s->gicd_ctlr & GICD_CTLR_EN_GRP1NS) {
79 grpmask |= group;
80 }
81 if (s->gicd_ctlr & GICD_CTLR_EN_GRP1S) {
82 grpmask |= (~group & grpmod);
83 }
84 if (s->gicd_ctlr & GICD_CTLR_EN_GRP0) {
85 grpmask |= (~group & ~grpmod);
86 }
87 pend &= grpmask;
88
89 return pend;
90}
91
92static uint32_t gicr_int_pending(GICv3CPUState *cs)
93{
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105 uint32_t pend, grpmask, grpmod;
106
107 pend = cs->gicr_ipendr0 | (~cs->edge_trigger & cs->level);
108 pend &= cs->gicr_ienabler0;
109 pend &= ~cs->gicr_iactiver0;
110
111 if (cs->gic->gicd_ctlr & GICD_CTLR_DS) {
112 grpmod = 0;
113 } else {
114 grpmod = cs->gicr_igrpmodr0;
115 }
116
117 grpmask = 0;
118 if (cs->gic->gicd_ctlr & GICD_CTLR_EN_GRP1NS) {
119 grpmask |= cs->gicr_igroupr0;
120 }
121 if (cs->gic->gicd_ctlr & GICD_CTLR_EN_GRP1S) {
122 grpmask |= (~cs->gicr_igroupr0 & grpmod);
123 }
124 if (cs->gic->gicd_ctlr & GICD_CTLR_EN_GRP0) {
125 grpmask |= (~cs->gicr_igroupr0 & ~grpmod);
126 }
127 pend &= grpmask;
128
129 return pend;
130}
131
132
133
134
135static void gicv3_redist_update_noirqset(GICv3CPUState *cs)
136{
137
138
139
140 bool seenbetter = false;
141 uint8_t prio;
142 int i;
143 uint32_t pend;
144
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148 pend = gicr_int_pending(cs);
149
150 if (pend) {
151 for (i = 0; i < GIC_INTERNAL; i++) {
152 if (!(pend & (1 << i))) {
153 continue;
154 }
155 prio = cs->gicr_ipriorityr[i];
156 if (irqbetter(cs, i, prio)) {
157 cs->hppi.irq = i;
158 cs->hppi.prio = prio;
159 seenbetter = true;
160 }
161 }
162 }
163
164 if (seenbetter) {
165 cs->hppi.grp = gicv3_irq_group(cs->gic, cs, cs->hppi.irq);
166 }
167
168 if ((cs->gicr_ctlr & GICR_CTLR_ENABLE_LPIS) && cs->gic->lpi_enable &&
169 (cs->hpplpi.prio != 0xff)) {
170 if (irqbetter(cs, cs->hpplpi.irq, cs->hpplpi.prio)) {
171 cs->hppi.irq = cs->hpplpi.irq;
172 cs->hppi.prio = cs->hpplpi.prio;
173 cs->hppi.grp = cs->hpplpi.grp;
174 seenbetter = true;
175 }
176 }
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188
189 if (!seenbetter && cs->hppi.prio != 0xff &&
190 (cs->hppi.irq < GIC_INTERNAL ||
191 cs->hppi.irq >= GICV3_LPI_INTID_START)) {
192 gicv3_full_update_noirqset(cs->gic);
193 }
194}
195
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199
200void gicv3_redist_update(GICv3CPUState *cs)
201{
202 gicv3_redist_update_noirqset(cs);
203 gicv3_cpuif_update(cs);
204}
205
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208
209
210static void gicv3_update_noirqset(GICv3State *s, int start, int len)
211{
212 int i;
213 uint8_t prio;
214 uint32_t pend = 0;
215
216 assert(start >= GIC_INTERNAL);
217 assert(len > 0);
218
219 for (i = 0; i < s->num_cpu; i++) {
220 s->cpu[i].seenbetter = false;
221 }
222
223
224 for (i = start; i < start + len; i++) {
225 GICv3CPUState *cs;
226
227 if (i == start || (i & 0x1f) == 0) {
228
229 pend = gicd_int_pending(s, i & ~0x1f);
230 }
231
232 if (!(pend & (1 << (i & 0x1f)))) {
233 continue;
234 }
235 cs = s->gicd_irouter_target[i];
236 if (!cs) {
237
238
239
240 continue;
241 }
242 prio = s->gicd_ipriority[i];
243 if (irqbetter(cs, i, prio)) {
244 cs->hppi.irq = i;
245 cs->hppi.prio = prio;
246 cs->seenbetter = true;
247 }
248 }
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261 for (i = 0; i < s->num_cpu; i++) {
262 GICv3CPUState *cs = &s->cpu[i];
263
264 if (cs->seenbetter) {
265 cs->hppi.grp = gicv3_irq_group(cs->gic, cs, cs->hppi.irq);
266 }
267
268 if (!cs->seenbetter && cs->hppi.prio != 0xff &&
269 cs->hppi.irq >= start && cs->hppi.irq < start + len) {
270 gicv3_full_update_noirqset(s);
271 break;
272 }
273 }
274}
275
276void gicv3_update(GICv3State *s, int start, int len)
277{
278 int i;
279
280 gicv3_update_noirqset(s, start, len);
281 for (i = 0; i < s->num_cpu; i++) {
282 gicv3_cpuif_update(&s->cpu[i]);
283 }
284}
285
286void gicv3_full_update_noirqset(GICv3State *s)
287{
288
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291 int i;
292
293 for (i = 0; i < s->num_cpu; i++) {
294 s->cpu[i].hppi.prio = 0xff;
295 }
296
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300
301
302 gicv3_update_noirqset(s, GIC_INTERNAL, s->num_irq - GIC_INTERNAL);
303
304 for (i = 0; i < s->num_cpu; i++) {
305 gicv3_redist_update_noirqset(&s->cpu[i]);
306 }
307}
308
309void gicv3_full_update(GICv3State *s)
310{
311
312
313
314 int i;
315
316 gicv3_full_update_noirqset(s);
317 for (i = 0; i < s->num_cpu; i++) {
318 gicv3_cpuif_update(&s->cpu[i]);
319 }
320}
321
322
323static void gicv3_set_irq(void *opaque, int irq, int level)
324{
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328
329
330
331 GICv3State *s = opaque;
332
333 if (irq < (s->num_irq - GIC_INTERNAL)) {
334
335 gicv3_dist_set_irq(s, irq + GIC_INTERNAL, level);
336 } else {
337
338 int cpu;
339
340 irq -= (s->num_irq - GIC_INTERNAL);
341 cpu = irq / GIC_INTERNAL;
342 irq %= GIC_INTERNAL;
343 assert(cpu < s->num_cpu);
344
345
346
347 assert(irq >= GIC_NR_SGIS);
348 gicv3_redist_set_irq(&s->cpu[cpu], irq, level);
349 }
350}
351
352static void arm_gicv3_post_load(GICv3State *s)
353{
354 int i;
355
356
357
358 for (i = 0; i < s->num_cpu; i++) {
359 gicv3_redist_update_lpi_only(&s->cpu[i]);
360 }
361 gicv3_full_update_noirqset(s);
362
363 gicv3_cache_all_target_cpustates(s);
364}
365
366static const MemoryRegionOps gic_ops[] = {
367 {
368 .read_with_attrs = gicv3_dist_read,
369 .write_with_attrs = gicv3_dist_write,
370 .endianness = DEVICE_NATIVE_ENDIAN,
371 },
372 {
373 .read_with_attrs = gicv3_redist_read,
374 .write_with_attrs = gicv3_redist_write,
375 .endianness = DEVICE_NATIVE_ENDIAN,
376 }
377};
378
379static void arm_gic_realize(DeviceState *dev, Error **errp)
380{
381
382 GICv3State *s = ARM_GICV3(dev);
383 ARMGICv3Class *agc = ARM_GICV3_GET_CLASS(s);
384 Error *local_err = NULL;
385
386 agc->parent_realize(dev, &local_err);
387 if (local_err) {
388 error_propagate(errp, local_err);
389 return;
390 }
391
392 gicv3_init_irqs_and_mmio(s, gicv3_set_irq, gic_ops);
393
394 gicv3_init_cpuif(s);
395}
396
397static void arm_gicv3_class_init(ObjectClass *klass, void *data)
398{
399 DeviceClass *dc = DEVICE_CLASS(klass);
400 ARMGICv3CommonClass *agcc = ARM_GICV3_COMMON_CLASS(klass);
401 ARMGICv3Class *agc = ARM_GICV3_CLASS(klass);
402
403 agcc->post_load = arm_gicv3_post_load;
404 device_class_set_parent_realize(dc, arm_gic_realize, &agc->parent_realize);
405}
406
407static const TypeInfo arm_gicv3_info = {
408 .name = TYPE_ARM_GICV3,
409 .parent = TYPE_ARM_GICV3_COMMON,
410 .instance_size = sizeof(GICv3State),
411 .class_init = arm_gicv3_class_init,
412 .class_size = sizeof(ARMGICv3Class),
413};
414
415static void arm_gicv3_register_types(void)
416{
417 type_register_static(&arm_gicv3_info);
418}
419
420type_init(arm_gicv3_register_types)
421