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24#include "qemu/osdep.h"
25#include "qapi/error.h"
26#include "qemu/module.h"
27#include "hw/core/cpu.h"
28#include "hw/intc/arm_gicv3_common.h"
29#include "hw/qdev-properties.h"
30#include "migration/vmstate.h"
31#include "gicv3_internal.h"
32#include "hw/arm/linux-boot-if.h"
33#include "sysemu/kvm.h"
34
35
36static void gicv3_gicd_no_migration_shift_bug_post_load(GICv3State *cs)
37{
38 if (cs->gicd_no_migration_shift_bug) {
39 return;
40 }
41
42
43
44
45
46
47
48
49 memmove(cs->group, (uint8_t *)cs->group + GIC_INTERNAL / 8,
50 sizeof(cs->group) - GIC_INTERNAL / 8);
51 memmove(cs->grpmod, (uint8_t *)cs->grpmod + GIC_INTERNAL / 8,
52 sizeof(cs->grpmod) - GIC_INTERNAL / 8);
53 memmove(cs->enabled, (uint8_t *)cs->enabled + GIC_INTERNAL / 8,
54 sizeof(cs->enabled) - GIC_INTERNAL / 8);
55 memmove(cs->pending, (uint8_t *)cs->pending + GIC_INTERNAL / 8,
56 sizeof(cs->pending) - GIC_INTERNAL / 8);
57 memmove(cs->active, (uint8_t *)cs->active + GIC_INTERNAL / 8,
58 sizeof(cs->active) - GIC_INTERNAL / 8);
59 memmove(cs->edge_trigger, (uint8_t *)cs->edge_trigger + GIC_INTERNAL / 8,
60 sizeof(cs->edge_trigger) - GIC_INTERNAL / 8);
61
62
63
64
65
66
67 cs->gicd_no_migration_shift_bug = true;
68}
69
70static int gicv3_pre_save(void *opaque)
71{
72 GICv3State *s = (GICv3State *)opaque;
73 ARMGICv3CommonClass *c = ARM_GICV3_COMMON_GET_CLASS(s);
74
75 if (c->pre_save) {
76 c->pre_save(s);
77 }
78
79 return 0;
80}
81
82static int gicv3_post_load(void *opaque, int version_id)
83{
84 GICv3State *s = (GICv3State *)opaque;
85 ARMGICv3CommonClass *c = ARM_GICV3_COMMON_GET_CLASS(s);
86
87 gicv3_gicd_no_migration_shift_bug_post_load(s);
88
89 if (c->post_load) {
90 c->post_load(s);
91 }
92 return 0;
93}
94
95static bool virt_state_needed(void *opaque)
96{
97 GICv3CPUState *cs = opaque;
98
99 return cs->num_list_regs != 0;
100}
101
102static const VMStateDescription vmstate_gicv3_cpu_virt = {
103 .name = "arm_gicv3_cpu/virt",
104 .version_id = 1,
105 .minimum_version_id = 1,
106 .needed = virt_state_needed,
107 .fields = (VMStateField[]) {
108 VMSTATE_UINT64_2DARRAY(ich_apr, GICv3CPUState, 3, 4),
109 VMSTATE_UINT64(ich_hcr_el2, GICv3CPUState),
110 VMSTATE_UINT64_ARRAY(ich_lr_el2, GICv3CPUState, GICV3_LR_MAX),
111 VMSTATE_UINT64(ich_vmcr_el2, GICv3CPUState),
112 VMSTATE_END_OF_LIST()
113 }
114};
115
116static int vmstate_gicv3_cpu_pre_load(void *opaque)
117{
118 GICv3CPUState *cs = opaque;
119
120
121
122
123
124
125 cs->icc_sre_el1 = 0x7;
126 return 0;
127}
128
129static bool icc_sre_el1_reg_needed(void *opaque)
130{
131 GICv3CPUState *cs = opaque;
132
133 return cs->icc_sre_el1 != 7;
134}
135
136const VMStateDescription vmstate_gicv3_cpu_sre_el1 = {
137 .name = "arm_gicv3_cpu/sre_el1",
138 .version_id = 1,
139 .minimum_version_id = 1,
140 .needed = icc_sre_el1_reg_needed,
141 .fields = (VMStateField[]) {
142 VMSTATE_UINT64(icc_sre_el1, GICv3CPUState),
143 VMSTATE_END_OF_LIST()
144 }
145};
146
147static const VMStateDescription vmstate_gicv3_cpu = {
148 .name = "arm_gicv3_cpu",
149 .version_id = 1,
150 .minimum_version_id = 1,
151 .pre_load = vmstate_gicv3_cpu_pre_load,
152 .fields = (VMStateField[]) {
153 VMSTATE_UINT32(level, GICv3CPUState),
154 VMSTATE_UINT32(gicr_ctlr, GICv3CPUState),
155 VMSTATE_UINT32_ARRAY(gicr_statusr, GICv3CPUState, 2),
156 VMSTATE_UINT32(gicr_waker, GICv3CPUState),
157 VMSTATE_UINT64(gicr_propbaser, GICv3CPUState),
158 VMSTATE_UINT64(gicr_pendbaser, GICv3CPUState),
159 VMSTATE_UINT32(gicr_igroupr0, GICv3CPUState),
160 VMSTATE_UINT32(gicr_ienabler0, GICv3CPUState),
161 VMSTATE_UINT32(gicr_ipendr0, GICv3CPUState),
162 VMSTATE_UINT32(gicr_iactiver0, GICv3CPUState),
163 VMSTATE_UINT32(edge_trigger, GICv3CPUState),
164 VMSTATE_UINT32(gicr_igrpmodr0, GICv3CPUState),
165 VMSTATE_UINT32(gicr_nsacr, GICv3CPUState),
166 VMSTATE_UINT8_ARRAY(gicr_ipriorityr, GICv3CPUState, GIC_INTERNAL),
167 VMSTATE_UINT64_ARRAY(icc_ctlr_el1, GICv3CPUState, 2),
168 VMSTATE_UINT64(icc_pmr_el1, GICv3CPUState),
169 VMSTATE_UINT64_ARRAY(icc_bpr, GICv3CPUState, 3),
170 VMSTATE_UINT64_2DARRAY(icc_apr, GICv3CPUState, 3, 4),
171 VMSTATE_UINT64_ARRAY(icc_igrpen, GICv3CPUState, 3),
172 VMSTATE_UINT64(icc_ctlr_el3, GICv3CPUState),
173 VMSTATE_END_OF_LIST()
174 },
175 .subsections = (const VMStateDescription * []) {
176 &vmstate_gicv3_cpu_virt,
177 &vmstate_gicv3_cpu_sre_el1,
178 NULL
179 }
180};
181
182static int gicv3_pre_load(void *opaque)
183{
184 GICv3State *cs = opaque;
185
186
187
188
189
190
191
192
193
194
195
196
197 if (kvm_enabled()) {
198 cs->gicd_no_migration_shift_bug = false;
199 }
200
201 return 0;
202}
203
204static bool needed_always(void *opaque)
205{
206 return true;
207}
208
209const VMStateDescription vmstate_gicv3_gicd_no_migration_shift_bug = {
210 .name = "arm_gicv3/gicd_no_migration_shift_bug",
211 .version_id = 1,
212 .minimum_version_id = 1,
213 .needed = needed_always,
214 .fields = (VMStateField[]) {
215 VMSTATE_BOOL(gicd_no_migration_shift_bug, GICv3State),
216 VMSTATE_END_OF_LIST()
217 }
218};
219
220static const VMStateDescription vmstate_gicv3 = {
221 .name = "arm_gicv3",
222 .version_id = 1,
223 .minimum_version_id = 1,
224 .pre_load = gicv3_pre_load,
225 .pre_save = gicv3_pre_save,
226 .post_load = gicv3_post_load,
227 .priority = MIG_PRI_GICV3,
228 .fields = (VMStateField[]) {
229 VMSTATE_UINT32(gicd_ctlr, GICv3State),
230 VMSTATE_UINT32_ARRAY(gicd_statusr, GICv3State, 2),
231 VMSTATE_UINT32_ARRAY(group, GICv3State, GICV3_BMP_SIZE),
232 VMSTATE_UINT32_ARRAY(grpmod, GICv3State, GICV3_BMP_SIZE),
233 VMSTATE_UINT32_ARRAY(enabled, GICv3State, GICV3_BMP_SIZE),
234 VMSTATE_UINT32_ARRAY(pending, GICv3State, GICV3_BMP_SIZE),
235 VMSTATE_UINT32_ARRAY(active, GICv3State, GICV3_BMP_SIZE),
236 VMSTATE_UINT32_ARRAY(level, GICv3State, GICV3_BMP_SIZE),
237 VMSTATE_UINT32_ARRAY(edge_trigger, GICv3State, GICV3_BMP_SIZE),
238 VMSTATE_UINT8_ARRAY(gicd_ipriority, GICv3State, GICV3_MAXIRQ),
239 VMSTATE_UINT64_ARRAY(gicd_irouter, GICv3State, GICV3_MAXIRQ),
240 VMSTATE_UINT32_ARRAY(gicd_nsacr, GICv3State,
241 DIV_ROUND_UP(GICV3_MAXIRQ, 16)),
242 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(cpu, GICv3State, num_cpu,
243 vmstate_gicv3_cpu, GICv3CPUState),
244 VMSTATE_END_OF_LIST()
245 },
246 .subsections = (const VMStateDescription * []) {
247 &vmstate_gicv3_gicd_no_migration_shift_bug,
248 NULL
249 }
250};
251
252void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler,
253 const MemoryRegionOps *ops)
254{
255 SysBusDevice *sbd = SYS_BUS_DEVICE(s);
256 int i;
257 int cpuidx;
258
259
260
261
262
263
264
265
266 i = s->num_irq - GIC_INTERNAL + GIC_INTERNAL * s->num_cpu;
267 qdev_init_gpio_in(DEVICE(s), handler, i);
268
269 for (i = 0; i < s->num_cpu; i++) {
270 sysbus_init_irq(sbd, &s->cpu[i].parent_irq);
271 }
272 for (i = 0; i < s->num_cpu; i++) {
273 sysbus_init_irq(sbd, &s->cpu[i].parent_fiq);
274 }
275 for (i = 0; i < s->num_cpu; i++) {
276 sysbus_init_irq(sbd, &s->cpu[i].parent_virq);
277 }
278 for (i = 0; i < s->num_cpu; i++) {
279 sysbus_init_irq(sbd, &s->cpu[i].parent_vfiq);
280 }
281
282 memory_region_init_io(&s->iomem_dist, OBJECT(s), ops, s,
283 "gicv3_dist", 0x10000);
284 sysbus_init_mmio(sbd, &s->iomem_dist);
285
286 s->redist_regions = g_new0(GICv3RedistRegion, s->nb_redist_regions);
287 cpuidx = 0;
288 for (i = 0; i < s->nb_redist_regions; i++) {
289 char *name = g_strdup_printf("gicv3_redist_region[%d]", i);
290 GICv3RedistRegion *region = &s->redist_regions[i];
291
292 region->gic = s;
293 region->cpuidx = cpuidx;
294 cpuidx += s->redist_region_count[i];
295
296 memory_region_init_io(®ion->iomem, OBJECT(s),
297 ops ? &ops[1] : NULL, region, name,
298 s->redist_region_count[i] * GICV3_REDIST_SIZE);
299 sysbus_init_mmio(sbd, ®ion->iomem);
300 g_free(name);
301 }
302}
303
304static void arm_gicv3_common_realize(DeviceState *dev, Error **errp)
305{
306 GICv3State *s = ARM_GICV3_COMMON(dev);
307 int i, rdist_capacity, cpuidx;
308
309
310
311
312
313
314 if (s->revision != 3) {
315 error_setg(errp, "unsupported GIC revision %d", s->revision);
316 return;
317 }
318
319 if (s->num_irq > GICV3_MAXIRQ) {
320 error_setg(errp,
321 "requested %u interrupt lines exceeds GIC maximum %d",
322 s->num_irq, GICV3_MAXIRQ);
323 return;
324 }
325 if (s->num_irq < GIC_INTERNAL) {
326 error_setg(errp,
327 "requested %u interrupt lines is below GIC minimum %d",
328 s->num_irq, GIC_INTERNAL);
329 return;
330 }
331
332
333
334
335
336
337 if (s->num_irq % 32) {
338 error_setg(errp,
339 "%d interrupt lines unsupported: not divisible by 32",
340 s->num_irq);
341 return;
342 }
343
344 if (s->lpi_enable && !s->dma) {
345 error_setg(errp, "Redist-ITS: Guest 'sysmem' reference link not set");
346 return;
347 }
348
349 rdist_capacity = 0;
350 for (i = 0; i < s->nb_redist_regions; i++) {
351 rdist_capacity += s->redist_region_count[i];
352 }
353 if (rdist_capacity < s->num_cpu) {
354 error_setg(errp, "Capacity of the redist regions(%d) "
355 "is less than number of vcpus(%d)",
356 rdist_capacity, s->num_cpu);
357 return;
358 }
359
360 s->cpu = g_new0(GICv3CPUState, s->num_cpu);
361
362 for (i = 0; i < s->num_cpu; i++) {
363 CPUState *cpu = qemu_get_cpu(i);
364 uint64_t cpu_affid;
365
366 s->cpu[i].cpu = cpu;
367 s->cpu[i].gic = s;
368
369 gicv3_set_gicv3state(cpu, &s->cpu[i]);
370
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381
382
383 cpu_affid = object_property_get_uint(OBJECT(cpu), "mp-affinity", NULL);
384
385
386
387
388 cpu_affid = ((cpu_affid & 0xFF00000000ULL) >> 8) |
389 (cpu_affid & 0xFFFFFF);
390 s->cpu[i].gicr_typer = (cpu_affid << 32) |
391 (1 << 24) |
392 (i << 8);
393
394 if (s->lpi_enable) {
395 s->cpu[i].gicr_typer |= GICR_TYPER_PLPIS;
396 }
397 }
398
399
400
401
402
403 cpuidx = 0;
404 for (i = 0; i < s->nb_redist_regions; i++) {
405 cpuidx += s->redist_region_count[i];
406 s->cpu[cpuidx - 1].gicr_typer |= GICR_TYPER_LAST;
407 }
408}
409
410static void arm_gicv3_finalize(Object *obj)
411{
412 GICv3State *s = ARM_GICV3_COMMON(obj);
413
414 g_free(s->redist_region_count);
415}
416
417static void arm_gicv3_common_reset(DeviceState *dev)
418{
419 GICv3State *s = ARM_GICV3_COMMON(dev);
420 int i;
421
422 for (i = 0; i < s->num_cpu; i++) {
423 GICv3CPUState *cs = &s->cpu[i];
424
425 cs->level = 0;
426 cs->gicr_ctlr = 0;
427 cs->gicr_statusr[GICV3_S] = 0;
428 cs->gicr_statusr[GICV3_NS] = 0;
429 cs->gicr_waker = GICR_WAKER_ProcessorSleep | GICR_WAKER_ChildrenAsleep;
430 cs->gicr_propbaser = 0;
431 cs->gicr_pendbaser = 0;
432
433
434
435
436
437 if (s->irq_reset_nonsecure) {
438 cs->gicr_igroupr0 = 0xffffffff;
439 } else {
440 cs->gicr_igroupr0 = 0;
441 }
442
443 cs->gicr_ienabler0 = 0;
444 cs->gicr_ipendr0 = 0;
445 cs->gicr_iactiver0 = 0;
446 cs->edge_trigger = 0xffff;
447 cs->gicr_igrpmodr0 = 0;
448 cs->gicr_nsacr = 0;
449 memset(cs->gicr_ipriorityr, 0, sizeof(cs->gicr_ipriorityr));
450
451 cs->hppi.prio = 0xff;
452 cs->hpplpi.prio = 0xff;
453
454
455
456
457 }
458
459
460 if (s->security_extn) {
461 s->gicd_ctlr = GICD_CTLR_ARE_S | GICD_CTLR_ARE_NS;
462 } else {
463 s->gicd_ctlr = GICD_CTLR_DS | GICD_CTLR_ARE;
464 }
465
466 s->gicd_statusr[GICV3_S] = 0;
467 s->gicd_statusr[GICV3_NS] = 0;
468
469 memset(s->group, 0, sizeof(s->group));
470 memset(s->grpmod, 0, sizeof(s->grpmod));
471 memset(s->enabled, 0, sizeof(s->enabled));
472 memset(s->pending, 0, sizeof(s->pending));
473 memset(s->active, 0, sizeof(s->active));
474 memset(s->level, 0, sizeof(s->level));
475 memset(s->edge_trigger, 0, sizeof(s->edge_trigger));
476 memset(s->gicd_ipriority, 0, sizeof(s->gicd_ipriority));
477 memset(s->gicd_irouter, 0, sizeof(s->gicd_irouter));
478 memset(s->gicd_nsacr, 0, sizeof(s->gicd_nsacr));
479
480
481
482
483
484
485 gicv3_cache_all_target_cpustates(s);
486
487 if (s->irq_reset_nonsecure) {
488
489
490
491
492
493 for (i = GIC_INTERNAL; i < s->num_irq; i++) {
494 gicv3_gicd_group_set(s, i);
495 }
496 }
497 s->gicd_no_migration_shift_bug = true;
498}
499
500static void arm_gic_common_linux_init(ARMLinuxBootIf *obj,
501 bool secure_boot)
502{
503 GICv3State *s = ARM_GICV3_COMMON(obj);
504
505 if (s->security_extn && !secure_boot) {
506
507
508
509
510
511
512
513 s->irq_reset_nonsecure = true;
514 }
515}
516
517static Property arm_gicv3_common_properties[] = {
518 DEFINE_PROP_UINT32("num-cpu", GICv3State, num_cpu, 1),
519 DEFINE_PROP_UINT32("num-irq", GICv3State, num_irq, 32),
520 DEFINE_PROP_UINT32("revision", GICv3State, revision, 3),
521 DEFINE_PROP_BOOL("has-lpi", GICv3State, lpi_enable, 0),
522 DEFINE_PROP_BOOL("has-security-extensions", GICv3State, security_extn, 0),
523 DEFINE_PROP_ARRAY("redist-region-count", GICv3State, nb_redist_regions,
524 redist_region_count, qdev_prop_uint32, uint32_t),
525 DEFINE_PROP_LINK("sysmem", GICv3State, dma, TYPE_MEMORY_REGION,
526 MemoryRegion *),
527 DEFINE_PROP_END_OF_LIST(),
528};
529
530static void arm_gicv3_common_class_init(ObjectClass *klass, void *data)
531{
532 DeviceClass *dc = DEVICE_CLASS(klass);
533 ARMLinuxBootIfClass *albifc = ARM_LINUX_BOOT_IF_CLASS(klass);
534
535 dc->reset = arm_gicv3_common_reset;
536 dc->realize = arm_gicv3_common_realize;
537 device_class_set_props(dc, arm_gicv3_common_properties);
538 dc->vmsd = &vmstate_gicv3;
539 albifc->arm_linux_init = arm_gic_common_linux_init;
540}
541
542static const TypeInfo arm_gicv3_common_type = {
543 .name = TYPE_ARM_GICV3_COMMON,
544 .parent = TYPE_SYS_BUS_DEVICE,
545 .instance_size = sizeof(GICv3State),
546 .class_size = sizeof(ARMGICv3CommonClass),
547 .class_init = arm_gicv3_common_class_init,
548 .instance_finalize = arm_gicv3_finalize,
549 .abstract = true,
550 .interfaces = (InterfaceInfo []) {
551 { TYPE_ARM_LINUX_BOOT_IF },
552 { },
553 },
554};
555
556static void register_types(void)
557{
558 type_register_static(&arm_gicv3_common_type);
559}
560
561type_init(register_types)
562