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11
12#include "qemu/osdep.h"
13#include "qemu/log.h"
14#include "trace.h"
15#include "gicv3_internal.h"
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32typedef uint32_t maskfn(GICv3State *s, int irq);
33
34static uint32_t mask_nsacr_ge1(GICv3State *s, int irq)
35{
36
37 uint64_t raw_nsacr = s->gicd_nsacr[irq / 16 + 1];
38
39 raw_nsacr = raw_nsacr << 32 | s->gicd_nsacr[irq / 16];
40 raw_nsacr = (raw_nsacr >> 1) | raw_nsacr;
41 return half_unshuffle64(raw_nsacr);
42}
43
44static uint32_t mask_nsacr_ge2(GICv3State *s, int irq)
45{
46
47 uint64_t raw_nsacr = s->gicd_nsacr[irq / 16 + 1];
48
49 raw_nsacr = raw_nsacr << 32 | s->gicd_nsacr[irq / 16];
50 raw_nsacr = raw_nsacr >> 1;
51 return half_unshuffle64(raw_nsacr);
52}
53
54
55
56
57
58
59static uint32_t mask_group_and_nsacr(GICv3State *s, MemTxAttrs attrs,
60 maskfn *maskfn, int irq)
61{
62
63
64
65
66 uint32_t mask;
67
68 if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) {
69
70
71
72 mask = *gic_bmp_ptr32(s->group, irq);
73 if (maskfn) {
74 mask |= maskfn(s, irq);
75 }
76 return mask;
77 }
78 return 0xFFFFFFFFU;
79}
80
81static int gicd_ns_access(GICv3State *s, int irq)
82{
83
84
85
86 if (irq < GIC_INTERNAL || irq >= s->num_irq) {
87 return 0;
88 }
89 return extract32(s->gicd_nsacr[irq / 16], (irq % 16) * 2, 2);
90}
91
92static void gicd_write_set_bitmap_reg(GICv3State *s, MemTxAttrs attrs,
93 uint32_t *bmp,
94 maskfn *maskfn,
95 int offset, uint32_t val)
96{
97
98
99
100
101
102
103
104
105
106 int irq = offset * 8;
107
108 if (irq < GIC_INTERNAL || irq >= s->num_irq) {
109 return;
110 }
111 val &= mask_group_and_nsacr(s, attrs, maskfn, irq);
112 *gic_bmp_ptr32(bmp, irq) |= val;
113 gicv3_update(s, irq, 32);
114}
115
116static void gicd_write_clear_bitmap_reg(GICv3State *s, MemTxAttrs attrs,
117 uint32_t *bmp,
118 maskfn *maskfn,
119 int offset, uint32_t val)
120{
121
122
123
124
125
126
127
128
129
130 int irq = offset * 8;
131
132 if (irq < GIC_INTERNAL || irq >= s->num_irq) {
133 return;
134 }
135 val &= mask_group_and_nsacr(s, attrs, maskfn, irq);
136 *gic_bmp_ptr32(bmp, irq) &= ~val;
137 gicv3_update(s, irq, 32);
138}
139
140static uint32_t gicd_read_bitmap_reg(GICv3State *s, MemTxAttrs attrs,
141 uint32_t *bmp,
142 maskfn *maskfn,
143 int offset)
144{
145
146
147
148
149
150
151
152
153 int irq = offset * 8;
154 uint32_t val;
155
156 if (irq < GIC_INTERNAL || irq >= s->num_irq) {
157 return 0;
158 }
159 val = *gic_bmp_ptr32(bmp, irq);
160 if (bmp == s->pending) {
161
162
163
164
165 uint32_t edge = *gic_bmp_ptr32(s->edge_trigger, irq);
166 uint32_t level = *gic_bmp_ptr32(s->level, irq);
167 val |= (~edge & level);
168 }
169 val &= mask_group_and_nsacr(s, attrs, maskfn, irq);
170 return val;
171}
172
173static uint8_t gicd_read_ipriorityr(GICv3State *s, MemTxAttrs attrs, int irq)
174{
175
176
177
178
179 uint32_t prio;
180
181 if (irq < GIC_INTERNAL || irq >= s->num_irq) {
182 return 0;
183 }
184
185 prio = s->gicd_ipriority[irq];
186
187 if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) {
188 if (!gicv3_gicd_group_test(s, irq)) {
189
190 return 0;
191 }
192
193 prio = (prio << 1) & 0xff;
194 }
195 return prio;
196}
197
198static void gicd_write_ipriorityr(GICv3State *s, MemTxAttrs attrs, int irq,
199 uint8_t value)
200{
201
202
203
204
205 if (irq < GIC_INTERNAL || irq >= s->num_irq) {
206 return;
207 }
208
209 if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) {
210 if (!gicv3_gicd_group_test(s, irq)) {
211
212 return;
213 }
214
215 value = 0x80 | (value >> 1);
216 }
217 s->gicd_ipriority[irq] = value;
218}
219
220static uint64_t gicd_read_irouter(GICv3State *s, MemTxAttrs attrs, int irq)
221{
222
223
224
225 if (irq < GIC_INTERNAL || irq >= s->num_irq) {
226 return 0;
227 }
228
229 if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) {
230
231 if (!gicv3_gicd_group_test(s, irq)) {
232 if (gicd_ns_access(s, irq) != 3) {
233 return 0;
234 }
235 }
236 }
237
238 return s->gicd_irouter[irq];
239}
240
241static void gicd_write_irouter(GICv3State *s, MemTxAttrs attrs, int irq,
242 uint64_t val)
243{
244
245
246
247 if (irq < GIC_INTERNAL || irq >= s->num_irq) {
248 return;
249 }
250
251 if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) {
252
253 if (!gicv3_gicd_group_test(s, irq)) {
254 if (gicd_ns_access(s, irq) != 3) {
255 return;
256 }
257 }
258 }
259
260 s->gicd_irouter[irq] = val;
261 gicv3_cache_target_cpustate(s, irq);
262 gicv3_update(s, irq, 1);
263}
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278static bool gicd_readb(GICv3State *s, hwaddr offset,
279 uint64_t *data, MemTxAttrs attrs)
280{
281
282 switch (offset) {
283 case GICD_CPENDSGIR ... GICD_CPENDSGIR + 0xf:
284 case GICD_SPENDSGIR ... GICD_SPENDSGIR + 0xf:
285 case GICD_ITARGETSR ... GICD_ITARGETSR + 0x3ff:
286
287
288
289 return true;
290 case GICD_IPRIORITYR ... GICD_IPRIORITYR + 0x3ff:
291 *data = gicd_read_ipriorityr(s, attrs, offset - GICD_IPRIORITYR);
292 return true;
293 default:
294 return false;
295 }
296}
297
298static bool gicd_writeb(GICv3State *s, hwaddr offset,
299 uint64_t value, MemTxAttrs attrs)
300{
301
302 switch (offset) {
303 case GICD_CPENDSGIR ... GICD_CPENDSGIR + 0xf:
304 case GICD_SPENDSGIR ... GICD_SPENDSGIR + 0xf:
305 case GICD_ITARGETSR ... GICD_ITARGETSR + 0x3ff:
306
307
308
309 return true;
310 case GICD_IPRIORITYR ... GICD_IPRIORITYR + 0x3ff:
311 {
312 int irq = offset - GICD_IPRIORITYR;
313
314 if (irq < GIC_INTERNAL || irq >= s->num_irq) {
315 return true;
316 }
317 gicd_write_ipriorityr(s, attrs, irq, value);
318 gicv3_update(s, irq, 1);
319 return true;
320 }
321 default:
322 return false;
323 }
324}
325
326static bool gicd_readw(GICv3State *s, hwaddr offset,
327 uint64_t *data, MemTxAttrs attrs)
328{
329
330
331
332
333
334
335 return false;
336}
337
338static bool gicd_writew(GICv3State *s, hwaddr offset,
339 uint64_t value, MemTxAttrs attrs)
340{
341
342
343
344
345
346
347 return false;
348}
349
350static bool gicd_readl(GICv3State *s, hwaddr offset,
351 uint64_t *data, MemTxAttrs attrs)
352{
353
354
355
356
357
358 switch (offset) {
359 case GICD_CTLR:
360 if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) {
361
362
363
364
365
366
367
368
369
370
371
372
373 *data = s->gicd_ctlr & (GICD_CTLR_ARE_S |
374 GICD_CTLR_EN_GRP1NS |
375 GICD_CTLR_RWP);
376 } else {
377 *data = s->gicd_ctlr;
378 }
379 return true;
380 case GICD_TYPER:
381 {
382
383
384
385
386
387
388
389
390
391
392
393
394
395 int itlinesnumber = ((s->num_irq - GIC_INTERNAL) / 32) - 1;
396
397
398
399
400
401 bool sec_extn = !(s->gicd_ctlr & GICD_CTLR_DS);
402
403 *data = (1 << 25) | (1 << 24) | (sec_extn << 10) |
404 (s->lpi_enable << GICD_TYPER_LPIS_SHIFT) |
405 (0xf << 19) | itlinesnumber;
406 return true;
407 }
408 case GICD_IIDR:
409
410
411
412 *data = gicv3_iidr();
413 return true;
414 case GICD_STATUSR:
415
416
417
418 *data = 0;
419 return true;
420 case GICD_IGROUPR ... GICD_IGROUPR + 0x7f:
421 {
422 int irq;
423
424 if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) {
425 *data = 0;
426 return true;
427 }
428
429 irq = (offset - GICD_IGROUPR) * 8;
430 if (irq < GIC_INTERNAL || irq >= s->num_irq) {
431 *data = 0;
432 return true;
433 }
434 *data = *gic_bmp_ptr32(s->group, irq);
435 return true;
436 }
437 case GICD_ISENABLER ... GICD_ISENABLER + 0x7f:
438 *data = gicd_read_bitmap_reg(s, attrs, s->enabled, NULL,
439 offset - GICD_ISENABLER);
440 return true;
441 case GICD_ICENABLER ... GICD_ICENABLER + 0x7f:
442 *data = gicd_read_bitmap_reg(s, attrs, s->enabled, NULL,
443 offset - GICD_ICENABLER);
444 return true;
445 case GICD_ISPENDR ... GICD_ISPENDR + 0x7f:
446 *data = gicd_read_bitmap_reg(s, attrs, s->pending, mask_nsacr_ge1,
447 offset - GICD_ISPENDR);
448 return true;
449 case GICD_ICPENDR ... GICD_ICPENDR + 0x7f:
450 *data = gicd_read_bitmap_reg(s, attrs, s->pending, mask_nsacr_ge2,
451 offset - GICD_ICPENDR);
452 return true;
453 case GICD_ISACTIVER ... GICD_ISACTIVER + 0x7f:
454 *data = gicd_read_bitmap_reg(s, attrs, s->active, mask_nsacr_ge2,
455 offset - GICD_ISACTIVER);
456 return true;
457 case GICD_ICACTIVER ... GICD_ICACTIVER + 0x7f:
458 *data = gicd_read_bitmap_reg(s, attrs, s->active, mask_nsacr_ge2,
459 offset - GICD_ICACTIVER);
460 return true;
461 case GICD_IPRIORITYR ... GICD_IPRIORITYR + 0x3ff:
462 {
463 int i, irq = offset - GICD_IPRIORITYR;
464 uint32_t value = 0;
465
466 for (i = irq + 3; i >= irq; i--) {
467 value <<= 8;
468 value |= gicd_read_ipriorityr(s, attrs, i);
469 }
470 *data = value;
471 return true;
472 }
473 case GICD_ITARGETSR ... GICD_ITARGETSR + 0x3ff:
474
475 *data = 0;
476 return true;
477 case GICD_ICFGR ... GICD_ICFGR + 0xff:
478 {
479
480 int irq = (offset - GICD_ICFGR) * 4;
481 uint32_t value = 0;
482
483 if (irq < GIC_INTERNAL || irq >= s->num_irq) {
484 *data = 0;
485 return true;
486 }
487
488
489
490
491
492 value = *gic_bmp_ptr32(s->edge_trigger, irq & ~0x1f);
493 value &= mask_group_and_nsacr(s, attrs, NULL, irq & ~0x1f);
494 value = extract32(value, (irq & 0x1f) ? 16 : 0, 16);
495 value = half_shuffle32(value) << 1;
496 *data = value;
497 return true;
498 }
499 case GICD_IGRPMODR ... GICD_IGRPMODR + 0xff:
500 {
501 int irq;
502
503 if ((s->gicd_ctlr & GICD_CTLR_DS) || !attrs.secure) {
504
505
506
507 *data = 0;
508 return true;
509 }
510
511 irq = (offset - GICD_IGRPMODR) * 8;
512 if (irq < GIC_INTERNAL || irq >= s->num_irq) {
513 *data = 0;
514 return true;
515 }
516 *data = *gic_bmp_ptr32(s->grpmod, irq);
517 return true;
518 }
519 case GICD_NSACR ... GICD_NSACR + 0xff:
520 {
521
522 int irq = (offset - GICD_NSACR) * 4;
523
524 if (irq < GIC_INTERNAL || irq >= s->num_irq) {
525 *data = 0;
526 return true;
527 }
528
529 if ((s->gicd_ctlr & GICD_CTLR_DS) || !attrs.secure) {
530
531
532
533 *data = 0;
534 return true;
535 }
536
537 *data = s->gicd_nsacr[irq / 16];
538 return true;
539 }
540 case GICD_CPENDSGIR ... GICD_CPENDSGIR + 0xf:
541 case GICD_SPENDSGIR ... GICD_SPENDSGIR + 0xf:
542
543 *data = 0;
544 return true;
545 case GICD_IROUTER ... GICD_IROUTER + 0x1fdf:
546 {
547 uint64_t r;
548 int irq = (offset - GICD_IROUTER) / 8;
549
550 r = gicd_read_irouter(s, attrs, irq);
551 if (offset & 7) {
552 *data = r >> 32;
553 } else {
554 *data = (uint32_t)r;
555 }
556 return true;
557 }
558 case GICD_IDREGS ... GICD_IDREGS + 0x2f:
559
560 *data = gicv3_idreg(offset - GICD_IDREGS);
561 return true;
562 case GICD_SGIR:
563
564 qemu_log_mask(LOG_GUEST_ERROR,
565 "%s: invalid guest read from WO register at offset "
566 TARGET_FMT_plx "\n", __func__, offset);
567 *data = 0;
568 return true;
569 default:
570 return false;
571 }
572}
573
574static bool gicd_writel(GICv3State *s, hwaddr offset,
575 uint64_t value, MemTxAttrs attrs)
576{
577
578
579
580
581 switch (offset) {
582 case GICD_CTLR:
583 {
584 uint32_t mask;
585
586 if (s->gicd_ctlr & GICD_CTLR_DS) {
587
588
589
590
591 mask = GICD_CTLR_EN_GRP0 | GICD_CTLR_EN_GRP1NS;
592 } else {
593 if (attrs.secure) {
594
595
596
597
598
599
600 mask = GICD_CTLR_DS | GICD_CTLR_EN_GRP0 | GICD_CTLR_EN_GRP1_ALL;
601 } else {
602
603
604
605
606 mask = GICD_CTLR_EN_GRP1NS;
607 }
608 }
609 s->gicd_ctlr = (s->gicd_ctlr & ~mask) | (value & mask);
610 if (value & mask & GICD_CTLR_DS) {
611
612
613
614
615
616 s->gicd_ctlr &= ~(GICD_CTLR_EN_GRP1S | GICD_CTLR_ARE_NS);
617 }
618 gicv3_full_update(s);
619 return true;
620 }
621 case GICD_STATUSR:
622
623 return true;
624 case GICD_IGROUPR ... GICD_IGROUPR + 0x7f:
625 {
626 int irq;
627
628 if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) {
629 return true;
630 }
631
632 irq = (offset - GICD_IGROUPR) * 8;
633 if (irq < GIC_INTERNAL || irq >= s->num_irq) {
634 return true;
635 }
636 *gic_bmp_ptr32(s->group, irq) = value;
637 gicv3_update(s, irq, 32);
638 return true;
639 }
640 case GICD_ISENABLER ... GICD_ISENABLER + 0x7f:
641 gicd_write_set_bitmap_reg(s, attrs, s->enabled, NULL,
642 offset - GICD_ISENABLER, value);
643 return true;
644 case GICD_ICENABLER ... GICD_ICENABLER + 0x7f:
645 gicd_write_clear_bitmap_reg(s, attrs, s->enabled, NULL,
646 offset - GICD_ICENABLER, value);
647 return true;
648 case GICD_ISPENDR ... GICD_ISPENDR + 0x7f:
649 gicd_write_set_bitmap_reg(s, attrs, s->pending, mask_nsacr_ge1,
650 offset - GICD_ISPENDR, value);
651 return true;
652 case GICD_ICPENDR ... GICD_ICPENDR + 0x7f:
653 gicd_write_clear_bitmap_reg(s, attrs, s->pending, mask_nsacr_ge2,
654 offset - GICD_ICPENDR, value);
655 return true;
656 case GICD_ISACTIVER ... GICD_ISACTIVER + 0x7f:
657 gicd_write_set_bitmap_reg(s, attrs, s->active, NULL,
658 offset - GICD_ISACTIVER, value);
659 return true;
660 case GICD_ICACTIVER ... GICD_ICACTIVER + 0x7f:
661 gicd_write_clear_bitmap_reg(s, attrs, s->active, NULL,
662 offset - GICD_ICACTIVER, value);
663 return true;
664 case GICD_IPRIORITYR ... GICD_IPRIORITYR + 0x3ff:
665 {
666 int i, irq = offset - GICD_IPRIORITYR;
667
668 if (irq < GIC_INTERNAL || irq + 3 >= s->num_irq) {
669 return true;
670 }
671
672 for (i = irq; i < irq + 4; i++, value >>= 8) {
673 gicd_write_ipriorityr(s, attrs, i, value);
674 }
675 gicv3_update(s, irq, 4);
676 return true;
677 }
678 case GICD_ITARGETSR ... GICD_ITARGETSR + 0x3ff:
679
680 return true;
681 case GICD_ICFGR ... GICD_ICFGR + 0xff:
682 {
683
684 int irq = (offset - GICD_ICFGR) * 4;
685 uint32_t mask, oldval;
686
687 if (irq < GIC_INTERNAL || irq >= s->num_irq) {
688 return true;
689 }
690
691
692
693
694
695 value = half_unshuffle32(value >> 1);
696 mask = mask_group_and_nsacr(s, attrs, NULL, irq & ~0x1f);
697 if (irq & 0x1f) {
698 value <<= 16;
699 mask &= 0xffff0000U;
700 } else {
701 mask &= 0xffff;
702 }
703 oldval = *gic_bmp_ptr32(s->edge_trigger, (irq & ~0x1f));
704 value = (oldval & ~mask) | (value & mask);
705 *gic_bmp_ptr32(s->edge_trigger, irq & ~0x1f) = value;
706 return true;
707 }
708 case GICD_IGRPMODR ... GICD_IGRPMODR + 0xff:
709 {
710 int irq;
711
712 if ((s->gicd_ctlr & GICD_CTLR_DS) || !attrs.secure) {
713
714
715
716 return true;
717 }
718
719 irq = (offset - GICD_IGRPMODR) * 8;
720 if (irq < GIC_INTERNAL || irq >= s->num_irq) {
721 return true;
722 }
723 *gic_bmp_ptr32(s->grpmod, irq) = value;
724 gicv3_update(s, irq, 32);
725 return true;
726 }
727 case GICD_NSACR ... GICD_NSACR + 0xff:
728 {
729
730 int irq = (offset - GICD_NSACR) * 4;
731
732 if (irq < GIC_INTERNAL || irq >= s->num_irq) {
733 return true;
734 }
735
736 if ((s->gicd_ctlr & GICD_CTLR_DS) || !attrs.secure) {
737
738
739
740 return true;
741 }
742
743 s->gicd_nsacr[irq / 16] = value;
744
745 return true;
746 }
747 case GICD_SGIR:
748
749 return true;
750 case GICD_CPENDSGIR ... GICD_CPENDSGIR + 0xf:
751 case GICD_SPENDSGIR ... GICD_SPENDSGIR + 0xf:
752
753 return true;
754 case GICD_IROUTER ... GICD_IROUTER + 0x1fdf:
755 {
756 uint64_t r;
757 int irq = (offset - GICD_IROUTER) / 8;
758
759 if (irq < GIC_INTERNAL || irq >= s->num_irq) {
760 return true;
761 }
762
763
764 r = gicd_read_irouter(s, attrs, irq);
765 r = deposit64(r, (offset & 7) ? 32 : 0, 32, value);
766 gicd_write_irouter(s, attrs, irq, r);
767 return true;
768 }
769 case GICD_IDREGS ... GICD_IDREGS + 0x2f:
770 case GICD_TYPER:
771 case GICD_IIDR:
772
773 qemu_log_mask(LOG_GUEST_ERROR,
774 "%s: invalid guest write to RO register at offset "
775 TARGET_FMT_plx "\n", __func__, offset);
776 return true;
777 default:
778 return false;
779 }
780}
781
782static bool gicd_writeq(GICv3State *s, hwaddr offset,
783 uint64_t value, MemTxAttrs attrs)
784{
785
786 int irq;
787
788 switch (offset) {
789 case GICD_IROUTER ... GICD_IROUTER + 0x1fdf:
790 irq = (offset - GICD_IROUTER) / 8;
791 gicd_write_irouter(s, attrs, irq, value);
792 return true;
793 default:
794 return false;
795 }
796}
797
798static bool gicd_readq(GICv3State *s, hwaddr offset,
799 uint64_t *data, MemTxAttrs attrs)
800{
801
802 int irq;
803
804 switch (offset) {
805 case GICD_IROUTER ... GICD_IROUTER + 0x1fdf:
806 irq = (offset - GICD_IROUTER) / 8;
807 *data = gicd_read_irouter(s, attrs, irq);
808 return true;
809 default:
810 return false;
811 }
812}
813
814MemTxResult gicv3_dist_read(void *opaque, hwaddr offset, uint64_t *data,
815 unsigned size, MemTxAttrs attrs)
816{
817 GICv3State *s = (GICv3State *)opaque;
818 bool r;
819
820 switch (size) {
821 case 1:
822 r = gicd_readb(s, offset, data, attrs);
823 break;
824 case 2:
825 r = gicd_readw(s, offset, data, attrs);
826 break;
827 case 4:
828 r = gicd_readl(s, offset, data, attrs);
829 break;
830 case 8:
831 r = gicd_readq(s, offset, data, attrs);
832 break;
833 default:
834 r = false;
835 break;
836 }
837
838 if (!r) {
839 qemu_log_mask(LOG_GUEST_ERROR,
840 "%s: invalid guest read at offset " TARGET_FMT_plx
841 "size %u\n", __func__, offset, size);
842 trace_gicv3_dist_badread(offset, size, attrs.secure);
843
844
845
846
847
848 *data = 0;
849 } else {
850 trace_gicv3_dist_read(offset, *data, size, attrs.secure);
851 }
852 return MEMTX_OK;
853}
854
855MemTxResult gicv3_dist_write(void *opaque, hwaddr offset, uint64_t data,
856 unsigned size, MemTxAttrs attrs)
857{
858 GICv3State *s = (GICv3State *)opaque;
859 bool r;
860
861 switch (size) {
862 case 1:
863 r = gicd_writeb(s, offset, data, attrs);
864 break;
865 case 2:
866 r = gicd_writew(s, offset, data, attrs);
867 break;
868 case 4:
869 r = gicd_writel(s, offset, data, attrs);
870 break;
871 case 8:
872 r = gicd_writeq(s, offset, data, attrs);
873 break;
874 default:
875 r = false;
876 break;
877 }
878
879 if (!r) {
880 qemu_log_mask(LOG_GUEST_ERROR,
881 "%s: invalid guest write at offset " TARGET_FMT_plx
882 "size %u\n", __func__, offset, size);
883 trace_gicv3_dist_badwrite(offset, data, size, attrs.secure);
884
885
886
887
888
889 } else {
890 trace_gicv3_dist_write(offset, data, size, attrs.secure);
891 }
892 return MEMTX_OK;
893}
894
895void gicv3_dist_set_irq(GICv3State *s, int irq, int level)
896{
897
898 if (level == gicv3_gicd_level_test(s, irq)) {
899 return;
900 }
901
902 trace_gicv3_dist_set_irq(irq, level);
903
904 gicv3_gicd_level_replace(s, irq, level);
905
906 if (level) {
907
908 if (gicv3_gicd_edge_trigger_test(s, irq)) {
909 gicv3_gicd_pending_set(s, irq);
910 }
911 }
912
913 gicv3_update(s, irq, 1);
914}
915