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22#include "qemu/osdep.h"
23#include "qapi/error.h"
24#include "qemu/module.h"
25#include "migration/vmstate.h"
26#include "monitor/monitor.h"
27#include "hw/i386/ioapic.h"
28#include "hw/i386/ioapic_internal.h"
29#include "hw/intc/intc.h"
30#include "hw/sysbus.h"
31
32
33
34
35
36
37
38int ioapic_no;
39
40void ioapic_stat_update_irq(IOAPICCommonState *s, int irq, int level)
41{
42 if (level != s->irq_level[irq]) {
43 s->irq_level[irq] = level;
44 if (level == 1) {
45 s->irq_count[irq]++;
46 }
47 }
48}
49
50static bool ioapic_get_statistics(InterruptStatsProvider *obj,
51 uint64_t **irq_counts,
52 unsigned int *nb_irqs)
53{
54 IOAPICCommonState *s = IOAPIC_COMMON(obj);
55
56 *irq_counts = s->irq_count;
57 *nb_irqs = IOAPIC_NUM_PINS;
58
59 return true;
60}
61
62static void ioapic_irr_dump(Monitor *mon, const char *name, uint32_t bitmap)
63{
64 int i;
65
66 monitor_printf(mon, "%-10s ", name);
67 if (bitmap == 0) {
68 monitor_printf(mon, "(none)\n");
69 return;
70 }
71 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
72 if (bitmap & (1 << i)) {
73 monitor_printf(mon, "%-2u ", i);
74 }
75 }
76 monitor_printf(mon, "\n");
77}
78
79void ioapic_print_redtbl(Monitor *mon, IOAPICCommonState *s)
80{
81 static const char *delm_str[] = {
82 "fixed", "lowest", "SMI", "...", "NMI", "INIT", "...", "extINT"};
83 uint32_t remote_irr = 0;
84 int i;
85
86 monitor_printf(mon, "ioapic0: ver=0x%x id=0x%02x sel=0x%02x",
87 s->version, s->id, s->ioregsel);
88 if (s->ioregsel) {
89 monitor_printf(mon, " (redir[%u])\n",
90 (s->ioregsel - IOAPIC_REG_REDTBL_BASE) >> 1);
91 } else {
92 monitor_printf(mon, "\n");
93 }
94 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
95 uint64_t entry = s->ioredtbl[i];
96 uint32_t delm = (uint32_t)((entry & IOAPIC_LVT_DELIV_MODE) >>
97 IOAPIC_LVT_DELIV_MODE_SHIFT);
98 monitor_printf(mon, " pin %-2u 0x%016"PRIx64" dest=%"PRIx64
99 " vec=%-3"PRIu64" %s %-5s %-6s %-6s %s\n",
100 i, entry,
101 (entry >> IOAPIC_LVT_DEST_SHIFT) &
102 (entry & IOAPIC_LVT_DEST_MODE ? 0xff : 0xf),
103 entry & IOAPIC_VECTOR_MASK,
104 entry & IOAPIC_LVT_POLARITY ? "active-lo" : "active-hi",
105 entry & IOAPIC_LVT_TRIGGER_MODE ? "level" : "edge",
106 entry & IOAPIC_LVT_MASKED ? "masked" : "",
107 delm_str[delm],
108 entry & IOAPIC_LVT_DEST_MODE ? "logical" : "physical");
109
110 remote_irr |= entry & IOAPIC_LVT_TRIGGER_MODE ?
111 (entry & IOAPIC_LVT_REMOTE_IRR ? (1 << i) : 0) : 0;
112 }
113 ioapic_irr_dump(mon, " IRR", s->irr);
114 ioapic_irr_dump(mon, " Remote IRR", remote_irr);
115}
116
117void ioapic_reset_common(DeviceState *dev)
118{
119 IOAPICCommonState *s = IOAPIC_COMMON(dev);
120 int i;
121
122 s->id = 0;
123 s->ioregsel = 0;
124 s->irr = 0;
125 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
126 s->ioredtbl[i] = 1 << IOAPIC_LVT_MASKED_SHIFT;
127 }
128}
129
130static int ioapic_dispatch_pre_save(void *opaque)
131{
132 IOAPICCommonState *s = IOAPIC_COMMON(opaque);
133 IOAPICCommonClass *info = IOAPIC_COMMON_GET_CLASS(s);
134
135 if (info->pre_save) {
136 info->pre_save(s);
137 }
138
139 return 0;
140}
141
142static int ioapic_dispatch_post_load(void *opaque, int version_id)
143{
144 IOAPICCommonState *s = IOAPIC_COMMON(opaque);
145 IOAPICCommonClass *info = IOAPIC_COMMON_GET_CLASS(s);
146
147 if (info->post_load) {
148 info->post_load(s);
149 }
150 return 0;
151}
152
153static void ioapic_common_realize(DeviceState *dev, Error **errp)
154{
155 IOAPICCommonState *s = IOAPIC_COMMON(dev);
156 IOAPICCommonClass *info;
157
158 if (ioapic_no >= MAX_IOAPICS) {
159 error_setg(errp, "Only %d ioapics allowed", MAX_IOAPICS);
160 return;
161 }
162
163 info = IOAPIC_COMMON_GET_CLASS(s);
164 info->realize(dev, errp);
165
166 sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->io_memory);
167 ioapic_no++;
168}
169
170static void ioapic_print_info(InterruptStatsProvider *obj,
171 Monitor *mon)
172{
173 IOAPICCommonState *s = IOAPIC_COMMON(obj);
174
175 ioapic_dispatch_pre_save(s);
176 ioapic_print_redtbl(mon, s);
177}
178
179static const VMStateDescription vmstate_ioapic_common = {
180 .name = "ioapic",
181 .version_id = 3,
182 .minimum_version_id = 1,
183 .pre_save = ioapic_dispatch_pre_save,
184 .post_load = ioapic_dispatch_post_load,
185 .fields = (VMStateField[]) {
186 VMSTATE_UINT8(id, IOAPICCommonState),
187 VMSTATE_UINT8(ioregsel, IOAPICCommonState),
188 VMSTATE_UNUSED_V(2, 8),
189 VMSTATE_UINT32_V(irr, IOAPICCommonState, 2),
190 VMSTATE_UINT64_ARRAY(ioredtbl, IOAPICCommonState, IOAPIC_NUM_PINS),
191 VMSTATE_END_OF_LIST()
192 }
193};
194
195static void ioapic_common_class_init(ObjectClass *klass, void *data)
196{
197 DeviceClass *dc = DEVICE_CLASS(klass);
198 InterruptStatsProviderClass *ic = INTERRUPT_STATS_PROVIDER_CLASS(klass);
199
200 dc->realize = ioapic_common_realize;
201 dc->vmsd = &vmstate_ioapic_common;
202 ic->print_info = ioapic_print_info;
203 ic->get_statistics = ioapic_get_statistics;
204}
205
206static const TypeInfo ioapic_common_type = {
207 .name = TYPE_IOAPIC_COMMON,
208 .parent = TYPE_SYS_BUS_DEVICE,
209 .instance_size = sizeof(IOAPICCommonState),
210 .class_size = sizeof(IOAPICCommonClass),
211 .class_init = ioapic_common_class_init,
212 .abstract = true,
213 .interfaces = (InterfaceInfo[]) {
214 { TYPE_INTERRUPT_STATS_PROVIDER },
215 { }
216 },
217};
218
219static void ioapic_common_register_types(void)
220{
221 type_register_static(&ioapic_common_type);
222}
223
224type_init(ioapic_common_register_types)
225
