qemu/hw/intc/openpic_kvm.c
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   1/*
   2 * KVM in-kernel OpenPIC
   3 *
   4 * Copyright 2013 Freescale Semiconductor, Inc.
   5 *
   6 * Permission is hereby granted, free of charge, to any person obtaining a copy
   7 * of this software and associated documentation files (the "Software"), to deal
   8 * in the Software without restriction, including without limitation the rights
   9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10 * copies of the Software, and to permit persons to whom the Software is
  11 * furnished to do so, subject to the following conditions:
  12 *
  13 * The above copyright notice and this permission notice shall be included in
  14 * all copies or substantial portions of the Software.
  15 *
  16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22 * THE SOFTWARE.
  23 */
  24
  25#include "qemu/osdep.h"
  26#include "qapi/error.h"
  27#include "cpu.h"
  28#include <sys/ioctl.h>
  29#include "exec/address-spaces.h"
  30#include "hw/ppc/openpic.h"
  31#include "hw/ppc/openpic_kvm.h"
  32#include "hw/pci/msi.h"
  33#include "hw/qdev-properties.h"
  34#include "hw/sysbus.h"
  35#include "sysemu/kvm.h"
  36#include "qemu/log.h"
  37#include "qemu/module.h"
  38
  39#define GCR_RESET        0x80000000
  40
  41#define KVM_OPENPIC(obj) \
  42    OBJECT_CHECK(KVMOpenPICState, (obj), TYPE_KVM_OPENPIC)
  43
  44typedef struct KVMOpenPICState {
  45    /*< private >*/
  46    SysBusDevice parent_obj;
  47    /*< public >*/
  48
  49    MemoryRegion mem;
  50    MemoryListener mem_listener;
  51    uint32_t fd;
  52    uint32_t model;
  53    hwaddr mapped;
  54} KVMOpenPICState;
  55
  56static void kvm_openpic_set_irq(void *opaque, int n_IRQ, int level)
  57{
  58    kvm_set_irq(kvm_state, n_IRQ, level);
  59}
  60
  61static void kvm_openpic_write(void *opaque, hwaddr addr, uint64_t val,
  62                              unsigned size)
  63{
  64    KVMOpenPICState *opp = opaque;
  65    struct kvm_device_attr attr;
  66    uint32_t val32 = val;
  67    int ret;
  68
  69    attr.group = KVM_DEV_MPIC_GRP_REGISTER;
  70    attr.attr = addr;
  71    attr.addr = (uint64_t)(unsigned long)&val32;
  72
  73    ret = ioctl(opp->fd, KVM_SET_DEVICE_ATTR, &attr);
  74    if (ret < 0) {
  75        qemu_log_mask(LOG_UNIMP, "%s: %s %" PRIx64 "\n", __func__,
  76                      strerror(errno), attr.attr);
  77    }
  78}
  79
  80static void kvm_openpic_reset(DeviceState *d)
  81{
  82    KVMOpenPICState *opp = KVM_OPENPIC(d);
  83
  84    /* Trigger the GCR.RESET bit to reset the PIC */
  85    kvm_openpic_write(opp, 0x1020, GCR_RESET, sizeof(uint32_t));
  86}
  87
  88static uint64_t kvm_openpic_read(void *opaque, hwaddr addr, unsigned size)
  89{
  90    KVMOpenPICState *opp = opaque;
  91    struct kvm_device_attr attr;
  92    uint32_t val = 0xdeadbeef;
  93    int ret;
  94
  95    attr.group = KVM_DEV_MPIC_GRP_REGISTER;
  96    attr.attr = addr;
  97    attr.addr = (uint64_t)(unsigned long)&val;
  98
  99    ret = ioctl(opp->fd, KVM_GET_DEVICE_ATTR, &attr);
 100    if (ret < 0) {
 101        qemu_log_mask(LOG_UNIMP, "%s: %s %" PRIx64 "\n", __func__,
 102                      strerror(errno), attr.attr);
 103        return 0;
 104    }
 105
 106    return val;
 107}
 108
 109static const MemoryRegionOps kvm_openpic_mem_ops = {
 110    .write = kvm_openpic_write,
 111    .read  = kvm_openpic_read,
 112    .endianness = DEVICE_BIG_ENDIAN,
 113    .impl = {
 114        .min_access_size = 4,
 115        .max_access_size = 4,
 116    },
 117};
 118
 119static void kvm_openpic_region_add(MemoryListener *listener,
 120                                   MemoryRegionSection *section)
 121{
 122    KVMOpenPICState *opp = container_of(listener, KVMOpenPICState,
 123                                        mem_listener);
 124    struct kvm_device_attr attr;
 125    uint64_t reg_base;
 126    int ret;
 127
 128    /* Ignore events on regions that are not us */
 129    if (section->mr != &opp->mem) {
 130        return;
 131    }
 132
 133    if (opp->mapped) {
 134        /*
 135         * We can only map the MPIC once. Since we are already mapped,
 136         * the best we can do is ignore new maps.
 137         */
 138        return;
 139    }
 140
 141    reg_base = section->offset_within_address_space;
 142    opp->mapped = reg_base;
 143
 144    attr.group = KVM_DEV_MPIC_GRP_MISC;
 145    attr.attr = KVM_DEV_MPIC_BASE_ADDR;
 146    attr.addr = (uint64_t)(unsigned long)&reg_base;
 147
 148    ret = ioctl(opp->fd, KVM_SET_DEVICE_ATTR, &attr);
 149    if (ret < 0) {
 150        fprintf(stderr, "%s: %s %" PRIx64 "\n", __func__,
 151                strerror(errno), reg_base);
 152    }
 153}
 154
 155static void kvm_openpic_region_del(MemoryListener *listener,
 156                                   MemoryRegionSection *section)
 157{
 158    KVMOpenPICState *opp = container_of(listener, KVMOpenPICState,
 159                                        mem_listener);
 160    struct kvm_device_attr attr;
 161    uint64_t reg_base = 0;
 162    int ret;
 163
 164    /* Ignore events on regions that are not us */
 165    if (section->mr != &opp->mem) {
 166        return;
 167    }
 168
 169    if (section->offset_within_address_space != opp->mapped) {
 170        /*
 171         * We can only map the MPIC once. This mapping was a secondary
 172         * one that we couldn't fulfill. Ignore it.
 173         */
 174        return;
 175    }
 176    opp->mapped = 0;
 177
 178    attr.group = KVM_DEV_MPIC_GRP_MISC;
 179    attr.attr = KVM_DEV_MPIC_BASE_ADDR;
 180    attr.addr = (uint64_t)(unsigned long)&reg_base;
 181
 182    ret = ioctl(opp->fd, KVM_SET_DEVICE_ATTR, &attr);
 183    if (ret < 0) {
 184        fprintf(stderr, "%s: %s %" PRIx64 "\n", __func__,
 185                strerror(errno), reg_base);
 186    }
 187}
 188
 189static void kvm_openpic_init(Object *obj)
 190{
 191    KVMOpenPICState *opp = KVM_OPENPIC(obj);
 192
 193    memory_region_init_io(&opp->mem, OBJECT(opp), &kvm_openpic_mem_ops, opp,
 194                          "kvm-openpic", 0x40000);
 195}
 196
 197static void kvm_openpic_realize(DeviceState *dev, Error **errp)
 198{
 199    SysBusDevice *d = SYS_BUS_DEVICE(dev);
 200    KVMOpenPICState *opp = KVM_OPENPIC(dev);
 201    KVMState *s = kvm_state;
 202    int kvm_openpic_model;
 203    struct kvm_create_device cd = {0};
 204    int ret, i;
 205
 206    if (!kvm_check_extension(s, KVM_CAP_DEVICE_CTRL)) {
 207        error_setg(errp, "Kernel is lacking Device Control API");
 208        return;
 209    }
 210
 211    switch (opp->model) {
 212    case OPENPIC_MODEL_FSL_MPIC_20:
 213        kvm_openpic_model = KVM_DEV_TYPE_FSL_MPIC_20;
 214        break;
 215
 216    case OPENPIC_MODEL_FSL_MPIC_42:
 217        kvm_openpic_model = KVM_DEV_TYPE_FSL_MPIC_42;
 218        break;
 219
 220    default:
 221        error_setg(errp, "Unsupported OpenPIC model %" PRIu32, opp->model);
 222        return;
 223    }
 224
 225    cd.type = kvm_openpic_model;
 226    ret = kvm_vm_ioctl(s, KVM_CREATE_DEVICE, &cd);
 227    if (ret < 0) {
 228        error_setg(errp, "Can't create device %d: %s",
 229                   cd.type, strerror(errno));
 230        return;
 231    }
 232    opp->fd = cd.fd;
 233
 234    sysbus_init_mmio(d, &opp->mem);
 235    qdev_init_gpio_in(dev, kvm_openpic_set_irq, OPENPIC_MAX_IRQ);
 236
 237    opp->mem_listener.region_add = kvm_openpic_region_add;
 238    opp->mem_listener.region_del = kvm_openpic_region_del;
 239    memory_listener_register(&opp->mem_listener, &address_space_memory);
 240
 241    /* indicate pic capabilities */
 242    msi_nonbroken = true;
 243    kvm_kernel_irqchip = true;
 244    kvm_async_interrupts_allowed = true;
 245
 246    /* set up irq routing */
 247    kvm_init_irq_routing(kvm_state);
 248    for (i = 0; i < 256; ++i) {
 249        kvm_irqchip_add_irq_route(kvm_state, i, 0, i);
 250    }
 251
 252    kvm_msi_via_irqfd_allowed = true;
 253    kvm_gsi_routing_allowed = true;
 254
 255    kvm_irqchip_commit_routes(s);
 256}
 257
 258int kvm_openpic_connect_vcpu(DeviceState *d, CPUState *cs)
 259{
 260    KVMOpenPICState *opp = KVM_OPENPIC(d);
 261
 262    return kvm_vcpu_enable_cap(cs, KVM_CAP_IRQ_MPIC, 0, opp->fd,
 263                               kvm_arch_vcpu_id(cs));
 264}
 265
 266static Property kvm_openpic_properties[] = {
 267    DEFINE_PROP_UINT32("model", KVMOpenPICState, model,
 268                       OPENPIC_MODEL_FSL_MPIC_20),
 269    DEFINE_PROP_END_OF_LIST(),
 270};
 271
 272static void kvm_openpic_class_init(ObjectClass *oc, void *data)
 273{
 274    DeviceClass *dc = DEVICE_CLASS(oc);
 275
 276    dc->realize = kvm_openpic_realize;
 277    dc->props = kvm_openpic_properties;
 278    dc->reset = kvm_openpic_reset;
 279    set_bit(DEVICE_CATEGORY_MISC, dc->categories);
 280}
 281
 282static const TypeInfo kvm_openpic_info = {
 283    .name          = TYPE_KVM_OPENPIC,
 284    .parent        = TYPE_SYS_BUS_DEVICE,
 285    .instance_size = sizeof(KVMOpenPICState),
 286    .instance_init = kvm_openpic_init,
 287    .class_init    = kvm_openpic_class_init,
 288};
 289
 290static void kvm_openpic_register_types(void)
 291{
 292    type_register_static(&kvm_openpic_info);
 293}
 294
 295type_init(kvm_openpic_register_types)
 296