qemu/hw/intc/openpic_kvm.c
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   1/*
   2 * KVM in-kernel OpenPIC
   3 *
   4 * Copyright 2013 Freescale Semiconductor, Inc.
   5 *
   6 * Permission is hereby granted, free of charge, to any person obtaining a copy
   7 * of this software and associated documentation files (the "Software"), to deal
   8 * in the Software without restriction, including without limitation the rights
   9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10 * copies of the Software, and to permit persons to whom the Software is
  11 * furnished to do so, subject to the following conditions:
  12 *
  13 * The above copyright notice and this permission notice shall be included in
  14 * all copies or substantial portions of the Software.
  15 *
  16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22 * THE SOFTWARE.
  23 */
  24
  25#include "qemu/osdep.h"
  26#include "qapi/error.h"
  27#include <sys/ioctl.h>
  28#include "hw/ppc/openpic.h"
  29#include "hw/ppc/openpic_kvm.h"
  30#include "hw/pci/msi.h"
  31#include "hw/qdev-properties.h"
  32#include "hw/sysbus.h"
  33#include "sysemu/kvm.h"
  34#include "qemu/log.h"
  35#include "qemu/module.h"
  36#include "qom/object.h"
  37
  38#define GCR_RESET        0x80000000
  39
  40OBJECT_DECLARE_SIMPLE_TYPE(KVMOpenPICState, KVM_OPENPIC)
  41
  42struct KVMOpenPICState {
  43    /*< private >*/
  44    SysBusDevice parent_obj;
  45    /*< public >*/
  46
  47    MemoryRegion mem;
  48    MemoryListener mem_listener;
  49    uint32_t fd;
  50    uint32_t model;
  51    hwaddr mapped;
  52};
  53
  54static void kvm_openpic_set_irq(void *opaque, int n_IRQ, int level)
  55{
  56    kvm_set_irq(kvm_state, n_IRQ, level);
  57}
  58
  59static void kvm_openpic_write(void *opaque, hwaddr addr, uint64_t val,
  60                              unsigned size)
  61{
  62    KVMOpenPICState *opp = opaque;
  63    struct kvm_device_attr attr;
  64    uint32_t val32 = val;
  65    int ret;
  66
  67    attr.group = KVM_DEV_MPIC_GRP_REGISTER;
  68    attr.attr = addr;
  69    attr.addr = (uint64_t)(unsigned long)&val32;
  70
  71    ret = ioctl(opp->fd, KVM_SET_DEVICE_ATTR, &attr);
  72    if (ret < 0) {
  73        qemu_log_mask(LOG_UNIMP, "%s: %s %" PRIx64 "\n", __func__,
  74                      strerror(errno), attr.attr);
  75    }
  76}
  77
  78static void kvm_openpic_reset(DeviceState *d)
  79{
  80    KVMOpenPICState *opp = KVM_OPENPIC(d);
  81
  82    /* Trigger the GCR.RESET bit to reset the PIC */
  83    kvm_openpic_write(opp, 0x1020, GCR_RESET, sizeof(uint32_t));
  84}
  85
  86static uint64_t kvm_openpic_read(void *opaque, hwaddr addr, unsigned size)
  87{
  88    KVMOpenPICState *opp = opaque;
  89    struct kvm_device_attr attr;
  90    uint32_t val = 0xdeadbeef;
  91    int ret;
  92
  93    attr.group = KVM_DEV_MPIC_GRP_REGISTER;
  94    attr.attr = addr;
  95    attr.addr = (uint64_t)(unsigned long)&val;
  96
  97    ret = ioctl(opp->fd, KVM_GET_DEVICE_ATTR, &attr);
  98    if (ret < 0) {
  99        qemu_log_mask(LOG_UNIMP, "%s: %s %" PRIx64 "\n", __func__,
 100                      strerror(errno), attr.attr);
 101        return 0;
 102    }
 103
 104    return val;
 105}
 106
 107static const MemoryRegionOps kvm_openpic_mem_ops = {
 108    .write = kvm_openpic_write,
 109    .read  = kvm_openpic_read,
 110    .endianness = DEVICE_BIG_ENDIAN,
 111    .impl = {
 112        .min_access_size = 4,
 113        .max_access_size = 4,
 114    },
 115};
 116
 117static void kvm_openpic_region_add(MemoryListener *listener,
 118                                   MemoryRegionSection *section)
 119{
 120    KVMOpenPICState *opp = container_of(listener, KVMOpenPICState,
 121                                        mem_listener);
 122    struct kvm_device_attr attr;
 123    uint64_t reg_base;
 124    int ret;
 125
 126    /* Ignore events on regions that are not us */
 127    if (section->mr != &opp->mem) {
 128        return;
 129    }
 130
 131    if (opp->mapped) {
 132        /*
 133         * We can only map the MPIC once. Since we are already mapped,
 134         * the best we can do is ignore new maps.
 135         */
 136        return;
 137    }
 138
 139    reg_base = section->offset_within_address_space;
 140    opp->mapped = reg_base;
 141
 142    attr.group = KVM_DEV_MPIC_GRP_MISC;
 143    attr.attr = KVM_DEV_MPIC_BASE_ADDR;
 144    attr.addr = (uint64_t)(unsigned long)&reg_base;
 145
 146    ret = ioctl(opp->fd, KVM_SET_DEVICE_ATTR, &attr);
 147    if (ret < 0) {
 148        fprintf(stderr, "%s: %s %" PRIx64 "\n", __func__,
 149                strerror(errno), reg_base);
 150    }
 151}
 152
 153static void kvm_openpic_region_del(MemoryListener *listener,
 154                                   MemoryRegionSection *section)
 155{
 156    KVMOpenPICState *opp = container_of(listener, KVMOpenPICState,
 157                                        mem_listener);
 158    struct kvm_device_attr attr;
 159    uint64_t reg_base = 0;
 160    int ret;
 161
 162    /* Ignore events on regions that are not us */
 163    if (section->mr != &opp->mem) {
 164        return;
 165    }
 166
 167    if (section->offset_within_address_space != opp->mapped) {
 168        /*
 169         * We can only map the MPIC once. This mapping was a secondary
 170         * one that we couldn't fulfill. Ignore it.
 171         */
 172        return;
 173    }
 174    opp->mapped = 0;
 175
 176    attr.group = KVM_DEV_MPIC_GRP_MISC;
 177    attr.attr = KVM_DEV_MPIC_BASE_ADDR;
 178    attr.addr = (uint64_t)(unsigned long)&reg_base;
 179
 180    ret = ioctl(opp->fd, KVM_SET_DEVICE_ATTR, &attr);
 181    if (ret < 0) {
 182        fprintf(stderr, "%s: %s %" PRIx64 "\n", __func__,
 183                strerror(errno), reg_base);
 184    }
 185}
 186
 187static void kvm_openpic_init(Object *obj)
 188{
 189    KVMOpenPICState *opp = KVM_OPENPIC(obj);
 190
 191    memory_region_init_io(&opp->mem, OBJECT(opp), &kvm_openpic_mem_ops, opp,
 192                          "kvm-openpic", 0x40000);
 193}
 194
 195static void kvm_openpic_realize(DeviceState *dev, Error **errp)
 196{
 197    SysBusDevice *d = SYS_BUS_DEVICE(dev);
 198    KVMOpenPICState *opp = KVM_OPENPIC(dev);
 199    KVMState *s = kvm_state;
 200    int kvm_openpic_model;
 201    struct kvm_create_device cd = {0};
 202    int ret, i;
 203
 204    if (!kvm_check_extension(s, KVM_CAP_DEVICE_CTRL)) {
 205        error_setg(errp, "Kernel is lacking Device Control API");
 206        return;
 207    }
 208
 209    switch (opp->model) {
 210    case OPENPIC_MODEL_FSL_MPIC_20:
 211        kvm_openpic_model = KVM_DEV_TYPE_FSL_MPIC_20;
 212        break;
 213
 214    case OPENPIC_MODEL_FSL_MPIC_42:
 215        kvm_openpic_model = KVM_DEV_TYPE_FSL_MPIC_42;
 216        break;
 217
 218    default:
 219        error_setg(errp, "Unsupported OpenPIC model %" PRIu32, opp->model);
 220        return;
 221    }
 222
 223    cd.type = kvm_openpic_model;
 224    ret = kvm_vm_ioctl(s, KVM_CREATE_DEVICE, &cd);
 225    if (ret < 0) {
 226        error_setg(errp, "Can't create device %d: %s",
 227                   cd.type, strerror(errno));
 228        return;
 229    }
 230    opp->fd = cd.fd;
 231
 232    sysbus_init_mmio(d, &opp->mem);
 233    qdev_init_gpio_in(dev, kvm_openpic_set_irq, OPENPIC_MAX_IRQ);
 234
 235    opp->mem_listener.region_add = kvm_openpic_region_add;
 236    opp->mem_listener.region_del = kvm_openpic_region_del;
 237    opp->mem_listener.name = "openpic-kvm";
 238    memory_listener_register(&opp->mem_listener, &address_space_memory);
 239
 240    /* indicate pic capabilities */
 241    msi_nonbroken = true;
 242    kvm_kernel_irqchip = true;
 243    kvm_async_interrupts_allowed = true;
 244
 245    /* set up irq routing */
 246    kvm_init_irq_routing(kvm_state);
 247    for (i = 0; i < 256; ++i) {
 248        kvm_irqchip_add_irq_route(kvm_state, i, 0, i);
 249    }
 250
 251    kvm_msi_via_irqfd_allowed = true;
 252    kvm_gsi_routing_allowed = true;
 253
 254    kvm_irqchip_commit_routes(s);
 255}
 256
 257int kvm_openpic_connect_vcpu(DeviceState *d, CPUState *cs)
 258{
 259    KVMOpenPICState *opp = KVM_OPENPIC(d);
 260
 261    return kvm_vcpu_enable_cap(cs, KVM_CAP_IRQ_MPIC, 0, opp->fd,
 262                               kvm_arch_vcpu_id(cs));
 263}
 264
 265static Property kvm_openpic_properties[] = {
 266    DEFINE_PROP_UINT32("model", KVMOpenPICState, model,
 267                       OPENPIC_MODEL_FSL_MPIC_20),
 268    DEFINE_PROP_END_OF_LIST(),
 269};
 270
 271static void kvm_openpic_class_init(ObjectClass *oc, void *data)
 272{
 273    DeviceClass *dc = DEVICE_CLASS(oc);
 274
 275    dc->realize = kvm_openpic_realize;
 276    device_class_set_props(dc, kvm_openpic_properties);
 277    dc->reset = kvm_openpic_reset;
 278    set_bit(DEVICE_CATEGORY_MISC, dc->categories);
 279}
 280
 281static const TypeInfo kvm_openpic_info = {
 282    .name          = TYPE_KVM_OPENPIC,
 283    .parent        = TYPE_SYS_BUS_DEVICE,
 284    .instance_size = sizeof(KVMOpenPICState),
 285    .instance_init = kvm_openpic_init,
 286    .class_init    = kvm_openpic_class_init,
 287};
 288
 289static void kvm_openpic_register_types(void)
 290{
 291    type_register_static(&kvm_openpic_info);
 292}
 293
 294type_init(kvm_openpic_register_types)
 295