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26#include "qemu/osdep.h"
27#include "qapi/error.h"
28#include "hw/irq.h"
29#include "hw/southbridge/piix.h"
30#include "hw/pci/pci.h"
31#include "hw/isa/isa.h"
32#include "hw/intc/i8259.h"
33#include "hw/dma/i8257.h"
34#include "hw/timer/i8254.h"
35#include "hw/rtc/mc146818rtc.h"
36#include "hw/ide/pci.h"
37#include "migration/vmstate.h"
38#include "sysemu/reset.h"
39#include "sysemu/runstate.h"
40#include "qom/object.h"
41
42PCIDevice *piix4_dev;
43
44struct PIIX4State {
45 PCIDevice dev;
46 qemu_irq cpu_intr;
47 qemu_irq *isa;
48
49 RTCState rtc;
50
51 MemoryRegion rcr_mem;
52 uint8_t rcr;
53};
54
55OBJECT_DECLARE_SIMPLE_TYPE(PIIX4State, PIIX4_PCI_DEVICE)
56
57static void piix4_isa_reset(DeviceState *dev)
58{
59 PIIX4State *d = PIIX4_PCI_DEVICE(dev);
60 uint8_t *pci_conf = d->dev.config;
61
62 pci_conf[0x04] = 0x07;
63 pci_conf[0x05] = 0x00;
64 pci_conf[0x06] = 0x00;
65 pci_conf[0x07] = 0x02;
66 pci_conf[0x4c] = 0x4d;
67 pci_conf[0x4e] = 0x03;
68 pci_conf[0x4f] = 0x00;
69 pci_conf[0x60] = 0x0a;
70 pci_conf[0x61] = 0x0a;
71 pci_conf[0x62] = 0x0b;
72 pci_conf[0x63] = 0x0b;
73 pci_conf[0x69] = 0x02;
74 pci_conf[0x70] = 0x80;
75 pci_conf[0x76] = 0x0c;
76 pci_conf[0x77] = 0x0c;
77 pci_conf[0x78] = 0x02;
78 pci_conf[0x79] = 0x00;
79 pci_conf[0x80] = 0x00;
80 pci_conf[0x82] = 0x00;
81 pci_conf[0xa0] = 0x08;
82 pci_conf[0xa2] = 0x00;
83 pci_conf[0xa3] = 0x00;
84 pci_conf[0xa4] = 0x00;
85 pci_conf[0xa5] = 0x00;
86 pci_conf[0xa6] = 0x00;
87 pci_conf[0xa7] = 0x00;
88 pci_conf[0xa8] = 0x0f;
89 pci_conf[0xaa] = 0x00;
90 pci_conf[0xab] = 0x00;
91 pci_conf[0xac] = 0x00;
92 pci_conf[0xae] = 0x00;
93}
94
95static int piix4_ide_post_load(void *opaque, int version_id)
96{
97 PIIX4State *s = opaque;
98
99 if (version_id == 2) {
100 s->rcr = 0;
101 }
102
103 return 0;
104}
105
106static const VMStateDescription vmstate_piix4 = {
107 .name = "PIIX4",
108 .version_id = 3,
109 .minimum_version_id = 2,
110 .post_load = piix4_ide_post_load,
111 .fields = (VMStateField[]) {
112 VMSTATE_PCI_DEVICE(dev, PIIX4State),
113 VMSTATE_UINT8_V(rcr, PIIX4State, 3),
114 VMSTATE_END_OF_LIST()
115 }
116};
117
118static void piix4_request_i8259_irq(void *opaque, int irq, int level)
119{
120 PIIX4State *s = opaque;
121 qemu_set_irq(s->cpu_intr, level);
122}
123
124static void piix4_set_i8259_irq(void *opaque, int irq, int level)
125{
126 PIIX4State *s = opaque;
127 qemu_set_irq(s->isa[irq], level);
128}
129
130static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val,
131 unsigned int len)
132{
133 PIIX4State *s = opaque;
134
135 if (val & 4) {
136 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
137 return;
138 }
139
140 s->rcr = val & 2;
141}
142
143static uint64_t piix4_rcr_read(void *opaque, hwaddr addr, unsigned int len)
144{
145 PIIX4State *s = opaque;
146
147 return s->rcr;
148}
149
150static const MemoryRegionOps piix4_rcr_ops = {
151 .read = piix4_rcr_read,
152 .write = piix4_rcr_write,
153 .endianness = DEVICE_LITTLE_ENDIAN,
154 .impl = {
155 .min_access_size = 1,
156 .max_access_size = 1,
157 },
158};
159
160static void piix4_realize(PCIDevice *dev, Error **errp)
161{
162 PIIX4State *s = PIIX4_PCI_DEVICE(dev);
163 ISABus *isa_bus;
164 qemu_irq *i8259_out_irq;
165
166 isa_bus = isa_bus_new(DEVICE(dev), pci_address_space(dev),
167 pci_address_space_io(dev), errp);
168 if (!isa_bus) {
169 return;
170 }
171
172 qdev_init_gpio_in_named(DEVICE(dev), piix4_set_i8259_irq,
173 "isa", ISA_NUM_IRQS);
174 qdev_init_gpio_out_named(DEVICE(dev), &s->cpu_intr,
175 "intr", 1);
176
177 memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops, s,
178 "reset-control", 1);
179 memory_region_add_subregion_overlap(pci_address_space_io(dev),
180 PIIX_RCR_IOPORT, &s->rcr_mem, 1);
181
182
183 i8259_out_irq = qemu_allocate_irqs(piix4_request_i8259_irq, s, 1);
184 s->isa = i8259_init(isa_bus, *i8259_out_irq);
185
186
187 isa_bus_irqs(isa_bus, s->isa);
188
189
190 i8254_pit_init(isa_bus, 0x40, 0, NULL);
191
192
193 i8257_dma_init(isa_bus, 0);
194
195
196 qdev_prop_set_int32(DEVICE(&s->rtc), "base_year", 2000);
197 if (!qdev_realize(DEVICE(&s->rtc), BUS(isa_bus), errp)) {
198 return;
199 }
200 isa_init_irq(ISA_DEVICE(&s->rtc), &s->rtc.irq, RTC_ISA_IRQ);
201
202 piix4_dev = dev;
203}
204
205static void piix4_init(Object *obj)
206{
207 PIIX4State *s = PIIX4_PCI_DEVICE(obj);
208
209 object_initialize(&s->rtc, sizeof(s->rtc), TYPE_MC146818_RTC);
210}
211
212static void piix4_class_init(ObjectClass *klass, void *data)
213{
214 DeviceClass *dc = DEVICE_CLASS(klass);
215 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
216
217 k->realize = piix4_realize;
218 k->vendor_id = PCI_VENDOR_ID_INTEL;
219 k->device_id = PCI_DEVICE_ID_INTEL_82371AB_0;
220 k->class_id = PCI_CLASS_BRIDGE_ISA;
221 dc->reset = piix4_isa_reset;
222 dc->desc = "ISA bridge";
223 dc->vmsd = &vmstate_piix4;
224
225
226
227
228 dc->user_creatable = false;
229 dc->hotpluggable = false;
230}
231
232static const TypeInfo piix4_info = {
233 .name = TYPE_PIIX4_PCI_DEVICE,
234 .parent = TYPE_PCI_DEVICE,
235 .instance_size = sizeof(PIIX4State),
236 .instance_init = piix4_init,
237 .class_init = piix4_class_init,
238 .interfaces = (InterfaceInfo[]) {
239 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
240 { },
241 },
242};
243
244static void piix4_register_types(void)
245{
246 type_register_static(&piix4_info);
247}
248
249type_init(piix4_register_types)
250
251DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, I2CBus **smbus)
252{
253 PCIDevice *pci;
254 DeviceState *dev;
255 int devfn = PCI_DEVFN(10, 0);
256
257 pci = pci_create_simple_multifunction(pci_bus, devfn, true,
258 TYPE_PIIX4_PCI_DEVICE);
259 dev = DEVICE(pci);
260 if (isa_bus) {
261 *isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
262 }
263
264 pci = pci_create_simple(pci_bus, devfn + 1, "piix4-ide");
265 pci_ide_create_devs(pci);
266
267 pci_create_simple(pci_bus, devfn + 2, "piix4-usb-uhci");
268 if (smbus) {
269 *smbus = piix4_pm_init(pci_bus, devfn + 3, 0x1100,
270 qdev_get_gpio_in_named(dev, "isa", 9),
271 NULL, 0, NULL);
272 }
273
274 return dev;
275}
276
