LXR qemu/hw/microblaze/petalogix_ml605

   1/*
   2 * Model of Petalogix linux reference design targeting Xilinx Spartan ml605
   3 * board.
   4 *
   5 * Copyright (c) 2011 Michal Simek <monstr@monstr.eu>
   6 * Copyright (c) 2011 PetaLogix
   7 * Copyright (c) 2009 Edgar E. Iglesias.
   8 *
   9 * Permission is hereby granted, free of charge, to any person obtaining a copy
  10 * of this software and associated documentation files (the "Software"), to deal
  11 * in the Software without restriction, including without limitation the rights
  12 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  13 * copies of the Software, and to permit persons to whom the Software is
  14 * furnished to do so, subject to the following conditions:
  15 *
  16 * The above copyright notice and this permission notice shall be included in
  17 * all copies or substantial portions of the Software.
  18 *
  19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  24 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  25 * THE SOFTWARE.
  26 */
  27
  28#include "qemu/osdep.h"
  29#include "qemu/units.h"
  30#include "qapi/error.h"
  31#include "cpu.h"
  32#include "hw/sysbus.h"
  33#include "net/net.h"
  34#include "hw/block/flash.h"
  35#include "sysemu/sysemu.h"
  36#include "hw/boards.h"
  37#include "hw/char/serial.h"
  38#include "hw/qdev-properties.h"
  39#include "exec/address-spaces.h"
  40#include "hw/ssi/ssi.h"
  41
  42#include "boot.h"
  43
  44#include "hw/stream.h"
  45
  46#define LMB_BRAM_SIZE  (128 * KiB)
  47#define FLASH_SIZE     (32 * MiB)
  48
  49#define BINARY_DEVICE_TREE_FILE "petalogix-ml605.dtb"
  50
  51#define NUM_SPI_FLASHES 4
  52
  53#define SPI_BASEADDR 0x40a00000
  54#define MEMORY_BASEADDR 0x50000000
  55#define FLASH_BASEADDR 0x86000000
  56#define INTC_BASEADDR 0x81800000
  57#define TIMER_BASEADDR 0x83c00000
  58#define UART16550_BASEADDR 0x83e00000
  59#define AXIENET_BASEADDR 0x82780000
  60#define AXIDMA_BASEADDR 0x84600000
  61
  62#define AXIDMA_IRQ1         0
  63#define AXIDMA_IRQ0         1
  64#define TIMER_IRQ           2
  65#define AXIENET_IRQ         3
  66#define SPI_IRQ             4
  67#define UART16550_IRQ       5
  68
  69static void
  70petalogix_ml605_init(MachineState *machine)
  71{
  72    ram_addr_t ram_size = machine->ram_size;
  73    MemoryRegion *address_space_mem = get_system_memory();
  74    DeviceState *dev, *dma, *eth0;
  75    Object *ds, *cs;
  76    MicroBlazeCPU *cpu;
  77    SysBusDevice *busdev;
  78    DriveInfo *dinfo;
  79    int i;
  80    MemoryRegion *phys_lmb_bram = g_new(MemoryRegion, 1);
  81    MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
  82    qemu_irq irq[32];
  83
  84    /* init CPUs */
  85    cpu = MICROBLAZE_CPU(object_new(TYPE_MICROBLAZE_CPU));
  86    object_property_set_str(OBJECT(cpu), "version", "8.10.a", &error_abort);
  87    /* Use FPU but don't use floating point conversion and square
  88     * root instructions
  89     */
  90    object_property_set_int(OBJECT(cpu), "use-fpu", 1, &error_abort);
  91    object_property_set_bool(OBJECT(cpu), "dcache-writeback", true,
  92                             &error_abort);
  93    object_property_set_bool(OBJECT(cpu), "endianness", true, &error_abort);
  94    qdev_realize(DEVICE(cpu), NULL, &error_abort);
  95
  96    /* Attach emulated BRAM through the LMB.  */
  97    memory_region_init_ram(phys_lmb_bram, NULL, "petalogix_ml605.lmb_bram",
  98                           LMB_BRAM_SIZE, &error_fatal);
  99    memory_region_add_subregion(address_space_mem, 0x00000000, phys_lmb_bram);
 100
 101    memory_region_init_ram(phys_ram, NULL, "petalogix_ml605.ram", ram_size,
 102                           &error_fatal);
 103    memory_region_add_subregion(address_space_mem, MEMORY_BASEADDR, phys_ram);
 104
 105    dinfo = drive_get(IF_PFLASH, 0, 0);
 106    /* 5th parameter 2 means bank-width
 107     * 10th paremeter 0 means little-endian */
 108    pflash_cfi01_register(FLASH_BASEADDR, "petalogix_ml605.flash", FLASH_SIZE,
 109                          dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
 110                          64 * KiB, 2, 0x89, 0x18, 0x0000, 0x0, 0);
 111
 112
 113    dev = qdev_new("xlnx.xps-intc");
 114    qdev_prop_set_uint32(dev, "kind-of-intr", 1 << TIMER_IRQ);
 115    sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 116    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, INTC_BASEADDR);
 117    sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
 118                       qdev_get_gpio_in(DEVICE(cpu), MB_CPU_IRQ));
 119    for (i = 0; i < 32; i++) {
 120        irq[i] = qdev_get_gpio_in(dev, i);
 121    }
 122
 123    serial_mm_init(address_space_mem, UART16550_BASEADDR + 0x1000, 2,
 124                   irq[UART16550_IRQ], 115200, serial_hd(0),
 125                   DEVICE_LITTLE_ENDIAN);
 126
 127    /* 2 timers at irq 2 @ 100 Mhz.  */
 128    dev = qdev_new("xlnx.xps-timer");
 129    qdev_prop_set_uint32(dev, "one-timer-only", 0);
 130    qdev_prop_set_uint32(dev, "clock-frequency", 100 * 1000000);
 131    sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 132    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, TIMER_BASEADDR);
 133    sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ]);
 134
 135    /* axi ethernet and dma initialization. */
 136    qemu_check_nic_model(&nd_table[0], "xlnx.axi-ethernet");
 137    eth0 = qdev_new("xlnx.axi-ethernet");
 138    dma = qdev_new("xlnx.axi-dma");
 139
 140    /* FIXME: attach to the sysbus instead */
 141    object_property_add_child(qdev_get_machine(), "xilinx-eth", OBJECT(eth0));
 142    object_property_add_child(qdev_get_machine(), "xilinx-dma", OBJECT(dma));
 143
 144    ds = object_property_get_link(OBJECT(dma),
 145                                  "axistream-connected-target", NULL);
 146    cs = object_property_get_link(OBJECT(dma),
 147                                  "axistream-control-connected-target", NULL);
 148    qdev_set_nic_properties(eth0, &nd_table[0]);
 149    qdev_prop_set_uint32(eth0, "rxmem", 0x1000);
 150    qdev_prop_set_uint32(eth0, "txmem", 0x1000);
 151    object_property_set_link(OBJECT(eth0), "axistream-connected", ds,
 152                             &error_abort);
 153    object_property_set_link(OBJECT(eth0), "axistream-control-connected", cs,
 154                             &error_abort);
 155    sysbus_realize_and_unref(SYS_BUS_DEVICE(eth0), &error_fatal);
 156    sysbus_mmio_map(SYS_BUS_DEVICE(eth0), 0, AXIENET_BASEADDR);
 157    sysbus_connect_irq(SYS_BUS_DEVICE(eth0), 0, irq[AXIENET_IRQ]);
 158
 159    ds = object_property_get_link(OBJECT(eth0),
 160                                  "axistream-connected-target", NULL);
 161    cs = object_property_get_link(OBJECT(eth0),
 162                                  "axistream-control-connected-target", NULL);
 163    qdev_prop_set_uint32(dma, "freqhz", 100 * 1000000);
 164    object_property_set_link(OBJECT(dma), "axistream-connected", ds,
 165                             &error_abort);
 166    object_property_set_link(OBJECT(dma), "axistream-control-connected", cs,
 167                             &error_abort);
 168    sysbus_realize_and_unref(SYS_BUS_DEVICE(dma), &error_fatal);
 169    sysbus_mmio_map(SYS_BUS_DEVICE(dma), 0, AXIDMA_BASEADDR);
 170    sysbus_connect_irq(SYS_BUS_DEVICE(dma), 0, irq[AXIDMA_IRQ0]);
 171    sysbus_connect_irq(SYS_BUS_DEVICE(dma), 1, irq[AXIDMA_IRQ1]);
 172
 173    {
 174        SSIBus *spi;
 175
 176        dev = qdev_new("xlnx.xps-spi");
 177        qdev_prop_set_uint8(dev, "num-ss-bits", NUM_SPI_FLASHES);
 178        busdev = SYS_BUS_DEVICE(dev);
 179        sysbus_realize_and_unref(busdev, &error_fatal);
 180        sysbus_mmio_map(busdev, 0, SPI_BASEADDR);
 181        sysbus_connect_irq(busdev, 0, irq[SPI_IRQ]);
 182
 183        spi = (SSIBus *)qdev_get_child_bus(dev, "spi");
 184
 185        for (i = 0; i < NUM_SPI_FLASHES; i++) {
 186            DriveInfo *dinfo = drive_get_next(IF_MTD);
 187            qemu_irq cs_line;
 188
 189            dev = qdev_new("n25q128");
 190            if (dinfo) {
 191                qdev_prop_set_drive_err(dev, "drive",
 192                                        blk_by_legacy_dinfo(dinfo),
 193                                        &error_fatal);
 194            }
 195            qdev_realize_and_unref(dev, BUS(spi), &error_fatal);
 196
 197            cs_line = qdev_get_gpio_in_named(dev, SSI_GPIO_CS, 0);
 198            sysbus_connect_irq(busdev, i+1, cs_line);
 199        }
 200    }
 201
 202    /* setup PVR to match kernel settings */
 203    cpu->cfg.pvr_regs[4] = 0xc56b8000;
 204    cpu->cfg.pvr_regs[5] = 0xc56be000;
 205    cpu->cfg.pvr_regs[10] = 0x0e000000; /* virtex 6 */
 206
 207    microblaze_load_kernel(cpu, MEMORY_BASEADDR, ram_size,
 208                           machine->initrd_filename,
 209                           BINARY_DEVICE_TREE_FILE,
 210                           NULL);
 211
 212}
 213
 214static void petalogix_ml605_machine_init(MachineClass *mc)
 215{
 216    mc->desc = "PetaLogix linux refdesign for xilinx ml605 little endian";
 217    mc->init = petalogix_ml605_init;
 218}
 219
 220DEFINE_MACHINE("petalogix-ml605", petalogix_ml605_machine_init)
 221