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20#include "qemu/osdep.h"
21#include "qapi/error.h"
22#include "qemu/module.h"
23#include "hw/mips/cps.h"
24#include "hw/mips/mips.h"
25#include "hw/qdev-clock.h"
26#include "hw/qdev-properties.h"
27#include "hw/mips/cpudevs.h"
28#include "sysemu/kvm.h"
29#include "sysemu/reset.h"
30
31qemu_irq get_cps_irq(MIPSCPSState *s, int pin_number)
32{
33 assert(pin_number < s->num_irq);
34 return s->gic.irq_state[pin_number].irq;
35}
36
37static void mips_cps_init(Object *obj)
38{
39 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
40 MIPSCPSState *s = MIPS_CPS(obj);
41
42 s->clock = qdev_init_clock_in(DEVICE(obj), "clk-in", NULL, NULL, 0);
43
44
45
46
47 memory_region_init(&s->container, obj, "mips-cps-container", UINT64_MAX);
48 sysbus_init_mmio(sbd, &s->container);
49}
50
51static void main_cpu_reset(void *opaque)
52{
53 MIPSCPU *cpu = opaque;
54 CPUState *cs = CPU(cpu);
55
56 cpu_reset(cs);
57}
58
59static bool cpu_mips_itu_supported(CPUMIPSState *env)
60{
61 bool is_mt = (env->CP0_Config5 & (1 << CP0C5_VP)) || ase_mt_available(env);
62
63 return is_mt && !kvm_enabled();
64}
65
66static void mips_cps_realize(DeviceState *dev, Error **errp)
67{
68 MIPSCPSState *s = MIPS_CPS(dev);
69 CPUMIPSState *env;
70 MIPSCPU *cpu;
71 int i;
72 target_ulong gcr_base;
73 bool itu_present = false;
74 bool saar_present = false;
75
76 if (!clock_get(s->clock)) {
77 error_setg(errp, "CPS input clock is not connected to an output clock");
78 return;
79 }
80
81 for (i = 0; i < s->num_vp; i++) {
82 cpu = MIPS_CPU(object_new(s->cpu_type));
83
84
85 if (!object_property_set_bool(OBJECT(cpu), "start-powered-off", true,
86 errp)) {
87 return;
88 }
89
90 qdev_connect_clock_in(DEVICE(cpu), "clk-in", s->clock);
91
92 if (!qdev_realize_and_unref(DEVICE(cpu), NULL, errp)) {
93 return;
94 }
95
96
97 cpu_mips_irq_init_cpu(cpu);
98 cpu_mips_clock_init(cpu);
99
100 env = &cpu->env;
101 if (cpu_mips_itu_supported(env)) {
102 itu_present = true;
103
104 env->itc_tag = mips_itu_get_tag_region(&s->itu);
105 env->itu = &s->itu;
106 }
107 qemu_register_reset(main_cpu_reset, cpu);
108 }
109
110 cpu = MIPS_CPU(first_cpu);
111 env = &cpu->env;
112 saar_present = (bool)env->saarp;
113
114
115 if (itu_present) {
116 object_initialize_child(OBJECT(dev), "itu", &s->itu, TYPE_MIPS_ITU);
117 object_property_set_int(OBJECT(&s->itu), "num-fifo", 16,
118 &error_abort);
119 object_property_set_int(OBJECT(&s->itu), "num-semaphores", 16,
120 &error_abort);
121 object_property_set_bool(OBJECT(&s->itu), "saar-present", saar_present,
122 &error_abort);
123 if (saar_present) {
124 s->itu.saar = &env->CP0_SAAR;
125 }
126 if (!sysbus_realize(SYS_BUS_DEVICE(&s->itu), errp)) {
127 return;
128 }
129
130 memory_region_add_subregion(&s->container, 0,
131 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->itu), 0));
132 }
133
134
135 object_initialize_child(OBJECT(dev), "cpc", &s->cpc, TYPE_MIPS_CPC);
136 object_property_set_int(OBJECT(&s->cpc), "num-vp", s->num_vp,
137 &error_abort);
138 object_property_set_int(OBJECT(&s->cpc), "vp-start-running", 1,
139 &error_abort);
140 if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpc), errp)) {
141 return;
142 }
143
144 memory_region_add_subregion(&s->container, 0,
145 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpc), 0));
146
147
148 object_initialize_child(OBJECT(dev), "gic", &s->gic, TYPE_MIPS_GIC);
149 object_property_set_int(OBJECT(&s->gic), "num-vp", s->num_vp,
150 &error_abort);
151 object_property_set_int(OBJECT(&s->gic), "num-irq", 128,
152 &error_abort);
153 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic), errp)) {
154 return;
155 }
156
157 memory_region_add_subregion(&s->container, 0,
158 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gic), 0));
159
160
161 gcr_base = env->CP0_CMGCRBase << 4;
162
163 object_initialize_child(OBJECT(dev), "gcr", &s->gcr, TYPE_MIPS_GCR);
164 object_property_set_int(OBJECT(&s->gcr), "num-vp", s->num_vp,
165 &error_abort);
166 object_property_set_int(OBJECT(&s->gcr), "gcr-rev", 0x800,
167 &error_abort);
168 object_property_set_int(OBJECT(&s->gcr), "gcr-base", gcr_base,
169 &error_abort);
170 object_property_set_link(OBJECT(&s->gcr), "gic", OBJECT(&s->gic.mr),
171 &error_abort);
172 object_property_set_link(OBJECT(&s->gcr), "cpc", OBJECT(&s->cpc.mr),
173 &error_abort);
174 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gcr), errp)) {
175 return;
176 }
177
178 memory_region_add_subregion(&s->container, gcr_base,
179 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gcr), 0));
180}
181
182static Property mips_cps_properties[] = {
183 DEFINE_PROP_UINT32("num-vp", MIPSCPSState, num_vp, 1),
184 DEFINE_PROP_UINT32("num-irq", MIPSCPSState, num_irq, 256),
185 DEFINE_PROP_STRING("cpu-type", MIPSCPSState, cpu_type),
186 DEFINE_PROP_END_OF_LIST()
187};
188
189static void mips_cps_class_init(ObjectClass *klass, void *data)
190{
191 DeviceClass *dc = DEVICE_CLASS(klass);
192
193 dc->realize = mips_cps_realize;
194 device_class_set_props(dc, mips_cps_properties);
195}
196
197static const TypeInfo mips_cps_info = {
198 .name = TYPE_MIPS_CPS,
199 .parent = TYPE_SYS_BUS_DEVICE,
200 .instance_size = sizeof(MIPSCPSState),
201 .instance_init = mips_cps_init,
202 .class_init = mips_cps_class_init,
203};
204
205static void mips_cps_register_types(void)
206{
207 type_register_static(&mips_cps_info);
208}
209
210type_init(mips_cps_register_types)
211
