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24
25#include "qemu/osdep.h"
26#include "qemu/units.h"
27#include "qemu/bitops.h"
28#include "qemu-common.h"
29#include "qemu/datadir.h"
30#include "hw/clock.h"
31#include "hw/southbridge/piix.h"
32#include "hw/isa/superio.h"
33#include "hw/char/serial.h"
34#include "net/net.h"
35#include "hw/boards.h"
36#include "hw/i2c/smbus_eeprom.h"
37#include "hw/block/flash.h"
38#include "hw/mips/mips.h"
39#include "hw/mips/cpudevs.h"
40#include "hw/pci/pci.h"
41#include "qemu/log.h"
42#include "hw/mips/bios.h"
43#include "hw/ide.h"
44#include "hw/irq.h"
45#include "hw/loader.h"
46#include "elf.h"
47#include "qom/object.h"
48#include "hw/sysbus.h"
49#include "qemu/host-utils.h"
50#include "sysemu/qtest.h"
51#include "sysemu/reset.h"
52#include "sysemu/runstate.h"
53#include "qapi/error.h"
54#include "qemu/error-report.h"
55#include "hw/misc/empty_slot.h"
56#include "sysemu/kvm.h"
57#include "semihosting/semihost.h"
58#include "hw/mips/cps.h"
59#include "hw/qdev-clock.h"
60
61#define ENVP_PADDR 0x2000
62#define ENVP_VADDR cpu_mips_phys_to_kseg0(NULL, ENVP_PADDR)
63#define ENVP_NB_ENTRIES 16
64#define ENVP_ENTRY_SIZE 256
65
66
67#define FLASH_ADDRESS 0x1e000000ULL
68#define FPGA_ADDRESS 0x1f000000ULL
69#define RESET_ADDRESS 0x1fc00000ULL
70
71#define FLASH_SIZE 0x400000
72
73#define MAX_IDE_BUS 2
74
75typedef struct {
76 MemoryRegion iomem;
77 MemoryRegion iomem_lo;
78 MemoryRegion iomem_hi;
79 uint32_t leds;
80 uint32_t brk;
81 uint32_t gpout;
82 uint32_t i2cin;
83 uint32_t i2coe;
84 uint32_t i2cout;
85 uint32_t i2csel;
86 CharBackend display;
87 char display_text[9];
88 SerialMM *uart;
89 bool display_inited;
90} MaltaFPGAState;
91
92#define TYPE_MIPS_MALTA "mips-malta"
93OBJECT_DECLARE_SIMPLE_TYPE(MaltaState, MIPS_MALTA)
94
95struct MaltaState {
96 SysBusDevice parent_obj;
97
98 Clock *cpuclk;
99 MIPSCPSState cps;
100 qemu_irq i8259[ISA_NUM_IRQS];
101};
102
103static struct _loaderparams {
104 int ram_size, ram_low_size;
105 const char *kernel_filename;
106 const char *kernel_cmdline;
107 const char *initrd_filename;
108} loaderparams;
109
110
111static void malta_fpga_update_display(void *opaque)
112{
113 char leds_text[9];
114 int i;
115 MaltaFPGAState *s = opaque;
116
117 for (i = 7 ; i >= 0 ; i--) {
118 if (s->leds & (1 << i)) {
119 leds_text[i] = '#';
120 } else {
121 leds_text[i] = ' ';
122 }
123 }
124 leds_text[8] = '\0';
125
126 qemu_chr_fe_printf(&s->display, "\e[H\n\n|\e[32m%-8.8s\e[00m|\r\n",
127 leds_text);
128 qemu_chr_fe_printf(&s->display, "\n\n\n\n|\e[31m%-8.8s\e[00m|",
129 s->display_text);
130}
131
132
133
134
135
136
137
138
139
140
141
142#if defined(DEBUG)
143# define logout(fmt, ...) \
144 fprintf(stderr, "MALTA\t%-24s" fmt, __func__, ## __VA_ARGS__)
145#else
146# define logout(fmt, ...) ((void)0)
147#endif
148
149struct _eeprom24c0x_t {
150 uint8_t tick;
151 uint8_t address;
152 uint8_t command;
153 uint8_t ack;
154 uint8_t scl;
155 uint8_t sda;
156 uint8_t data;
157
158 uint8_t contents[256];
159};
160
161typedef struct _eeprom24c0x_t eeprom24c0x_t;
162
163static eeprom24c0x_t spd_eeprom = {
164 .contents = {
165
166 0x80, 0x08, 0xFF, 0x0D, 0x0A, 0xFF, 0x40, 0x00,
167
168 0x01, 0x75, 0x54, 0x00, 0x82, 0x08, 0x00, 0x01,
169
170 0x8F, 0x04, 0x02, 0x01, 0x01, 0x00, 0x00, 0x00,
171
172 0x00, 0x00, 0x00, 0x14, 0x0F, 0x14, 0x2D, 0xFF,
173
174 0x15, 0x08, 0x15, 0x08, 0x00, 0x00, 0x00, 0x00,
175
176 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
177
178 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
179
180 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0xD0,
181
182 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
183
184 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
185
186 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
187
188 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
189
190 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
191
192 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
193
194 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
195
196 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x64, 0xF4,
197 },
198};
199
200static void generate_eeprom_spd(uint8_t *eeprom, ram_addr_t ram_size)
201{
202 enum { SDR = 0x4, DDR2 = 0x8 } type;
203 uint8_t *spd = spd_eeprom.contents;
204 uint8_t nbanks = 0;
205 uint16_t density = 0;
206 int i;
207
208
209 ram_size /= MiB;
210
211 while ((ram_size >= 4) && (nbanks <= 2)) {
212 int sz_log2 = MIN(31 - clz32(ram_size), 14);
213 nbanks++;
214 density |= 1 << (sz_log2 - 2);
215 ram_size -= 1 << sz_log2;
216 }
217
218
219 if ((nbanks == 1) && (density > 1)) {
220 nbanks++;
221 density >>= 1;
222 }
223
224 if (density & 0xff00) {
225 density = (density & 0xe0) | ((density >> 8) & 0x1f);
226 type = DDR2;
227 } else if (!(density & 0x1f)) {
228 type = DDR2;
229 } else {
230 type = SDR;
231 }
232
233 if (ram_size) {
234 warn_report("SPD cannot represent final " RAM_ADDR_FMT "MB"
235 " of SDRAM", ram_size);
236 }
237
238
239 spd[2] = type;
240 spd[5] = nbanks;
241 spd[31] = density;
242
243
244 spd[63] = 0;
245 for (i = 0; i < 63; i++) {
246 spd[63] += spd[i];
247 }
248
249
250 memcpy(eeprom, spd, sizeof(spd_eeprom.contents));
251}
252
253static void generate_eeprom_serial(uint8_t *eeprom)
254{
255 int i, pos = 0;
256 uint8_t mac[6] = { 0x00 };
257 uint8_t sn[5] = { 0x01, 0x23, 0x45, 0x67, 0x89 };
258
259
260 eeprom[pos++] = 0x01;
261
262
263 eeprom[pos++] = 0x02;
264
265
266 eeprom[pos++] = 0x01;
267 eeprom[pos++] = 0x06;
268 memcpy(&eeprom[pos], mac, sizeof(mac));
269 pos += sizeof(mac);
270
271
272 eeprom[pos++] = 0x02;
273 eeprom[pos++] = 0x05;
274 memcpy(&eeprom[pos], sn, sizeof(sn));
275 pos += sizeof(sn);
276
277
278 eeprom[pos] = 0;
279 for (i = 0; i < pos; i++) {
280 eeprom[pos] += eeprom[i];
281 }
282}
283
284static uint8_t eeprom24c0x_read(eeprom24c0x_t *eeprom)
285{
286 logout("%u: scl = %u, sda = %u, data = 0x%02x\n",
287 eeprom->tick, eeprom->scl, eeprom->sda, eeprom->data);
288 return eeprom->sda;
289}
290
291static void eeprom24c0x_write(eeprom24c0x_t *eeprom, int scl, int sda)
292{
293 if (eeprom->scl && scl && (eeprom->sda != sda)) {
294 logout("%u: scl = %u->%u, sda = %u->%u i2c %s\n",
295 eeprom->tick, eeprom->scl, scl, eeprom->sda, sda,
296 sda ? "stop" : "start");
297 if (!sda) {
298 eeprom->tick = 1;
299 eeprom->command = 0;
300 }
301 } else if (eeprom->tick == 0 && !eeprom->ack) {
302
303 logout("%u: scl = %u->%u, sda = %u->%u wait for i2c start\n",
304 eeprom->tick, eeprom->scl, scl, eeprom->sda, sda);
305 } else if (!eeprom->scl && scl) {
306 logout("%u: scl = %u->%u, sda = %u->%u trigger bit\n",
307 eeprom->tick, eeprom->scl, scl, eeprom->sda, sda);
308 if (eeprom->ack) {
309 logout("\ti2c ack bit = 0\n");
310 sda = 0;
311 eeprom->ack = 0;
312 } else if (eeprom->sda == sda) {
313 uint8_t bit = (sda != 0);
314 logout("\ti2c bit = %d\n", bit);
315 if (eeprom->tick < 9) {
316 eeprom->command <<= 1;
317 eeprom->command += bit;
318 eeprom->tick++;
319 if (eeprom->tick == 9) {
320 logout("\tcommand 0x%04x, %s\n", eeprom->command,
321 bit ? "read" : "write");
322 eeprom->ack = 1;
323 }
324 } else if (eeprom->tick < 17) {
325 if (eeprom->command & 1) {
326 sda = ((eeprom->data & 0x80) != 0);
327 }
328 eeprom->address <<= 1;
329 eeprom->address += bit;
330 eeprom->tick++;
331 eeprom->data <<= 1;
332 if (eeprom->tick == 17) {
333 eeprom->data = eeprom->contents[eeprom->address];
334 logout("\taddress 0x%04x, data 0x%02x\n",
335 eeprom->address, eeprom->data);
336 eeprom->ack = 1;
337 eeprom->tick = 0;
338 }
339 } else if (eeprom->tick >= 17) {
340 sda = 0;
341 }
342 } else {
343 logout("\tsda changed with raising scl\n");
344 }
345 } else {
346 logout("%u: scl = %u->%u, sda = %u->%u\n", eeprom->tick, eeprom->scl,
347 scl, eeprom->sda, sda);
348 }
349 eeprom->scl = scl;
350 eeprom->sda = sda;
351}
352
353static uint64_t malta_fpga_read(void *opaque, hwaddr addr,
354 unsigned size)
355{
356 MaltaFPGAState *s = opaque;
357 uint32_t val = 0;
358 uint32_t saddr;
359
360 saddr = (addr & 0xfffff);
361
362 switch (saddr) {
363
364
365 case 0x00200:
366 val = 0x00000000;
367 break;
368
369
370 case 0x00208:
371#ifdef TARGET_WORDS_BIGENDIAN
372 val = 0x00000012;
373#else
374 val = 0x00000010;
375#endif
376 break;
377
378
379 case 0x00210:
380 val = 0x00;
381 break;
382
383
384 case 0x00408:
385 val = s->leds;
386 break;
387
388
389 case 0x00508:
390 val = s->brk;
391 break;
392
393
394
395
396 case 0x00a00:
397 val = s->gpout;
398 break;
399
400
401
402
403 case 0x00a08:
404
405 if (s->i2csel) {
406 val = s->i2cout;
407 } else {
408 val = 0x00;
409 }
410 break;
411
412
413 case 0x00b00:
414 val = ((s->i2cin & ~1) | eeprom24c0x_read(&spd_eeprom));
415 break;
416
417
418 case 0x00b08:
419 val = s->i2coe;
420 break;
421
422
423 case 0x00b10:
424 val = s->i2cout;
425 break;
426
427
428 case 0x00b18:
429 val = s->i2csel;
430 break;
431
432 default:
433 qemu_log_mask(LOG_GUEST_ERROR,
434 "malta_fpga_read: Bad register addr 0x%"HWADDR_PRIX"\n",
435 addr);
436 break;
437 }
438 return val;
439}
440
441static void malta_fpga_write(void *opaque, hwaddr addr,
442 uint64_t val, unsigned size)
443{
444 MaltaFPGAState *s = opaque;
445 uint32_t saddr;
446
447 saddr = (addr & 0xfffff);
448
449 switch (saddr) {
450
451
452 case 0x00200:
453 break;
454
455
456 case 0x00210:
457 break;
458
459
460 case 0x00408:
461 s->leds = val & 0xff;
462 malta_fpga_update_display(s);
463 break;
464
465
466 case 0x00410:
467 snprintf(s->display_text, 9, "%08X", (uint32_t)val);
468 malta_fpga_update_display(s);
469 break;
470
471
472 case 0x00418:
473 case 0x00420:
474 case 0x00428:
475 case 0x00430:
476 case 0x00438:
477 case 0x00440:
478 case 0x00448:
479 case 0x00450:
480 s->display_text[(saddr - 0x00418) >> 3] = (char) val;
481 malta_fpga_update_display(s);
482 break;
483
484
485 case 0x00500:
486 if (val == 0x42) {
487 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
488 }
489 break;
490
491
492 case 0x00508:
493 s->brk = val & 0xff;
494 break;
495
496
497
498
499 case 0x00a00:
500 s->gpout = val & 0xff;
501 break;
502
503
504 case 0x00b08:
505 s->i2coe = val & 0x03;
506 break;
507
508
509 case 0x00b10:
510 eeprom24c0x_write(&spd_eeprom, val & 0x02, val & 0x01);
511 s->i2cout = val;
512 break;
513
514
515 case 0x00b18:
516 s->i2csel = val & 0x01;
517 break;
518
519 default:
520 qemu_log_mask(LOG_GUEST_ERROR,
521 "malta_fpga_write: Bad register addr 0x%"HWADDR_PRIX"\n",
522 addr);
523 break;
524 }
525}
526
527static const MemoryRegionOps malta_fpga_ops = {
528 .read = malta_fpga_read,
529 .write = malta_fpga_write,
530 .endianness = DEVICE_NATIVE_ENDIAN,
531};
532
533static void malta_fpga_reset(void *opaque)
534{
535 MaltaFPGAState *s = opaque;
536
537 s->leds = 0x00;
538 s->brk = 0x0a;
539 s->gpout = 0x00;
540 s->i2cin = 0x3;
541 s->i2coe = 0x0;
542 s->i2cout = 0x3;
543 s->i2csel = 0x1;
544
545 s->display_text[8] = '\0';
546 snprintf(s->display_text, 9, " ");
547}
548
549static void malta_fgpa_display_event(void *opaque, QEMUChrEvent event)
550{
551 MaltaFPGAState *s = opaque;
552
553 if (event == CHR_EVENT_OPENED && !s->display_inited) {
554 qemu_chr_fe_printf(&s->display, "\e[HMalta LEDBAR\r\n");
555 qemu_chr_fe_printf(&s->display, "+--------+\r\n");
556 qemu_chr_fe_printf(&s->display, "+ +\r\n");
557 qemu_chr_fe_printf(&s->display, "+--------+\r\n");
558 qemu_chr_fe_printf(&s->display, "\n");
559 qemu_chr_fe_printf(&s->display, "Malta ASCII\r\n");
560 qemu_chr_fe_printf(&s->display, "+--------+\r\n");
561 qemu_chr_fe_printf(&s->display, "+ +\r\n");
562 qemu_chr_fe_printf(&s->display, "+--------+\r\n");
563 s->display_inited = true;
564 }
565}
566
567static MaltaFPGAState *malta_fpga_init(MemoryRegion *address_space,
568 hwaddr base, qemu_irq uart_irq, Chardev *uart_chr)
569{
570 MaltaFPGAState *s;
571 Chardev *chr;
572
573 s = g_new0(MaltaFPGAState, 1);
574
575 memory_region_init_io(&s->iomem, NULL, &malta_fpga_ops, s,
576 "malta-fpga", 0x100000);
577 memory_region_init_alias(&s->iomem_lo, NULL, "malta-fpga",
578 &s->iomem, 0, 0x900);
579 memory_region_init_alias(&s->iomem_hi, NULL, "malta-fpga",
580 &s->iomem, 0xa00, 0x100000 - 0xa00);
581
582 memory_region_add_subregion(address_space, base, &s->iomem_lo);
583 memory_region_add_subregion(address_space, base + 0xa00, &s->iomem_hi);
584
585 chr = qemu_chr_new("fpga", "vc:320x200", NULL);
586 qemu_chr_fe_init(&s->display, chr, NULL);
587 qemu_chr_fe_set_handlers(&s->display, NULL, NULL,
588 malta_fgpa_display_event, NULL, s, NULL, true);
589
590 s->uart = serial_mm_init(address_space, base + 0x900, 3, uart_irq,
591 230400, uart_chr, DEVICE_NATIVE_ENDIAN);
592
593 malta_fpga_reset(s);
594 qemu_register_reset(malta_fpga_reset, s);
595
596 return s;
597}
598
599
600static void network_init(PCIBus *pci_bus)
601{
602 int i;
603
604 for (i = 0; i < nb_nics; i++) {
605 NICInfo *nd = &nd_table[i];
606 const char *default_devaddr = NULL;
607
608 if (i == 0 && (!nd->model || strcmp(nd->model, "pcnet") == 0))
609
610 default_devaddr = "0b";
611
612 pci_nic_init_nofail(nd, pci_bus, "pcnet", default_devaddr);
613 }
614}
615
616static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr,
617 uint64_t kernel_entry)
618{
619 uint16_t *p;
620
621
622 p = (uint16_t *)base;
623
624#define NM_HI1(VAL) (((VAL) >> 16) & 0x1f)
625#define NM_HI2(VAL) \
626 (((VAL) & 0xf000) | (((VAL) >> 19) & 0xffc) | (((VAL) >> 31) & 0x1))
627#define NM_LO(VAL) ((VAL) & 0xfff)
628
629 stw_p(p++, 0x2800); stw_p(p++, 0x001c);
630
631 stw_p(p++, 0x8000); stw_p(p++, 0xc000);
632
633 stw_p(p++, 0x8000); stw_p(p++, 0xc000);
634
635 stw_p(p++, 0x8000); stw_p(p++, 0xc000);
636
637 stw_p(p++, 0x8000); stw_p(p++, 0xc000);
638
639 stw_p(p++, 0x8000); stw_p(p++, 0xc000);
640
641 stw_p(p++, 0x8000); stw_p(p++, 0xc000);
642
643 stw_p(p++, 0x8000); stw_p(p++, 0xc000);
644
645
646
647 if (semihosting_get_argc()) {
648
649 stw_p(p++, 0x8000); stw_p(p++, 0xc000);
650
651 } else {
652 stw_p(p++, 0x0080); stw_p(p++, 0x0002);
653
654 }
655
656 stw_p(p++, 0xe3a0 | NM_HI1(ENVP_VADDR - 64));
657
658 stw_p(p++, NM_HI2(ENVP_VADDR - 64));
659
660
661 stw_p(p++, 0x83bd); stw_p(p++, NM_LO(ENVP_VADDR - 64));
662
663
664 stw_p(p++, 0xe0a0 | NM_HI1(ENVP_VADDR));
665
666 stw_p(p++, NM_HI2(ENVP_VADDR));
667
668
669 stw_p(p++, 0x80a5); stw_p(p++, NM_LO(ENVP_VADDR));
670
671
672 stw_p(p++, 0xe0c0 | NM_HI1(ENVP_VADDR + 8));
673
674 stw_p(p++, NM_HI2(ENVP_VADDR + 8));
675
676
677 stw_p(p++, 0x80c6); stw_p(p++, NM_LO(ENVP_VADDR + 8));
678
679
680 stw_p(p++, 0xe0e0 | NM_HI1(loaderparams.ram_low_size));
681
682 stw_p(p++, NM_HI2(loaderparams.ram_low_size));
683
684
685 stw_p(p++, 0x80e7); stw_p(p++, NM_LO(loaderparams.ram_low_size));
686
687
688
689
690
691
692
693
694
695
696 stw_p(p++, 0xe040); stw_p(p++, 0x0681);
697
698
699#ifdef TARGET_WORDS_BIGENDIAN
700
701 stw_p(p++, 0xe020); stw_p(p++, 0x0be1);
702
703
704
705 stw_p(p++, 0x8422); stw_p(p++, 0x9068);
706
707
708 stw_p(p++, 0xe040); stw_p(p++, 0x077d);
709
710
711 stw_p(p++, 0xe020); stw_p(p++, 0x0801);
712
713
714
715 stw_p(p++, 0x8422); stw_p(p++, 0x9048);
716
717
718 stw_p(p++, 0xe020); stw_p(p++, 0x0800);
719
720
721
722 stw_p(p++, 0x8422); stw_p(p++, 0x9050);
723
724
725 stw_p(p++, 0xe020); stw_p(p++, 0x0001);
726
727
728
729 stw_p(p++, 0x8422); stw_p(p++, 0x9058);
730
731
732 stw_p(p++, 0xe020); stw_p(p++, 0x07e0);
733
734
735
736 stw_p(p++, 0x8422); stw_p(p++, 0x9060);
737
738
739 stw_p(p++, 0xe020); stw_p(p++, 0x0821);
740
741
742
743 stw_p(p++, 0x8422); stw_p(p++, 0x9080);
744
745
746 stw_p(p++, 0xe020); stw_p(p++, 0x0bc0);
747
748
749#else
750
751 stw_p(p++, 0x0020); stw_p(p++, 0x00df);
752
753
754
755 stw_p(p++, 0x8422); stw_p(p++, 0x9068);
756
757
758
759 stw_p(p++, 0xe040); stw_p(p++, 0x077d);
760
761
762 stw_p(p++, 0x0020); stw_p(p++, 0x00c0);
763
764
765
766 stw_p(p++, 0x8422); stw_p(p++, 0x9048);
767
768
769 stw_p(p++, 0x0020); stw_p(p++, 0x0040);
770
771
772
773 stw_p(p++, 0x8422); stw_p(p++, 0x9050);
774
775
776 stw_p(p++, 0x0020); stw_p(p++, 0x0080);
777
778
779
780 stw_p(p++, 0x8422); stw_p(p++, 0x9058);
781
782
783 stw_p(p++, 0x0020); stw_p(p++, 0x003f);
784
785
786
787 stw_p(p++, 0x8422); stw_p(p++, 0x9060);
788
789
790 stw_p(p++, 0x0020); stw_p(p++, 0x00c1);
791
792
793
794 stw_p(p++, 0x8422); stw_p(p++, 0x9080);
795
796
797 stw_p(p++, 0x0020); stw_p(p++, 0x005e);
798
799
800#endif
801
802
803 stw_p(p++, 0x8422); stw_p(p++, 0x9088);
804
805
806 stw_p(p++, 0xe320 | NM_HI1(kernel_entry));
807
808 stw_p(p++, NM_HI2(kernel_entry));
809
810
811 stw_p(p++, 0x8339); stw_p(p++, NM_LO(kernel_entry));
812
813
814 stw_p(p++, 0x4bf9); stw_p(p++, 0x0000);
815
816}
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840static void write_bootloader(uint8_t *base, uint64_t run_addr,
841 uint64_t kernel_entry)
842{
843 uint32_t *p;
844
845
846 p = (uint32_t *)base;
847
848 stl_p(p++, 0x08000000 |
849 ((run_addr + 0x580) & 0x0fffffff) >> 2);
850 stl_p(p++, 0x00000000);
851
852
853 stl_p(base + 0x500, run_addr + 0x0580);
854 stl_p(base + 0x504, run_addr + 0x083c);
855 stl_p(base + 0x520, run_addr + 0x0580);
856 stl_p(base + 0x52c, run_addr + 0x0800);
857 stl_p(base + 0x534, run_addr + 0x0808);
858 stl_p(base + 0x538, run_addr + 0x0800);
859 stl_p(base + 0x53c, run_addr + 0x0800);
860 stl_p(base + 0x540, run_addr + 0x0800);
861 stl_p(base + 0x544, run_addr + 0x0800);
862 stl_p(base + 0x548, run_addr + 0x0800);
863 stl_p(base + 0x54c, run_addr + 0x0800);
864 stl_p(base + 0x550, run_addr + 0x0800);
865 stl_p(base + 0x554, run_addr + 0x0800);
866
867
868
869 p = (uint32_t *) (base + 0x580);
870
871 if (semihosting_get_argc()) {
872
873 stl_p(p++, 0x00000000);
874 } else {
875 stl_p(p++, 0x24040002);
876 }
877
878
879 stl_p(p++, 0x3c1d0000 | (((ENVP_VADDR - 64) >> 16) & 0xffff));
880
881 stl_p(p++, 0x37bd0000 | ((ENVP_VADDR - 64) & 0xffff));
882
883 stl_p(p++, 0x3c050000 | ((ENVP_VADDR >> 16) & 0xffff));
884
885 stl_p(p++, 0x34a50000 | (ENVP_VADDR & 0xffff));
886
887 stl_p(p++, 0x3c060000 | (((ENVP_VADDR + 8) >> 16) & 0xffff));
888
889 stl_p(p++, 0x34c60000 | ((ENVP_VADDR + 8) & 0xffff));
890
891 stl_p(p++, 0x3c070000 | (loaderparams.ram_low_size >> 16));
892
893 stl_p(p++, 0x34e70000 | (loaderparams.ram_low_size & 0xffff));
894
895
896 stl_p(p++, 0x3c09b400);
897
898#ifdef TARGET_WORDS_BIGENDIAN
899 stl_p(p++, 0x3c08df00);
900#else
901 stl_p(p++, 0x340800df);
902#endif
903 stl_p(p++, 0xad280068);
904
905 stl_p(p++, 0x3c09bbe0);
906
907#ifdef TARGET_WORDS_BIGENDIAN
908 stl_p(p++, 0x3c08c000);
909#else
910 stl_p(p++, 0x340800c0);
911#endif
912 stl_p(p++, 0xad280048);
913#ifdef TARGET_WORDS_BIGENDIAN
914 stl_p(p++, 0x3c084000);
915#else
916 stl_p(p++, 0x34080040);
917#endif
918 stl_p(p++, 0xad280050);
919
920#ifdef TARGET_WORDS_BIGENDIAN
921 stl_p(p++, 0x3c088000);
922#else
923 stl_p(p++, 0x34080080);
924#endif
925 stl_p(p++, 0xad280058);
926#ifdef TARGET_WORDS_BIGENDIAN
927 stl_p(p++, 0x3c083f00);
928#else
929 stl_p(p++, 0x3408003f);
930#endif
931 stl_p(p++, 0xad280060);
932
933#ifdef TARGET_WORDS_BIGENDIAN
934 stl_p(p++, 0x3c08c100);
935#else
936 stl_p(p++, 0x340800c1);
937#endif
938 stl_p(p++, 0xad280080);
939#ifdef TARGET_WORDS_BIGENDIAN
940 stl_p(p++, 0x3c085e00);
941#else
942 stl_p(p++, 0x3408005e);
943#endif
944 stl_p(p++, 0xad280088);
945
946
947 stl_p(p++, 0x3c1f0000 |
948 ((kernel_entry >> 16) & 0xffff));
949 stl_p(p++, 0x37ff0000 |
950 (kernel_entry & 0xffff));
951 stl_p(p++, 0x03e00009);
952 stl_p(p++, 0x00000000);
953
954
955 p = (uint32_t *) (base + 0x800);
956 stl_p(p++, 0x03e00009);
957 stl_p(p++, 0x24020000);
958
959 stl_p(p++, 0x03e06821);
960 stl_p(p++, 0x00805821);
961 stl_p(p++, 0x00a05021);
962 stl_p(p++, 0x91440000);
963 stl_p(p++, 0x254a0001);
964 stl_p(p++, 0x10800005);
965 stl_p(p++, 0x00000000);
966 stl_p(p++, 0x0ff0021c);
967 stl_p(p++, 0x00000000);
968 stl_p(p++, 0x1000fff9);
969 stl_p(p++, 0x00000000);
970 stl_p(p++, 0x01a00009);
971 stl_p(p++, 0x01602021);
972
973 stl_p(p++, 0x03e06821);
974 stl_p(p++, 0x00805821);
975 stl_p(p++, 0x00a05021);
976 stl_p(p++, 0x00c06021);
977 stl_p(p++, 0x91440000);
978 stl_p(p++, 0x0ff0021c);
979 stl_p(p++, 0x00000000);
980 stl_p(p++, 0x254a0001);
981 stl_p(p++, 0x258cffff);
982 stl_p(p++, 0x1580fffa);
983 stl_p(p++, 0x00000000);
984 stl_p(p++, 0x01a00009);
985 stl_p(p++, 0x01602021);
986
987 stl_p(p++, 0x3c08b800);
988 stl_p(p++, 0x350803f8);
989 stl_p(p++, 0x91090005);
990 stl_p(p++, 0x00000000);
991 stl_p(p++, 0x31290040);
992 stl_p(p++, 0x1120fffc);
993 stl_p(p++, 0x00000000);
994 stl_p(p++, 0x03e00009);
995 stl_p(p++, 0xa1040000);
996
997}
998
999static void GCC_FMT_ATTR(3, 4) prom_set(uint32_t *prom_buf, int index,
1000 const char *string, ...)
1001{
1002 va_list ap;
1003 uint32_t table_addr;
1004
1005 if (index >= ENVP_NB_ENTRIES) {
1006 return;
1007 }
1008
1009 if (string == NULL) {
1010 prom_buf[index] = 0;
1011 return;
1012 }
1013
1014 table_addr = sizeof(uint32_t) * ENVP_NB_ENTRIES + index * ENVP_ENTRY_SIZE;
1015 prom_buf[index] = tswap32(ENVP_VADDR + table_addr);
1016
1017 va_start(ap, string);
1018 vsnprintf((char *)prom_buf + table_addr, ENVP_ENTRY_SIZE, string, ap);
1019 va_end(ap);
1020}
1021
1022
1023static uint64_t load_kernel(void)
1024{
1025 uint64_t kernel_entry, kernel_high, initrd_size;
1026 long kernel_size;
1027 ram_addr_t initrd_offset;
1028 int big_endian;
1029 uint32_t *prom_buf;
1030 long prom_size;
1031 int prom_index = 0;
1032 uint64_t (*xlate_to_kseg0) (void *opaque, uint64_t addr);
1033
1034#ifdef TARGET_WORDS_BIGENDIAN
1035 big_endian = 1;
1036#else
1037 big_endian = 0;
1038#endif
1039
1040 kernel_size = load_elf(loaderparams.kernel_filename, NULL,
1041 cpu_mips_kseg0_to_phys, NULL,
1042 &kernel_entry, NULL,
1043 &kernel_high, NULL, big_endian, EM_MIPS,
1044 1, 0);
1045 if (kernel_size < 0) {
1046 error_report("could not load kernel '%s': %s",
1047 loaderparams.kernel_filename,
1048 load_elf_strerror(kernel_size));
1049 exit(1);
1050 }
1051
1052
1053 if (kernel_entry & 0x80000000ll) {
1054 if (kvm_enabled()) {
1055 error_report("KVM guest kernels must be linked in useg. "
1056 "Did you forget to enable CONFIG_KVM_GUEST?");
1057 exit(1);
1058 }
1059
1060 xlate_to_kseg0 = cpu_mips_phys_to_kseg0;
1061 } else {
1062
1063 mips_um_ksegs_enable();
1064
1065 xlate_to_kseg0 = cpu_mips_kvm_um_phys_to_kseg0;
1066 }
1067
1068
1069 initrd_size = 0;
1070 initrd_offset = 0;
1071 if (loaderparams.initrd_filename) {
1072 initrd_size = get_image_size(loaderparams.initrd_filename);
1073 if (initrd_size > 0) {
1074
1075
1076
1077
1078
1079 initrd_offset = ROUND_UP(loaderparams.ram_low_size
1080 - (initrd_size + 128 * KiB),
1081 INITRD_PAGE_SIZE);
1082 if (kernel_high >= initrd_offset) {
1083 error_report("memory too small for initial ram disk '%s'",
1084 loaderparams.initrd_filename);
1085 exit(1);
1086 }
1087 initrd_size = load_image_targphys(loaderparams.initrd_filename,
1088 initrd_offset,
1089 loaderparams.ram_size - initrd_offset);
1090 }
1091 if (initrd_size == (target_ulong) -1) {
1092 error_report("could not load initial ram disk '%s'",
1093 loaderparams.initrd_filename);
1094 exit(1);
1095 }
1096 }
1097
1098
1099 prom_size = ENVP_NB_ENTRIES * (sizeof(int32_t) + ENVP_ENTRY_SIZE);
1100 prom_buf = g_malloc(prom_size);
1101
1102 prom_set(prom_buf, prom_index++, "%s", loaderparams.kernel_filename);
1103 if (initrd_size > 0) {
1104 prom_set(prom_buf, prom_index++,
1105 "rd_start=0x%" PRIx64 " rd_size=%" PRId64 " %s",
1106 xlate_to_kseg0(NULL, initrd_offset),
1107 initrd_size, loaderparams.kernel_cmdline);
1108 } else {
1109 prom_set(prom_buf, prom_index++, "%s", loaderparams.kernel_cmdline);
1110 }
1111
1112 prom_set(prom_buf, prom_index++, "memsize");
1113 prom_set(prom_buf, prom_index++, "%u", loaderparams.ram_low_size);
1114
1115 prom_set(prom_buf, prom_index++, "ememsize");
1116 prom_set(prom_buf, prom_index++, "%u", loaderparams.ram_size);
1117
1118 prom_set(prom_buf, prom_index++, "modetty0");
1119 prom_set(prom_buf, prom_index++, "38400n8r");
1120 prom_set(prom_buf, prom_index++, NULL);
1121
1122 rom_add_blob_fixed("prom", prom_buf, prom_size, ENVP_PADDR);
1123
1124 g_free(prom_buf);
1125 return kernel_entry;
1126}
1127
1128static void malta_mips_config(MIPSCPU *cpu)
1129{
1130 MachineState *ms = MACHINE(qdev_get_machine());
1131 unsigned int smp_cpus = ms->smp.cpus;
1132 CPUMIPSState *env = &cpu->env;
1133 CPUState *cs = CPU(cpu);
1134
1135 if (ase_mt_available(env)) {
1136 env->mvp->CP0_MVPConf0 = deposit32(env->mvp->CP0_MVPConf0,
1137 CP0MVPC0_PTC, 8,
1138 smp_cpus * cs->nr_threads - 1);
1139 env->mvp->CP0_MVPConf0 = deposit32(env->mvp->CP0_MVPConf0,
1140 CP0MVPC0_PVPE, 4, smp_cpus - 1);
1141 }
1142}
1143
1144static void main_cpu_reset(void *opaque)
1145{
1146 MIPSCPU *cpu = opaque;
1147 CPUMIPSState *env = &cpu->env;
1148
1149 cpu_reset(CPU(cpu));
1150
1151
1152
1153
1154
1155
1156 if (loaderparams.kernel_filename) {
1157 env->CP0_Status &= ~(1 << CP0St_ERL);
1158 }
1159
1160 malta_mips_config(cpu);
1161
1162 if (kvm_enabled()) {
1163
1164 env->active_tc.PC = 0x40000000 + loaderparams.ram_low_size;
1165 }
1166}
1167
1168static void create_cpu_without_cps(MachineState *ms, MaltaState *s,
1169 qemu_irq *cbus_irq, qemu_irq *i8259_irq)
1170{
1171 CPUMIPSState *env;
1172 MIPSCPU *cpu;
1173 int i;
1174
1175 for (i = 0; i < ms->smp.cpus; i++) {
1176 cpu = mips_cpu_create_with_clock(ms->cpu_type, s->cpuclk);
1177
1178
1179 cpu_mips_irq_init_cpu(cpu);
1180 cpu_mips_clock_init(cpu);
1181 qemu_register_reset(main_cpu_reset, cpu);
1182 }
1183
1184 cpu = MIPS_CPU(first_cpu);
1185 env = &cpu->env;
1186 *i8259_irq = env->irq[2];
1187 *cbus_irq = env->irq[4];
1188}
1189
1190static void create_cps(MachineState *ms, MaltaState *s,
1191 qemu_irq *cbus_irq, qemu_irq *i8259_irq)
1192{
1193 object_initialize_child(OBJECT(s), "cps", &s->cps, TYPE_MIPS_CPS);
1194 object_property_set_str(OBJECT(&s->cps), "cpu-type", ms->cpu_type,
1195 &error_fatal);
1196 object_property_set_int(OBJECT(&s->cps), "num-vp", ms->smp.cpus,
1197 &error_fatal);
1198 qdev_connect_clock_in(DEVICE(&s->cps), "clk-in", s->cpuclk);
1199 sysbus_realize(SYS_BUS_DEVICE(&s->cps), &error_fatal);
1200
1201 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->cps), 0, 0, 1);
1202
1203 *i8259_irq = get_cps_irq(&s->cps, 3);
1204 *cbus_irq = NULL;
1205}
1206
1207static void mips_create_cpu(MachineState *ms, MaltaState *s,
1208 qemu_irq *cbus_irq, qemu_irq *i8259_irq)
1209{
1210 if ((ms->smp.cpus > 1) && cpu_type_supports_cps_smp(ms->cpu_type)) {
1211 create_cps(ms, s, cbus_irq, i8259_irq);
1212 } else {
1213 create_cpu_without_cps(ms, s, cbus_irq, i8259_irq);
1214 }
1215}
1216
1217static
1218void mips_malta_init(MachineState *machine)
1219{
1220 ram_addr_t ram_size = machine->ram_size;
1221 ram_addr_t ram_low_size;
1222 const char *kernel_filename = machine->kernel_filename;
1223 const char *kernel_cmdline = machine->kernel_cmdline;
1224 const char *initrd_filename = machine->initrd_filename;
1225 char *filename;
1226 PFlashCFI01 *fl;
1227 MemoryRegion *system_memory = get_system_memory();
1228 MemoryRegion *ram_low_preio = g_new(MemoryRegion, 1);
1229 MemoryRegion *ram_low_postio;
1230 MemoryRegion *bios, *bios_copy = g_new(MemoryRegion, 1);
1231 const size_t smbus_eeprom_size = 8 * 256;
1232 uint8_t *smbus_eeprom_buf = g_malloc0(smbus_eeprom_size);
1233 uint64_t kernel_entry, bootloader_run_addr;
1234 PCIBus *pci_bus;
1235 ISABus *isa_bus;
1236 qemu_irq cbus_irq, i8259_irq;
1237 I2CBus *smbus;
1238 DriveInfo *dinfo;
1239 int fl_idx = 0;
1240 int be;
1241 MaltaState *s;
1242 DeviceState *dev;
1243
1244 s = MIPS_MALTA(qdev_new(TYPE_MIPS_MALTA));
1245 sysbus_realize_and_unref(SYS_BUS_DEVICE(s), &error_fatal);
1246
1247
1248 mips_create_cpu(machine, s, &cbus_irq, &i8259_irq);
1249
1250
1251 if (ram_size > 2 * GiB) {
1252 error_report("Too much memory for this machine: %" PRId64 "MB,"
1253 " maximum 2048MB", ram_size / MiB);
1254 exit(1);
1255 }
1256
1257
1258 memory_region_add_subregion(system_memory, 0x80000000, machine->ram);
1259
1260
1261 memory_region_init_alias(ram_low_preio, NULL, "mips_malta_low_preio.ram",
1262 machine->ram, 0, MIN(ram_size, 256 * MiB));
1263 memory_region_add_subregion(system_memory, 0, ram_low_preio);
1264
1265
1266 if (ram_size > 512 * MiB) {
1267 ram_low_postio = g_new(MemoryRegion, 1);
1268 memory_region_init_alias(ram_low_postio, NULL,
1269 "mips_malta_low_postio.ram",
1270 machine->ram, 512 * MiB,
1271 ram_size - 512 * MiB);
1272 memory_region_add_subregion(system_memory, 512 * MiB,
1273 ram_low_postio);
1274 }
1275
1276#ifdef TARGET_WORDS_BIGENDIAN
1277 be = 1;
1278#else
1279 be = 0;
1280#endif
1281
1282
1283
1284
1285 malta_fpga_init(system_memory, FPGA_ADDRESS, cbus_irq, serial_hd(2));
1286
1287
1288 dinfo = drive_get(IF_PFLASH, 0, fl_idx);
1289 fl = pflash_cfi01_register(FLASH_ADDRESS, "mips_malta.bios",
1290 FLASH_SIZE,
1291 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
1292 65536,
1293 4, 0x0000, 0x0000, 0x0000, 0x0000, be);
1294 bios = pflash_cfi01_get_memory(fl);
1295 fl_idx++;
1296 if (kernel_filename) {
1297 ram_low_size = MIN(ram_size, 256 * MiB);
1298
1299 if (kvm_enabled()) {
1300 ram_low_size -= 0x100000;
1301 bootloader_run_addr = cpu_mips_kvm_um_phys_to_kseg0(NULL, ram_low_size);
1302 } else {
1303 bootloader_run_addr = cpu_mips_phys_to_kseg0(NULL, RESET_ADDRESS);
1304 }
1305
1306
1307 loaderparams.ram_size = ram_size;
1308 loaderparams.ram_low_size = ram_low_size;
1309 loaderparams.kernel_filename = kernel_filename;
1310 loaderparams.kernel_cmdline = kernel_cmdline;
1311 loaderparams.initrd_filename = initrd_filename;
1312 kernel_entry = load_kernel();
1313
1314 if (!cpu_type_supports_isa(machine->cpu_type, ISA_NANOMIPS32)) {
1315 write_bootloader(memory_region_get_ram_ptr(bios),
1316 bootloader_run_addr, kernel_entry);
1317 } else {
1318 write_bootloader_nanomips(memory_region_get_ram_ptr(bios),
1319 bootloader_run_addr, kernel_entry);
1320 }
1321 if (kvm_enabled()) {
1322
1323 write_bootloader(memory_region_get_ram_ptr(ram_low_preio) +
1324 ram_low_size,
1325 bootloader_run_addr, kernel_entry);
1326 }
1327 } else {
1328 target_long bios_size = FLASH_SIZE;
1329
1330 if (kvm_enabled()) {
1331 error_report("KVM enabled but no -kernel argument was specified. "
1332 "Booting from flash is not supported with KVM.");
1333 exit(1);
1334 }
1335
1336 if (!dinfo) {
1337
1338 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS,
1339 machine->firmware ?: BIOS_FILENAME);
1340 if (filename) {
1341 bios_size = load_image_targphys(filename, FLASH_ADDRESS,
1342 BIOS_SIZE);
1343 g_free(filename);
1344 } else {
1345 bios_size = -1;
1346 }
1347 if ((bios_size < 0 || bios_size > BIOS_SIZE) &&
1348 machine->firmware && !qtest_enabled()) {
1349 error_report("Could not load MIPS bios '%s'", machine->firmware);
1350 exit(1);
1351 }
1352 }
1353
1354
1355
1356
1357#ifndef TARGET_WORDS_BIGENDIAN
1358 {
1359 uint32_t *end, *addr;
1360 const size_t swapsize = MIN(bios_size, 0x3e0000);
1361 addr = rom_ptr(FLASH_ADDRESS, swapsize);
1362 if (!addr) {
1363 addr = memory_region_get_ram_ptr(bios);
1364 }
1365 end = (void *)addr + swapsize;
1366 while (addr < end) {
1367 bswap32s(addr);
1368 addr++;
1369 }
1370 }
1371#endif
1372 }
1373
1374
1375
1376
1377
1378
1379
1380 memory_region_init_ram(bios_copy, NULL, "bios.1fc", BIOS_SIZE,
1381 &error_fatal);
1382 if (!rom_copy(memory_region_get_ram_ptr(bios_copy),
1383 FLASH_ADDRESS, BIOS_SIZE)) {
1384 memcpy(memory_region_get_ram_ptr(bios_copy),
1385 memory_region_get_ram_ptr(bios), BIOS_SIZE);
1386 }
1387 memory_region_set_readonly(bios_copy, true);
1388 memory_region_add_subregion(system_memory, RESET_ADDRESS, bios_copy);
1389
1390
1391 stl_p(memory_region_get_ram_ptr(bios_copy) + 0x10, 0x00000420);
1392
1393
1394 pci_bus = gt64120_register(s->i8259);
1395
1396
1397
1398
1399
1400 empty_slot_init("GT64120", 0, 0x20000000);
1401
1402
1403 dev = piix4_create(pci_bus, &isa_bus, &smbus);
1404
1405
1406 qdev_connect_gpio_out_named(dev, "intr", 0, i8259_irq);
1407 for (int i = 0; i < ISA_NUM_IRQS; i++) {
1408 s->i8259[i] = qdev_get_gpio_in_named(dev, "isa", i);
1409 }
1410
1411
1412 generate_eeprom_spd(&smbus_eeprom_buf[0 * 256], ram_size);
1413 generate_eeprom_serial(&smbus_eeprom_buf[6 * 256]);
1414 smbus_eeprom_init(smbus, 8, smbus_eeprom_buf, smbus_eeprom_size);
1415 g_free(smbus_eeprom_buf);
1416
1417
1418 isa_create_simple(isa_bus, TYPE_FDC37M81X_SUPERIO);
1419
1420
1421 network_init(pci_bus);
1422
1423
1424 pci_vga_init(pci_bus);
1425}
1426
1427static void mips_malta_instance_init(Object *obj)
1428{
1429 MaltaState *s = MIPS_MALTA(obj);
1430
1431 s->cpuclk = qdev_init_clock_out(DEVICE(obj), "cpu-refclk");
1432 clock_set_hz(s->cpuclk, 320000000);
1433}
1434
1435static const TypeInfo mips_malta_device = {
1436 .name = TYPE_MIPS_MALTA,
1437 .parent = TYPE_SYS_BUS_DEVICE,
1438 .instance_size = sizeof(MaltaState),
1439 .instance_init = mips_malta_instance_init,
1440};
1441
1442static void mips_malta_machine_init(MachineClass *mc)
1443{
1444 mc->desc = "MIPS Malta Core LV";
1445 mc->init = mips_malta_init;
1446 mc->block_default_type = IF_IDE;
1447 mc->max_cpus = 16;
1448 mc->is_default = true;
1449#ifdef TARGET_MIPS64
1450 mc->default_cpu_type = MIPS_CPU_TYPE_NAME("20Kc");
1451#else
1452 mc->default_cpu_type = MIPS_CPU_TYPE_NAME("24Kf");
1453#endif
1454 mc->default_ram_id = "mips_malta.ram";
1455}
1456
1457DEFINE_MACHINE("malta", mips_malta_machine_init)
1458
1459static void mips_malta_register_types(void)
1460{
1461 type_register_static(&mips_malta_device);
1462}
1463
1464type_init(mips_malta_register_types)
1465