1#ifndef HW_PCNET_H
2#define HW_PCNET_H
3
4#define PCNET_IOPORT_SIZE 0x20
5#define PCNET_PNPMMIO_SIZE 0x20
6
7#define PCNET_LOOPTEST_CRC 1
8#define PCNET_LOOPTEST_NOCRC 2
9
10#include "exec/memory.h"
11#include "hw/irq.h"
12
13
14#define BCR_MSRDA 0
15#define BCR_MSWRA 1
16#define BCR_MC 2
17#define BCR_LNKST 4
18#define BCR_LED1 5
19#define BCR_LED2 6
20#define BCR_LED3 7
21#define BCR_FDC 9
22#define BCR_BSBC 18
23#define BCR_EECAS 19
24#define BCR_SWS 20
25#define BCR_PLAT 22
26
27#define BCR_TMAULOOP(S) !!((S)->bcr[BCR_MC ] & 0x4000)
28#define BCR_APROMWE(S) !!((S)->bcr[BCR_MC ] & 0x0100)
29#define BCR_DWIO(S) !!((S)->bcr[BCR_BSBC] & 0x0080)
30#define BCR_SSIZE32(S) !!((S)->bcr[BCR_SWS ] & 0x0100)
31#define BCR_SWSTYLE(S) ((S)->bcr[BCR_SWS ] & 0x00FF)
32
33typedef struct PCNetState_st PCNetState;
34
35struct PCNetState_st {
36 NICState *nic;
37 NICConf conf;
38 QEMUTimer *poll_timer;
39 int rap, isr, lnkst;
40 uint32_t rdra, tdra;
41 uint8_t prom[16];
42 uint16_t csr[128];
43 uint16_t bcr[32];
44 int xmit_pos;
45 uint64_t timer;
46 MemoryRegion mmio;
47 uint8_t buffer[4096];
48 qemu_irq irq;
49 void (*phys_mem_read)(void *dma_opaque, hwaddr addr,
50 uint8_t *buf, int len, int do_bswap);
51 void (*phys_mem_write)(void *dma_opaque, hwaddr addr,
52 uint8_t *buf, int len, int do_bswap);
53 DeviceState *dma_opaque;
54 int tx_busy;
55 int looptest;
56};
57
58void pcnet_h_reset(void *opaque);
59void pcnet_ioport_writew(void *opaque, uint32_t addr, uint32_t val);
60uint32_t pcnet_ioport_readw(void *opaque, uint32_t addr);
61void pcnet_ioport_writel(void *opaque, uint32_t addr, uint32_t val);
62uint32_t pcnet_ioport_readl(void *opaque, uint32_t addr);
63uint32_t pcnet_bcr_readw(PCNetState *s, uint32_t rap);
64ssize_t pcnet_receive(NetClientState *nc, const uint8_t *buf, size_t size_);
65void pcnet_set_link_status(NetClientState *nc);
66void pcnet_common_init(DeviceState *dev, PCNetState *s, NetClientInfo *info);
67extern const VMStateDescription vmstate_pcnet;
68#endif
69
