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18#include "qemu/osdep.h"
19#include "hw/hw.h"
20#include "hw/pci/pci.h"
21#include "hw/qdev-properties.h"
22#include "net/tap.h"
23#include "net/checksum.h"
24#include "sysemu/sysemu.h"
25#include "qemu/bswap.h"
26#include "qemu/log.h"
27#include "qemu/module.h"
28#include "hw/pci/msix.h"
29#include "hw/pci/msi.h"
30#include "migration/register.h"
31#include "migration/vmstate.h"
32
33#include "vmxnet3.h"
34#include "vmxnet3_defs.h"
35#include "vmxnet_debug.h"
36#include "vmware_utils.h"
37#include "net_tx_pkt.h"
38#include "net_rx_pkt.h"
39#include "qom/object.h"
40
41#define PCI_DEVICE_ID_VMWARE_VMXNET3_REVISION 0x1
42#define VMXNET3_MSIX_BAR_SIZE 0x2000
43#define MIN_BUF_SIZE 60
44
45
46#define VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS_BIT 0
47#define VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS \
48 (1 << VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS_BIT)
49#define VMXNET3_COMPAT_FLAG_DISABLE_PCIE_BIT 1
50#define VMXNET3_COMPAT_FLAG_DISABLE_PCIE \
51 (1 << VMXNET3_COMPAT_FLAG_DISABLE_PCIE_BIT)
52
53#define VMXNET3_EXP_EP_OFFSET (0x48)
54#define VMXNET3_MSI_OFFSET(s) \
55 ((s)->compat_flags & VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS ? 0x50 : 0x84)
56#define VMXNET3_MSIX_OFFSET(s) \
57 ((s)->compat_flags & VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS ? 0 : 0x9c)
58#define VMXNET3_DSN_OFFSET (0x100)
59
60#define VMXNET3_BAR0_IDX (0)
61#define VMXNET3_BAR1_IDX (1)
62#define VMXNET3_MSIX_BAR_IDX (2)
63
64#define VMXNET3_OFF_MSIX_TABLE (0x000)
65#define VMXNET3_OFF_MSIX_PBA(s) \
66 ((s)->compat_flags & VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS ? 0x800 : 0x1000)
67
68
69#define VMXNET3_LINK_SPEED (1000 << 16)
70
71
72#define VMXNET3_LINK_STATUS_UP 0x1
73
74
75#define VMXNET3_UPT_REVISION 0x1
76#define VMXNET3_DEVICE_REVISION 0x1
77
78
79#define VMXNET3_MAX_NMSIX_INTRS (1)
80
81
82#define VMXNET3_READ_TX_QUEUE_DESCR8(_d, dpa, field) \
83 (vmw_shmem_ld8(_d, dpa + offsetof(struct Vmxnet3_TxQueueDesc, field)))
84
85#define VMXNET3_WRITE_TX_QUEUE_DESCR8(_d, dpa, field, value) \
86 (vmw_shmem_st8(_d, dpa + offsetof(struct Vmxnet3_TxQueueDesc, field, value)))
87
88#define VMXNET3_READ_TX_QUEUE_DESCR32(_d, dpa, field) \
89 (vmw_shmem_ld32(_d, dpa + offsetof(struct Vmxnet3_TxQueueDesc, field)))
90
91#define VMXNET3_WRITE_TX_QUEUE_DESCR32(_d, dpa, field, value) \
92 (vmw_shmem_st32(_d, dpa + offsetof(struct Vmxnet3_TxQueueDesc, field), value))
93
94#define VMXNET3_READ_TX_QUEUE_DESCR64(_d, dpa, field) \
95 (vmw_shmem_ld64(_d, dpa + offsetof(struct Vmxnet3_TxQueueDesc, field)))
96
97#define VMXNET3_WRITE_TX_QUEUE_DESCR64(_d, dpa, field, value) \
98 (vmw_shmem_st64(_d, dpa + offsetof(struct Vmxnet3_TxQueueDesc, field), value))
99
100#define VMXNET3_READ_RX_QUEUE_DESCR64(_d, dpa, field) \
101 (vmw_shmem_ld64(_d, dpa + offsetof(struct Vmxnet3_RxQueueDesc, field)))
102
103#define VMXNET3_READ_RX_QUEUE_DESCR32(_d, dpa, field) \
104 (vmw_shmem_ld32(_d, dpa + offsetof(struct Vmxnet3_RxQueueDesc, field)))
105
106#define VMXNET3_WRITE_RX_QUEUE_DESCR64(_d, dpa, field, value) \
107 (vmw_shmem_st64(_d, dpa + offsetof(struct Vmxnet3_RxQueueDesc, field), value))
108
109#define VMXNET3_WRITE_RX_QUEUE_DESCR8(_d, dpa, field, value) \
110 (vmw_shmem_st8(_d, dpa + offsetof(struct Vmxnet3_RxQueueDesc, field), value))
111
112
113#define VMXNET3_READ_DRV_SHARED64(_d, shpa, field) \
114 (vmw_shmem_ld64(_d, shpa + offsetof(struct Vmxnet3_DriverShared, field)))
115
116#define VMXNET3_READ_DRV_SHARED32(_d, shpa, field) \
117 (vmw_shmem_ld32(_d, shpa + offsetof(struct Vmxnet3_DriverShared, field)))
118
119#define VMXNET3_WRITE_DRV_SHARED32(_d, shpa, field, val) \
120 (vmw_shmem_st32(_d, shpa + offsetof(struct Vmxnet3_DriverShared, field), val))
121
122#define VMXNET3_READ_DRV_SHARED16(_d, shpa, field) \
123 (vmw_shmem_ld16(_d, shpa + offsetof(struct Vmxnet3_DriverShared, field)))
124
125#define VMXNET3_READ_DRV_SHARED8(_d, shpa, field) \
126 (vmw_shmem_ld8(_d, shpa + offsetof(struct Vmxnet3_DriverShared, field)))
127
128#define VMXNET3_READ_DRV_SHARED(_d, shpa, field, b, l) \
129 (vmw_shmem_read(_d, shpa + offsetof(struct Vmxnet3_DriverShared, field), b, l))
130
131#define VMXNET_FLAG_IS_SET(field, flag) (((field) & (flag)) == (flag))
132
133struct VMXNET3Class {
134 PCIDeviceClass parent_class;
135 DeviceRealize parent_dc_realize;
136};
137typedef struct VMXNET3Class VMXNET3Class;
138
139DECLARE_CLASS_CHECKERS(VMXNET3Class, VMXNET3_DEVICE,
140 TYPE_VMXNET3)
141
142static inline void vmxnet3_ring_init(PCIDevice *d,
143 Vmxnet3Ring *ring,
144 hwaddr pa,
145 uint32_t size,
146 uint32_t cell_size,
147 bool zero_region)
148{
149 ring->pa = pa;
150 ring->size = size;
151 ring->cell_size = cell_size;
152 ring->gen = VMXNET3_INIT_GEN;
153 ring->next = 0;
154
155 if (zero_region) {
156 vmw_shmem_set(d, pa, 0, size * cell_size);
157 }
158}
159
160#define VMXNET3_RING_DUMP(macro, ring_name, ridx, r) \
161 macro("%s#%d: base %" PRIx64 " size %u cell_size %u gen %d next %u", \
162 (ring_name), (ridx), \
163 (r)->pa, (r)->size, (r)->cell_size, (r)->gen, (r)->next)
164
165static inline void vmxnet3_ring_inc(Vmxnet3Ring *ring)
166{
167 if (++ring->next >= ring->size) {
168 ring->next = 0;
169 ring->gen ^= 1;
170 }
171}
172
173static inline void vmxnet3_ring_dec(Vmxnet3Ring *ring)
174{
175 if (ring->next-- == 0) {
176 ring->next = ring->size - 1;
177 ring->gen ^= 1;
178 }
179}
180
181static inline hwaddr vmxnet3_ring_curr_cell_pa(Vmxnet3Ring *ring)
182{
183 return ring->pa + ring->next * ring->cell_size;
184}
185
186static inline void vmxnet3_ring_read_curr_cell(PCIDevice *d, Vmxnet3Ring *ring,
187 void *buff)
188{
189 vmw_shmem_read(d, vmxnet3_ring_curr_cell_pa(ring), buff, ring->cell_size);
190}
191
192static inline void vmxnet3_ring_write_curr_cell(PCIDevice *d, Vmxnet3Ring *ring,
193 void *buff)
194{
195 vmw_shmem_write(d, vmxnet3_ring_curr_cell_pa(ring), buff, ring->cell_size);
196}
197
198static inline size_t vmxnet3_ring_curr_cell_idx(Vmxnet3Ring *ring)
199{
200 return ring->next;
201}
202
203static inline uint8_t vmxnet3_ring_curr_gen(Vmxnet3Ring *ring)
204{
205 return ring->gen;
206}
207
208
209static inline void
210vmxnet3_dump_tx_descr(struct Vmxnet3_TxDesc *descr)
211{
212 VMW_PKPRN("TX DESCR: "
213 "addr %" PRIx64 ", len: %d, gen: %d, rsvd: %d, "
214 "dtype: %d, ext1: %d, msscof: %d, hlen: %d, om: %d, "
215 "eop: %d, cq: %d, ext2: %d, ti: %d, tci: %d",
216 descr->addr, descr->len, descr->gen, descr->rsvd,
217 descr->dtype, descr->ext1, descr->msscof, descr->hlen, descr->om,
218 descr->eop, descr->cq, descr->ext2, descr->ti, descr->tci);
219}
220
221static inline void
222vmxnet3_dump_virt_hdr(struct virtio_net_hdr *vhdr)
223{
224 VMW_PKPRN("VHDR: flags 0x%x, gso_type: 0x%x, hdr_len: %d, gso_size: %d, "
225 "csum_start: %d, csum_offset: %d",
226 vhdr->flags, vhdr->gso_type, vhdr->hdr_len, vhdr->gso_size,
227 vhdr->csum_start, vhdr->csum_offset);
228}
229
230static inline void
231vmxnet3_dump_rx_descr(struct Vmxnet3_RxDesc *descr)
232{
233 VMW_PKPRN("RX DESCR: addr %" PRIx64 ", len: %d, gen: %d, rsvd: %d, "
234 "dtype: %d, ext1: %d, btype: %d",
235 descr->addr, descr->len, descr->gen,
236 descr->rsvd, descr->dtype, descr->ext1, descr->btype);
237}
238
239
240
241
242
243
244
245
246
247
248static bool _vmxnet3_assert_interrupt_line(VMXNET3State *s, uint32_t int_idx)
249{
250 PCIDevice *d = PCI_DEVICE(s);
251
252 if (s->msix_used && msix_enabled(d)) {
253 VMW_IRPRN("Sending MSI-X notification for vector %u", int_idx);
254 msix_notify(d, int_idx);
255 return false;
256 }
257 if (msi_enabled(d)) {
258 VMW_IRPRN("Sending MSI notification for vector %u", int_idx);
259 msi_notify(d, int_idx);
260 return false;
261 }
262
263 VMW_IRPRN("Asserting line for interrupt %u", int_idx);
264 pci_irq_assert(d);
265 return true;
266}
267
268static void _vmxnet3_deassert_interrupt_line(VMXNET3State *s, int lidx)
269{
270 PCIDevice *d = PCI_DEVICE(s);
271
272
273
274
275
276 assert(!s->msix_used || !msix_enabled(d));
277
278
279
280
281 assert(!msi_enabled(d));
282
283 VMW_IRPRN("Deasserting line for interrupt %u", lidx);
284 pci_irq_deassert(d);
285}
286
287static void vmxnet3_update_interrupt_line_state(VMXNET3State *s, int lidx)
288{
289 if (!s->interrupt_states[lidx].is_pending &&
290 s->interrupt_states[lidx].is_asserted) {
291 VMW_IRPRN("New interrupt line state for index %d is DOWN", lidx);
292 _vmxnet3_deassert_interrupt_line(s, lidx);
293 s->interrupt_states[lidx].is_asserted = false;
294 return;
295 }
296
297 if (s->interrupt_states[lidx].is_pending &&
298 !s->interrupt_states[lidx].is_masked &&
299 !s->interrupt_states[lidx].is_asserted) {
300 VMW_IRPRN("New interrupt line state for index %d is UP", lidx);
301 s->interrupt_states[lidx].is_asserted =
302 _vmxnet3_assert_interrupt_line(s, lidx);
303 s->interrupt_states[lidx].is_pending = false;
304 return;
305 }
306}
307
308static void vmxnet3_trigger_interrupt(VMXNET3State *s, int lidx)
309{
310 PCIDevice *d = PCI_DEVICE(s);
311 s->interrupt_states[lidx].is_pending = true;
312 vmxnet3_update_interrupt_line_state(s, lidx);
313
314 if (s->msix_used && msix_enabled(d) && s->auto_int_masking) {
315 goto do_automask;
316 }
317
318 if (msi_enabled(d) && s->auto_int_masking) {
319 goto do_automask;
320 }
321
322 return;
323
324do_automask:
325 s->interrupt_states[lidx].is_masked = true;
326 vmxnet3_update_interrupt_line_state(s, lidx);
327}
328
329static bool vmxnet3_interrupt_asserted(VMXNET3State *s, int lidx)
330{
331 return s->interrupt_states[lidx].is_asserted;
332}
333
334static void vmxnet3_clear_interrupt(VMXNET3State *s, int int_idx)
335{
336 s->interrupt_states[int_idx].is_pending = false;
337 if (s->auto_int_masking) {
338 s->interrupt_states[int_idx].is_masked = true;
339 }
340 vmxnet3_update_interrupt_line_state(s, int_idx);
341}
342
343static void
344vmxnet3_on_interrupt_mask_changed(VMXNET3State *s, int lidx, bool is_masked)
345{
346 s->interrupt_states[lidx].is_masked = is_masked;
347 vmxnet3_update_interrupt_line_state(s, lidx);
348}
349
350static bool vmxnet3_verify_driver_magic(PCIDevice *d, hwaddr dshmem)
351{
352 return (VMXNET3_READ_DRV_SHARED32(d, dshmem, magic) == VMXNET3_REV1_MAGIC);
353}
354
355#define VMXNET3_GET_BYTE(x, byte_num) (((x) >> (byte_num)*8) & 0xFF)
356#define VMXNET3_MAKE_BYTE(byte_num, val) \
357 (((uint32_t)((val) & 0xFF)) << (byte_num)*8)
358
359static void vmxnet3_set_variable_mac(VMXNET3State *s, uint32_t h, uint32_t l)
360{
361 s->conf.macaddr.a[0] = VMXNET3_GET_BYTE(l, 0);
362 s->conf.macaddr.a[1] = VMXNET3_GET_BYTE(l, 1);
363 s->conf.macaddr.a[2] = VMXNET3_GET_BYTE(l, 2);
364 s->conf.macaddr.a[3] = VMXNET3_GET_BYTE(l, 3);
365 s->conf.macaddr.a[4] = VMXNET3_GET_BYTE(h, 0);
366 s->conf.macaddr.a[5] = VMXNET3_GET_BYTE(h, 1);
367
368 VMW_CFPRN("Variable MAC: " MAC_FMT, MAC_ARG(s->conf.macaddr.a));
369
370 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
371}
372
373static uint64_t vmxnet3_get_mac_low(MACAddr *addr)
374{
375 return VMXNET3_MAKE_BYTE(0, addr->a[0]) |
376 VMXNET3_MAKE_BYTE(1, addr->a[1]) |
377 VMXNET3_MAKE_BYTE(2, addr->a[2]) |
378 VMXNET3_MAKE_BYTE(3, addr->a[3]);
379}
380
381static uint64_t vmxnet3_get_mac_high(MACAddr *addr)
382{
383 return VMXNET3_MAKE_BYTE(0, addr->a[4]) |
384 VMXNET3_MAKE_BYTE(1, addr->a[5]);
385}
386
387static void
388vmxnet3_inc_tx_consumption_counter(VMXNET3State *s, int qidx)
389{
390 vmxnet3_ring_inc(&s->txq_descr[qidx].tx_ring);
391}
392
393static inline void
394vmxnet3_inc_rx_consumption_counter(VMXNET3State *s, int qidx, int ridx)
395{
396 vmxnet3_ring_inc(&s->rxq_descr[qidx].rx_ring[ridx]);
397}
398
399static inline void
400vmxnet3_inc_tx_completion_counter(VMXNET3State *s, int qidx)
401{
402 vmxnet3_ring_inc(&s->txq_descr[qidx].comp_ring);
403}
404
405static void
406vmxnet3_inc_rx_completion_counter(VMXNET3State *s, int qidx)
407{
408 vmxnet3_ring_inc(&s->rxq_descr[qidx].comp_ring);
409}
410
411static void
412vmxnet3_dec_rx_completion_counter(VMXNET3State *s, int qidx)
413{
414 vmxnet3_ring_dec(&s->rxq_descr[qidx].comp_ring);
415}
416
417static void vmxnet3_complete_packet(VMXNET3State *s, int qidx, uint32_t tx_ridx)
418{
419 struct Vmxnet3_TxCompDesc txcq_descr;
420 PCIDevice *d = PCI_DEVICE(s);
421
422 VMXNET3_RING_DUMP(VMW_RIPRN, "TXC", qidx, &s->txq_descr[qidx].comp_ring);
423
424 memset(&txcq_descr, 0, sizeof(txcq_descr));
425 txcq_descr.txdIdx = tx_ridx;
426 txcq_descr.gen = vmxnet3_ring_curr_gen(&s->txq_descr[qidx].comp_ring);
427 txcq_descr.val1 = cpu_to_le32(txcq_descr.val1);
428 txcq_descr.val2 = cpu_to_le32(txcq_descr.val2);
429 vmxnet3_ring_write_curr_cell(d, &s->txq_descr[qidx].comp_ring, &txcq_descr);
430
431
432 smp_wmb();
433
434 vmxnet3_inc_tx_completion_counter(s, qidx);
435 vmxnet3_trigger_interrupt(s, s->txq_descr[qidx].intr_idx);
436}
437
438static bool
439vmxnet3_setup_tx_offloads(VMXNET3State *s)
440{
441 switch (s->offload_mode) {
442 case VMXNET3_OM_NONE:
443 net_tx_pkt_build_vheader(s->tx_pkt, false, false, 0);
444 break;
445
446 case VMXNET3_OM_CSUM:
447 net_tx_pkt_build_vheader(s->tx_pkt, false, true, 0);
448 VMW_PKPRN("L4 CSO requested\n");
449 break;
450
451 case VMXNET3_OM_TSO:
452 net_tx_pkt_build_vheader(s->tx_pkt, true, true,
453 s->cso_or_gso_size);
454 net_tx_pkt_update_ip_checksums(s->tx_pkt);
455 VMW_PKPRN("GSO offload requested.");
456 break;
457
458 default:
459 g_assert_not_reached();
460 return false;
461 }
462
463 return true;
464}
465
466static void
467vmxnet3_tx_retrieve_metadata(VMXNET3State *s,
468 const struct Vmxnet3_TxDesc *txd)
469{
470 s->offload_mode = txd->om;
471 s->cso_or_gso_size = txd->msscof;
472 s->tci = txd->tci;
473 s->needs_vlan = txd->ti;
474}
475
476typedef enum {
477 VMXNET3_PKT_STATUS_OK,
478 VMXNET3_PKT_STATUS_ERROR,
479 VMXNET3_PKT_STATUS_DISCARD,
480 VMXNET3_PKT_STATUS_OUT_OF_BUF
481} Vmxnet3PktStatus;
482
483static void
484vmxnet3_on_tx_done_update_stats(VMXNET3State *s, int qidx,
485 Vmxnet3PktStatus status)
486{
487 size_t tot_len = net_tx_pkt_get_total_len(s->tx_pkt);
488 struct UPT1_TxStats *stats = &s->txq_descr[qidx].txq_stats;
489
490 switch (status) {
491 case VMXNET3_PKT_STATUS_OK:
492 switch (net_tx_pkt_get_packet_type(s->tx_pkt)) {
493 case ETH_PKT_BCAST:
494 stats->bcastPktsTxOK++;
495 stats->bcastBytesTxOK += tot_len;
496 break;
497 case ETH_PKT_MCAST:
498 stats->mcastPktsTxOK++;
499 stats->mcastBytesTxOK += tot_len;
500 break;
501 case ETH_PKT_UCAST:
502 stats->ucastPktsTxOK++;
503 stats->ucastBytesTxOK += tot_len;
504 break;
505 default:
506 g_assert_not_reached();
507 }
508
509 if (s->offload_mode == VMXNET3_OM_TSO) {
510
511
512
513
514
515
516 stats->TSOPktsTxOK++;
517 stats->TSOBytesTxOK += tot_len;
518 }
519 break;
520
521 case VMXNET3_PKT_STATUS_DISCARD:
522 stats->pktsTxDiscard++;
523 break;
524
525 case VMXNET3_PKT_STATUS_ERROR:
526 stats->pktsTxError++;
527 break;
528
529 default:
530 g_assert_not_reached();
531 }
532}
533
534static void
535vmxnet3_on_rx_done_update_stats(VMXNET3State *s,
536 int qidx,
537 Vmxnet3PktStatus status)
538{
539 struct UPT1_RxStats *stats = &s->rxq_descr[qidx].rxq_stats;
540 size_t tot_len = net_rx_pkt_get_total_len(s->rx_pkt);
541
542 switch (status) {
543 case VMXNET3_PKT_STATUS_OUT_OF_BUF:
544 stats->pktsRxOutOfBuf++;
545 break;
546
547 case VMXNET3_PKT_STATUS_ERROR:
548 stats->pktsRxError++;
549 break;
550 case VMXNET3_PKT_STATUS_OK:
551 switch (net_rx_pkt_get_packet_type(s->rx_pkt)) {
552 case ETH_PKT_BCAST:
553 stats->bcastPktsRxOK++;
554 stats->bcastBytesRxOK += tot_len;
555 break;
556 case ETH_PKT_MCAST:
557 stats->mcastPktsRxOK++;
558 stats->mcastBytesRxOK += tot_len;
559 break;
560 case ETH_PKT_UCAST:
561 stats->ucastPktsRxOK++;
562 stats->ucastBytesRxOK += tot_len;
563 break;
564 default:
565 g_assert_not_reached();
566 }
567
568 if (tot_len > s->mtu) {
569 stats->LROPktsRxOK++;
570 stats->LROBytesRxOK += tot_len;
571 }
572 break;
573 default:
574 g_assert_not_reached();
575 }
576}
577
578static inline void
579vmxnet3_ring_read_curr_txdesc(PCIDevice *pcidev, Vmxnet3Ring *ring,
580 struct Vmxnet3_TxDesc *txd)
581{
582 vmxnet3_ring_read_curr_cell(pcidev, ring, txd);
583 txd->addr = le64_to_cpu(txd->addr);
584 txd->val1 = le32_to_cpu(txd->val1);
585 txd->val2 = le32_to_cpu(txd->val2);
586}
587
588static inline bool
589vmxnet3_pop_next_tx_descr(VMXNET3State *s,
590 int qidx,
591 struct Vmxnet3_TxDesc *txd,
592 uint32_t *descr_idx)
593{
594 Vmxnet3Ring *ring = &s->txq_descr[qidx].tx_ring;
595 PCIDevice *d = PCI_DEVICE(s);
596
597 vmxnet3_ring_read_curr_txdesc(d, ring, txd);
598 if (txd->gen == vmxnet3_ring_curr_gen(ring)) {
599
600 smp_rmb();
601
602 vmxnet3_ring_read_curr_txdesc(d, ring, txd);
603 VMXNET3_RING_DUMP(VMW_RIPRN, "TX", qidx, ring);
604 *descr_idx = vmxnet3_ring_curr_cell_idx(ring);
605 vmxnet3_inc_tx_consumption_counter(s, qidx);
606 return true;
607 }
608
609 return false;
610}
611
612static bool
613vmxnet3_send_packet(VMXNET3State *s, uint32_t qidx)
614{
615 Vmxnet3PktStatus status = VMXNET3_PKT_STATUS_OK;
616
617 if (!vmxnet3_setup_tx_offloads(s)) {
618 status = VMXNET3_PKT_STATUS_ERROR;
619 goto func_exit;
620 }
621
622
623 vmxnet3_dump_virt_hdr(net_tx_pkt_get_vhdr(s->tx_pkt));
624 net_tx_pkt_dump(s->tx_pkt);
625
626 if (!net_tx_pkt_send(s->tx_pkt, qemu_get_queue(s->nic))) {
627 status = VMXNET3_PKT_STATUS_DISCARD;
628 goto func_exit;
629 }
630
631func_exit:
632 vmxnet3_on_tx_done_update_stats(s, qidx, status);
633 return (status == VMXNET3_PKT_STATUS_OK);
634}
635
636static void vmxnet3_process_tx_queue(VMXNET3State *s, int qidx)
637{
638 struct Vmxnet3_TxDesc txd;
639 uint32_t txd_idx;
640 uint32_t data_len;
641 hwaddr data_pa;
642
643 for (;;) {
644 if (!vmxnet3_pop_next_tx_descr(s, qidx, &txd, &txd_idx)) {
645 break;
646 }
647
648 vmxnet3_dump_tx_descr(&txd);
649
650 if (!s->skip_current_tx_pkt) {
651 data_len = (txd.len > 0) ? txd.len : VMXNET3_MAX_TX_BUF_SIZE;
652 data_pa = txd.addr;
653
654 if (!net_tx_pkt_add_raw_fragment(s->tx_pkt,
655 data_pa,
656 data_len)) {
657 s->skip_current_tx_pkt = true;
658 }
659 }
660
661 if (s->tx_sop) {
662 vmxnet3_tx_retrieve_metadata(s, &txd);
663 s->tx_sop = false;
664 }
665
666 if (txd.eop) {
667 if (!s->skip_current_tx_pkt && net_tx_pkt_parse(s->tx_pkt)) {
668 if (s->needs_vlan) {
669 net_tx_pkt_setup_vlan_header(s->tx_pkt, s->tci);
670 }
671
672 vmxnet3_send_packet(s, qidx);
673 } else {
674 vmxnet3_on_tx_done_update_stats(s, qidx,
675 VMXNET3_PKT_STATUS_ERROR);
676 }
677
678 vmxnet3_complete_packet(s, qidx, txd_idx);
679 s->tx_sop = true;
680 s->skip_current_tx_pkt = false;
681 net_tx_pkt_reset(s->tx_pkt);
682 }
683 }
684}
685
686static inline void
687vmxnet3_read_next_rx_descr(VMXNET3State *s, int qidx, int ridx,
688 struct Vmxnet3_RxDesc *dbuf, uint32_t *didx)
689{
690 PCIDevice *d = PCI_DEVICE(s);
691
692 Vmxnet3Ring *ring = &s->rxq_descr[qidx].rx_ring[ridx];
693 *didx = vmxnet3_ring_curr_cell_idx(ring);
694 vmxnet3_ring_read_curr_cell(d, ring, dbuf);
695 dbuf->addr = le64_to_cpu(dbuf->addr);
696 dbuf->val1 = le32_to_cpu(dbuf->val1);
697 dbuf->ext1 = le32_to_cpu(dbuf->ext1);
698}
699
700static inline uint8_t
701vmxnet3_get_rx_ring_gen(VMXNET3State *s, int qidx, int ridx)
702{
703 return s->rxq_descr[qidx].rx_ring[ridx].gen;
704}
705
706static inline hwaddr
707vmxnet3_pop_rxc_descr(VMXNET3State *s, int qidx, uint32_t *descr_gen)
708{
709 uint8_t ring_gen;
710 struct Vmxnet3_RxCompDesc rxcd;
711
712 hwaddr daddr =
713 vmxnet3_ring_curr_cell_pa(&s->rxq_descr[qidx].comp_ring);
714
715 pci_dma_read(PCI_DEVICE(s),
716 daddr, &rxcd, sizeof(struct Vmxnet3_RxCompDesc));
717 rxcd.val1 = le32_to_cpu(rxcd.val1);
718 rxcd.val2 = le32_to_cpu(rxcd.val2);
719 rxcd.val3 = le32_to_cpu(rxcd.val3);
720 ring_gen = vmxnet3_ring_curr_gen(&s->rxq_descr[qidx].comp_ring);
721
722 if (rxcd.gen != ring_gen) {
723 *descr_gen = ring_gen;
724 vmxnet3_inc_rx_completion_counter(s, qidx);
725 return daddr;
726 }
727
728 return 0;
729}
730
731static inline void
732vmxnet3_revert_rxc_descr(VMXNET3State *s, int qidx)
733{
734 vmxnet3_dec_rx_completion_counter(s, qidx);
735}
736
737#define RXQ_IDX (0)
738#define RX_HEAD_BODY_RING (0)
739#define RX_BODY_ONLY_RING (1)
740
741static bool
742vmxnet3_get_next_head_rx_descr(VMXNET3State *s,
743 struct Vmxnet3_RxDesc *descr_buf,
744 uint32_t *descr_idx,
745 uint32_t *ridx)
746{
747 for (;;) {
748 uint32_t ring_gen;
749 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_HEAD_BODY_RING,
750 descr_buf, descr_idx);
751
752
753 ring_gen = vmxnet3_get_rx_ring_gen(s, RXQ_IDX, RX_HEAD_BODY_RING);
754 if (descr_buf->gen != ring_gen) {
755 return false;
756 }
757
758
759 smp_rmb();
760
761 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_HEAD_BODY_RING,
762 descr_buf, descr_idx);
763
764
765 vmxnet3_inc_rx_consumption_counter(s, RXQ_IDX, RX_HEAD_BODY_RING);
766
767
768 if (descr_buf->btype == VMXNET3_RXD_BTYPE_HEAD) {
769 *ridx = RX_HEAD_BODY_RING;
770 return true;
771 }
772 }
773}
774
775static bool
776vmxnet3_get_next_body_rx_descr(VMXNET3State *s,
777 struct Vmxnet3_RxDesc *d,
778 uint32_t *didx,
779 uint32_t *ridx)
780{
781 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_HEAD_BODY_RING, d, didx);
782
783
784 if (d->gen == vmxnet3_get_rx_ring_gen(s, RXQ_IDX, RX_HEAD_BODY_RING)) {
785
786 smp_rmb();
787
788 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_HEAD_BODY_RING, d, didx);
789 if (d->btype == VMXNET3_RXD_BTYPE_BODY) {
790 vmxnet3_inc_rx_consumption_counter(s, RXQ_IDX, RX_HEAD_BODY_RING);
791 *ridx = RX_HEAD_BODY_RING;
792 return true;
793 }
794 }
795
796
797
798
799
800 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_BODY_ONLY_RING, d, didx);
801
802
803 if (d->gen == vmxnet3_get_rx_ring_gen(s, RXQ_IDX, RX_BODY_ONLY_RING)) {
804
805 smp_rmb();
806
807 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_BODY_ONLY_RING, d, didx);
808 assert(d->btype == VMXNET3_RXD_BTYPE_BODY);
809 *ridx = RX_BODY_ONLY_RING;
810 vmxnet3_inc_rx_consumption_counter(s, RXQ_IDX, RX_BODY_ONLY_RING);
811 return true;
812 }
813
814 return false;
815}
816
817static inline bool
818vmxnet3_get_next_rx_descr(VMXNET3State *s, bool is_head,
819 struct Vmxnet3_RxDesc *descr_buf,
820 uint32_t *descr_idx,
821 uint32_t *ridx)
822{
823 if (is_head || !s->rx_packets_compound) {
824 return vmxnet3_get_next_head_rx_descr(s, descr_buf, descr_idx, ridx);
825 } else {
826 return vmxnet3_get_next_body_rx_descr(s, descr_buf, descr_idx, ridx);
827 }
828}
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845static void vmxnet3_rx_need_csum_calculate(struct NetRxPkt *pkt,
846 const void *pkt_data,
847 size_t pkt_len)
848{
849 struct virtio_net_hdr *vhdr;
850 bool isip4, isip6, istcp, isudp;
851 uint8_t *data;
852 int len;
853
854 if (!net_rx_pkt_has_virt_hdr(pkt)) {
855 return;
856 }
857
858 vhdr = net_rx_pkt_get_vhdr(pkt);
859 if (!VMXNET_FLAG_IS_SET(vhdr->flags, VIRTIO_NET_HDR_F_NEEDS_CSUM)) {
860 return;
861 }
862
863 net_rx_pkt_get_protocols(pkt, &isip4, &isip6, &isudp, &istcp);
864 if (!(isip4 || isip6) || !(istcp || isudp)) {
865 return;
866 }
867
868 vmxnet3_dump_virt_hdr(vhdr);
869
870
871 if (pkt_len < (vhdr->csum_start + vhdr->csum_offset + 2)) {
872 VMW_PKPRN("packet len:%zu < csum_start(%d) + csum_offset(%d) + 2, "
873 "cannot calculate checksum",
874 pkt_len, vhdr->csum_start, vhdr->csum_offset);
875 return;
876 }
877
878 data = (uint8_t *)pkt_data + vhdr->csum_start;
879 len = pkt_len - vhdr->csum_start;
880
881 stw_be_p(data + vhdr->csum_offset,
882 net_checksum_finish_nozero(net_checksum_add(len, data)));
883
884 vhdr->flags &= ~VIRTIO_NET_HDR_F_NEEDS_CSUM;
885 vhdr->flags |= VIRTIO_NET_HDR_F_DATA_VALID;
886}
887
888static void vmxnet3_rx_update_descr(struct NetRxPkt *pkt,
889 struct Vmxnet3_RxCompDesc *rxcd)
890{
891 int csum_ok, is_gso;
892 bool isip4, isip6, istcp, isudp;
893 struct virtio_net_hdr *vhdr;
894 uint8_t offload_type;
895
896 if (net_rx_pkt_is_vlan_stripped(pkt)) {
897 rxcd->ts = 1;
898 rxcd->tci = net_rx_pkt_get_vlan_tag(pkt);
899 }
900
901 if (!net_rx_pkt_has_virt_hdr(pkt)) {
902 goto nocsum;
903 }
904
905 vhdr = net_rx_pkt_get_vhdr(pkt);
906
907
908
909
910
911
912 csum_ok = VMXNET_FLAG_IS_SET(vhdr->flags, VIRTIO_NET_HDR_F_DATA_VALID) ||
913 VMXNET_FLAG_IS_SET(vhdr->flags, VIRTIO_NET_HDR_F_NEEDS_CSUM);
914
915 offload_type = vhdr->gso_type & ~VIRTIO_NET_HDR_GSO_ECN;
916 is_gso = (offload_type != VIRTIO_NET_HDR_GSO_NONE) ? 1 : 0;
917
918 if (!csum_ok && !is_gso) {
919 goto nocsum;
920 }
921
922 net_rx_pkt_get_protocols(pkt, &isip4, &isip6, &isudp, &istcp);
923 if ((!istcp && !isudp) || (!isip4 && !isip6)) {
924 goto nocsum;
925 }
926
927 rxcd->cnc = 0;
928 rxcd->v4 = isip4 ? 1 : 0;
929 rxcd->v6 = isip6 ? 1 : 0;
930 rxcd->tcp = istcp ? 1 : 0;
931 rxcd->udp = isudp ? 1 : 0;
932 rxcd->fcs = rxcd->tuc = rxcd->ipc = 1;
933 return;
934
935nocsum:
936 rxcd->cnc = 1;
937 return;
938}
939
940static void
941vmxnet3_pci_dma_writev(PCIDevice *pci_dev,
942 const struct iovec *iov,
943 size_t start_iov_off,
944 hwaddr target_addr,
945 size_t bytes_to_copy)
946{
947 size_t curr_off = 0;
948 size_t copied = 0;
949
950 while (bytes_to_copy) {
951 if (start_iov_off < (curr_off + iov->iov_len)) {
952 size_t chunk_len =
953 MIN((curr_off + iov->iov_len) - start_iov_off, bytes_to_copy);
954
955 pci_dma_write(pci_dev, target_addr + copied,
956 iov->iov_base + start_iov_off - curr_off,
957 chunk_len);
958
959 copied += chunk_len;
960 start_iov_off += chunk_len;
961 curr_off = start_iov_off;
962 bytes_to_copy -= chunk_len;
963 } else {
964 curr_off += iov->iov_len;
965 }
966 iov++;
967 }
968}
969
970static void
971vmxnet3_pci_dma_write_rxcd(PCIDevice *pcidev, dma_addr_t pa,
972 struct Vmxnet3_RxCompDesc *rxcd)
973{
974 rxcd->val1 = cpu_to_le32(rxcd->val1);
975 rxcd->val2 = cpu_to_le32(rxcd->val2);
976 rxcd->val3 = cpu_to_le32(rxcd->val3);
977 pci_dma_write(pcidev, pa, rxcd, sizeof(*rxcd));
978}
979
980static bool
981vmxnet3_indicate_packet(VMXNET3State *s)
982{
983 struct Vmxnet3_RxDesc rxd;
984 PCIDevice *d = PCI_DEVICE(s);
985 bool is_head = true;
986 uint32_t rxd_idx;
987 uint32_t rx_ridx = 0;
988
989 struct Vmxnet3_RxCompDesc rxcd;
990 uint32_t new_rxcd_gen = VMXNET3_INIT_GEN;
991 hwaddr new_rxcd_pa = 0;
992 hwaddr ready_rxcd_pa = 0;
993 struct iovec *data = net_rx_pkt_get_iovec(s->rx_pkt);
994 size_t bytes_copied = 0;
995 size_t bytes_left = net_rx_pkt_get_total_len(s->rx_pkt);
996 uint16_t num_frags = 0;
997 size_t chunk_size;
998
999 net_rx_pkt_dump(s->rx_pkt);
1000
1001 while (bytes_left > 0) {
1002
1003
1004 if (num_frags == s->max_rx_frags) {
1005 break;
1006 }
1007
1008 new_rxcd_pa = vmxnet3_pop_rxc_descr(s, RXQ_IDX, &new_rxcd_gen);
1009 if (!new_rxcd_pa) {
1010 break;
1011 }
1012
1013 if (!vmxnet3_get_next_rx_descr(s, is_head, &rxd, &rxd_idx, &rx_ridx)) {
1014 break;
1015 }
1016
1017 chunk_size = MIN(bytes_left, rxd.len);
1018 vmxnet3_pci_dma_writev(d, data, bytes_copied, rxd.addr, chunk_size);
1019 bytes_copied += chunk_size;
1020 bytes_left -= chunk_size;
1021
1022 vmxnet3_dump_rx_descr(&rxd);
1023
1024 if (ready_rxcd_pa != 0) {
1025 vmxnet3_pci_dma_write_rxcd(d, ready_rxcd_pa, &rxcd);
1026 }
1027
1028 memset(&rxcd, 0, sizeof(struct Vmxnet3_RxCompDesc));
1029 rxcd.rxdIdx = rxd_idx;
1030 rxcd.len = chunk_size;
1031 rxcd.sop = is_head;
1032 rxcd.gen = new_rxcd_gen;
1033 rxcd.rqID = RXQ_IDX + rx_ridx * s->rxq_num;
1034
1035 if (bytes_left == 0) {
1036 vmxnet3_rx_update_descr(s->rx_pkt, &rxcd);
1037 }
1038
1039 VMW_RIPRN("RX Completion descriptor: rxRing: %lu rxIdx %lu len %lu "
1040 "sop %d csum_correct %lu",
1041 (unsigned long) rx_ridx,
1042 (unsigned long) rxcd.rxdIdx,
1043 (unsigned long) rxcd.len,
1044 (int) rxcd.sop,
1045 (unsigned long) rxcd.tuc);
1046
1047 is_head = false;
1048 ready_rxcd_pa = new_rxcd_pa;
1049 new_rxcd_pa = 0;
1050 num_frags++;
1051 }
1052
1053 if (ready_rxcd_pa != 0) {
1054 rxcd.eop = 1;
1055 rxcd.err = (bytes_left != 0);
1056
1057 vmxnet3_pci_dma_write_rxcd(d, ready_rxcd_pa, &rxcd);
1058
1059
1060 smp_wmb();
1061 }
1062
1063 if (new_rxcd_pa != 0) {
1064 vmxnet3_revert_rxc_descr(s, RXQ_IDX);
1065 }
1066
1067 vmxnet3_trigger_interrupt(s, s->rxq_descr[RXQ_IDX].intr_idx);
1068
1069 if (bytes_left == 0) {
1070 vmxnet3_on_rx_done_update_stats(s, RXQ_IDX, VMXNET3_PKT_STATUS_OK);
1071 return true;
1072 } else if (num_frags == s->max_rx_frags) {
1073 vmxnet3_on_rx_done_update_stats(s, RXQ_IDX, VMXNET3_PKT_STATUS_ERROR);
1074 return false;
1075 } else {
1076 vmxnet3_on_rx_done_update_stats(s, RXQ_IDX,
1077 VMXNET3_PKT_STATUS_OUT_OF_BUF);
1078 return false;
1079 }
1080}
1081
1082static void
1083vmxnet3_io_bar0_write(void *opaque, hwaddr addr,
1084 uint64_t val, unsigned size)
1085{
1086 VMXNET3State *s = opaque;
1087
1088 if (!s->device_active) {
1089 return;
1090 }
1091
1092 if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_TXPROD,
1093 VMXNET3_DEVICE_MAX_TX_QUEUES, VMXNET3_REG_ALIGN)) {
1094 int tx_queue_idx =
1095 VMW_MULTIREG_IDX_BY_ADDR(addr, VMXNET3_REG_TXPROD,
1096 VMXNET3_REG_ALIGN);
1097 if (tx_queue_idx <= s->txq_num) {
1098 vmxnet3_process_tx_queue(s, tx_queue_idx);
1099 } else {
1100 qemu_log_mask(LOG_GUEST_ERROR, "vmxnet3: Illegal TX queue %d/%d\n",
1101 tx_queue_idx, s->txq_num);
1102 }
1103 return;
1104 }
1105
1106 if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_IMR,
1107 VMXNET3_MAX_INTRS, VMXNET3_REG_ALIGN)) {
1108 int l = VMW_MULTIREG_IDX_BY_ADDR(addr, VMXNET3_REG_IMR,
1109 VMXNET3_REG_ALIGN);
1110
1111 VMW_CBPRN("Interrupt mask for line %d written: 0x%" PRIx64, l, val);
1112
1113 vmxnet3_on_interrupt_mask_changed(s, l, val);
1114 return;
1115 }
1116
1117 if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_RXPROD,
1118 VMXNET3_DEVICE_MAX_RX_QUEUES, VMXNET3_REG_ALIGN) ||
1119 VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_RXPROD2,
1120 VMXNET3_DEVICE_MAX_RX_QUEUES, VMXNET3_REG_ALIGN)) {
1121 return;
1122 }
1123
1124 VMW_WRPRN("BAR0 unknown write [%" PRIx64 "] = %" PRIx64 ", size %d",
1125 (uint64_t) addr, val, size);
1126}
1127
1128static uint64_t
1129vmxnet3_io_bar0_read(void *opaque, hwaddr addr, unsigned size)
1130{
1131 VMXNET3State *s = opaque;
1132
1133 if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_IMR,
1134 VMXNET3_MAX_INTRS, VMXNET3_REG_ALIGN)) {
1135 int l = VMW_MULTIREG_IDX_BY_ADDR(addr, VMXNET3_REG_IMR,
1136 VMXNET3_REG_ALIGN);
1137 return s->interrupt_states[l].is_masked;
1138 }
1139
1140 VMW_CBPRN("BAR0 unknown read [%" PRIx64 "], size %d", addr, size);
1141 return 0;
1142}
1143
1144static void vmxnet3_reset_interrupt_states(VMXNET3State *s)
1145{
1146 int i;
1147 for (i = 0; i < ARRAY_SIZE(s->interrupt_states); i++) {
1148 s->interrupt_states[i].is_asserted = false;
1149 s->interrupt_states[i].is_pending = false;
1150 s->interrupt_states[i].is_masked = true;
1151 }
1152}
1153
1154static void vmxnet3_reset_mac(VMXNET3State *s)
1155{
1156 memcpy(&s->conf.macaddr.a, &s->perm_mac.a, sizeof(s->perm_mac.a));
1157 VMW_CFPRN("MAC address set to: " MAC_FMT, MAC_ARG(s->conf.macaddr.a));
1158}
1159
1160static void vmxnet3_deactivate_device(VMXNET3State *s)
1161{
1162 if (s->device_active) {
1163 VMW_CBPRN("Deactivating vmxnet3...");
1164 net_tx_pkt_reset(s->tx_pkt);
1165 net_tx_pkt_uninit(s->tx_pkt);
1166 net_rx_pkt_uninit(s->rx_pkt);
1167 s->device_active = false;
1168 }
1169}
1170
1171static void vmxnet3_reset(VMXNET3State *s)
1172{
1173 VMW_CBPRN("Resetting vmxnet3...");
1174
1175 vmxnet3_deactivate_device(s);
1176 vmxnet3_reset_interrupt_states(s);
1177 s->drv_shmem = 0;
1178 s->tx_sop = true;
1179 s->skip_current_tx_pkt = false;
1180}
1181
1182static void vmxnet3_update_rx_mode(VMXNET3State *s)
1183{
1184 PCIDevice *d = PCI_DEVICE(s);
1185
1186 s->rx_mode = VMXNET3_READ_DRV_SHARED32(d, s->drv_shmem,
1187 devRead.rxFilterConf.rxMode);
1188 VMW_CFPRN("RX mode: 0x%08X", s->rx_mode);
1189}
1190
1191static void vmxnet3_update_vlan_filters(VMXNET3State *s)
1192{
1193 int i;
1194 PCIDevice *d = PCI_DEVICE(s);
1195
1196
1197 VMXNET3_READ_DRV_SHARED(d, s->drv_shmem,
1198 devRead.rxFilterConf.vfTable,
1199 s->vlan_table,
1200 sizeof(s->vlan_table));
1201
1202
1203 for (i = 0; i < ARRAY_SIZE(s->vlan_table); i++) {
1204 s->vlan_table[i] = le32_to_cpu(s->vlan_table[i]);
1205 }
1206
1207
1208 VMW_CFPRN("Configured VLANs:");
1209 for (i = 0; i < sizeof(s->vlan_table) * 8; i++) {
1210 if (VMXNET3_VFTABLE_ENTRY_IS_SET(s->vlan_table, i)) {
1211 VMW_CFPRN("\tVLAN %d is present", i);
1212 }
1213 }
1214}
1215
1216static void vmxnet3_update_mcast_filters(VMXNET3State *s)
1217{
1218 PCIDevice *d = PCI_DEVICE(s);
1219
1220 uint16_t list_bytes =
1221 VMXNET3_READ_DRV_SHARED16(d, s->drv_shmem,
1222 devRead.rxFilterConf.mfTableLen);
1223
1224 s->mcast_list_len = list_bytes / sizeof(s->mcast_list[0]);
1225
1226 s->mcast_list = g_realloc(s->mcast_list, list_bytes);
1227 if (!s->mcast_list) {
1228 if (s->mcast_list_len == 0) {
1229 VMW_CFPRN("Current multicast list is empty");
1230 } else {
1231 VMW_ERPRN("Failed to allocate multicast list of %d elements",
1232 s->mcast_list_len);
1233 }
1234 s->mcast_list_len = 0;
1235 } else {
1236 int i;
1237 hwaddr mcast_list_pa =
1238 VMXNET3_READ_DRV_SHARED64(d, s->drv_shmem,
1239 devRead.rxFilterConf.mfTablePA);
1240
1241 pci_dma_read(d, mcast_list_pa, s->mcast_list, list_bytes);
1242
1243 VMW_CFPRN("Current multicast list len is %d:", s->mcast_list_len);
1244 for (i = 0; i < s->mcast_list_len; i++) {
1245 VMW_CFPRN("\t" MAC_FMT, MAC_ARG(s->mcast_list[i].a));
1246 }
1247 }
1248}
1249
1250static void vmxnet3_setup_rx_filtering(VMXNET3State *s)
1251{
1252 vmxnet3_update_rx_mode(s);
1253 vmxnet3_update_vlan_filters(s);
1254 vmxnet3_update_mcast_filters(s);
1255}
1256
1257static uint32_t vmxnet3_get_interrupt_config(VMXNET3State *s)
1258{
1259 uint32_t interrupt_mode = VMXNET3_IT_AUTO | (VMXNET3_IMM_AUTO << 2);
1260 VMW_CFPRN("Interrupt config is 0x%X", interrupt_mode);
1261 return interrupt_mode;
1262}
1263
1264static void vmxnet3_fill_stats(VMXNET3State *s)
1265{
1266 int i;
1267 PCIDevice *d = PCI_DEVICE(s);
1268
1269 if (!s->device_active)
1270 return;
1271
1272 for (i = 0; i < s->txq_num; i++) {
1273 pci_dma_write(d,
1274 s->txq_descr[i].tx_stats_pa,
1275 &s->txq_descr[i].txq_stats,
1276 sizeof(s->txq_descr[i].txq_stats));
1277 }
1278
1279 for (i = 0; i < s->rxq_num; i++) {
1280 pci_dma_write(d,
1281 s->rxq_descr[i].rx_stats_pa,
1282 &s->rxq_descr[i].rxq_stats,
1283 sizeof(s->rxq_descr[i].rxq_stats));
1284 }
1285}
1286
1287static void vmxnet3_adjust_by_guest_type(VMXNET3State *s)
1288{
1289 struct Vmxnet3_GOSInfo gos;
1290 PCIDevice *d = PCI_DEVICE(s);
1291
1292 VMXNET3_READ_DRV_SHARED(d, s->drv_shmem, devRead.misc.driverInfo.gos,
1293 &gos, sizeof(gos));
1294 s->rx_packets_compound =
1295 (gos.gosType == VMXNET3_GOS_TYPE_WIN) ? false : true;
1296
1297 VMW_CFPRN("Guest type specifics: RXCOMPOUND: %d", s->rx_packets_compound);
1298}
1299
1300static void
1301vmxnet3_dump_conf_descr(const char *name,
1302 struct Vmxnet3_VariableLenConfDesc *pm_descr)
1303{
1304 VMW_CFPRN("%s descriptor dump: Version %u, Length %u",
1305 name, pm_descr->confVer, pm_descr->confLen);
1306
1307};
1308
1309static void vmxnet3_update_pm_state(VMXNET3State *s)
1310{
1311 struct Vmxnet3_VariableLenConfDesc pm_descr;
1312 PCIDevice *d = PCI_DEVICE(s);
1313
1314 pm_descr.confLen =
1315 VMXNET3_READ_DRV_SHARED32(d, s->drv_shmem, devRead.pmConfDesc.confLen);
1316 pm_descr.confVer =
1317 VMXNET3_READ_DRV_SHARED32(d, s->drv_shmem, devRead.pmConfDesc.confVer);
1318 pm_descr.confPA =
1319 VMXNET3_READ_DRV_SHARED64(d, s->drv_shmem, devRead.pmConfDesc.confPA);
1320
1321 vmxnet3_dump_conf_descr("PM State", &pm_descr);
1322}
1323
1324static void vmxnet3_update_features(VMXNET3State *s)
1325{
1326 uint32_t guest_features;
1327 int rxcso_supported;
1328 PCIDevice *d = PCI_DEVICE(s);
1329
1330 guest_features = VMXNET3_READ_DRV_SHARED32(d, s->drv_shmem,
1331 devRead.misc.uptFeatures);
1332
1333 rxcso_supported = VMXNET_FLAG_IS_SET(guest_features, UPT1_F_RXCSUM);
1334 s->rx_vlan_stripping = VMXNET_FLAG_IS_SET(guest_features, UPT1_F_RXVLAN);
1335 s->lro_supported = VMXNET_FLAG_IS_SET(guest_features, UPT1_F_LRO);
1336
1337 VMW_CFPRN("Features configuration: LRO: %d, RXCSUM: %d, VLANSTRIP: %d",
1338 s->lro_supported, rxcso_supported,
1339 s->rx_vlan_stripping);
1340 if (s->peer_has_vhdr) {
1341 qemu_set_offload(qemu_get_queue(s->nic)->peer,
1342 rxcso_supported,
1343 s->lro_supported,
1344 s->lro_supported,
1345 0,
1346 0);
1347 }
1348}
1349
1350static bool vmxnet3_verify_intx(VMXNET3State *s, int intx)
1351{
1352 return s->msix_used || msi_enabled(PCI_DEVICE(s))
1353 || intx == pci_get_byte(s->parent_obj.config + PCI_INTERRUPT_PIN) - 1;
1354}
1355
1356static void vmxnet3_validate_interrupt_idx(bool is_msix, int idx)
1357{
1358 int max_ints = is_msix ? VMXNET3_MAX_INTRS : VMXNET3_MAX_NMSIX_INTRS;
1359 if (idx >= max_ints) {
1360 hw_error("Bad interrupt index: %d\n", idx);
1361 }
1362}
1363
1364static void vmxnet3_validate_interrupts(VMXNET3State *s)
1365{
1366 int i;
1367
1368 VMW_CFPRN("Verifying event interrupt index (%d)", s->event_int_idx);
1369 vmxnet3_validate_interrupt_idx(s->msix_used, s->event_int_idx);
1370
1371 for (i = 0; i < s->txq_num; i++) {
1372 int idx = s->txq_descr[i].intr_idx;
1373 VMW_CFPRN("Verifying TX queue %d interrupt index (%d)", i, idx);
1374 vmxnet3_validate_interrupt_idx(s->msix_used, idx);
1375 }
1376
1377 for (i = 0; i < s->rxq_num; i++) {
1378 int idx = s->rxq_descr[i].intr_idx;
1379 VMW_CFPRN("Verifying RX queue %d interrupt index (%d)", i, idx);
1380 vmxnet3_validate_interrupt_idx(s->msix_used, idx);
1381 }
1382}
1383
1384static bool vmxnet3_validate_queues(VMXNET3State *s)
1385{
1386
1387
1388
1389
1390
1391
1392 if (s->txq_num > VMXNET3_DEVICE_MAX_TX_QUEUES) {
1393 qemu_log_mask(LOG_GUEST_ERROR, "vmxnet3: Bad TX queues number: %d\n",
1394 s->txq_num);
1395 return false;
1396 }
1397
1398 if (s->rxq_num > VMXNET3_DEVICE_MAX_RX_QUEUES) {
1399 qemu_log_mask(LOG_GUEST_ERROR, "vmxnet3: Bad RX queues number: %d\n",
1400 s->rxq_num);
1401 return false;
1402 }
1403
1404 return true;
1405}
1406
1407static void vmxnet3_activate_device(VMXNET3State *s)
1408{
1409 int i;
1410 static const uint32_t VMXNET3_DEF_TX_THRESHOLD = 1;
1411 PCIDevice *d = PCI_DEVICE(s);
1412 hwaddr qdescr_table_pa;
1413 uint64_t pa;
1414 uint32_t size;
1415
1416
1417 if (!vmxnet3_verify_driver_magic(d, s->drv_shmem)) {
1418 VMW_ERPRN("Device configuration received from driver is invalid");
1419 return;
1420 }
1421
1422
1423 if (s->device_active) {
1424 VMW_CFPRN("Vmxnet3 device is active");
1425 return;
1426 }
1427
1428 s->txq_num =
1429 VMXNET3_READ_DRV_SHARED8(d, s->drv_shmem, devRead.misc.numTxQueues);
1430 s->rxq_num =
1431 VMXNET3_READ_DRV_SHARED8(d, s->drv_shmem, devRead.misc.numRxQueues);
1432
1433 VMW_CFPRN("Number of TX/RX queues %u/%u", s->txq_num, s->rxq_num);
1434 if (!vmxnet3_validate_queues(s)) {
1435 return;
1436 }
1437
1438 vmxnet3_adjust_by_guest_type(s);
1439 vmxnet3_update_features(s);
1440 vmxnet3_update_pm_state(s);
1441 vmxnet3_setup_rx_filtering(s);
1442
1443 s->mtu = VMXNET3_READ_DRV_SHARED32(d, s->drv_shmem, devRead.misc.mtu);
1444 assert(VMXNET3_MIN_MTU <= s->mtu && s->mtu < VMXNET3_MAX_MTU);
1445 VMW_CFPRN("MTU is %u", s->mtu);
1446
1447 s->max_rx_frags =
1448 VMXNET3_READ_DRV_SHARED16(d, s->drv_shmem, devRead.misc.maxNumRxSG);
1449
1450 if (s->max_rx_frags == 0) {
1451 s->max_rx_frags = 1;
1452 }
1453
1454 VMW_CFPRN("Max RX fragments is %u", s->max_rx_frags);
1455
1456 s->event_int_idx =
1457 VMXNET3_READ_DRV_SHARED8(d, s->drv_shmem, devRead.intrConf.eventIntrIdx);
1458 assert(vmxnet3_verify_intx(s, s->event_int_idx));
1459 VMW_CFPRN("Events interrupt line is %u", s->event_int_idx);
1460
1461 s->auto_int_masking =
1462 VMXNET3_READ_DRV_SHARED8(d, s->drv_shmem, devRead.intrConf.autoMask);
1463 VMW_CFPRN("Automatic interrupt masking is %d", (int)s->auto_int_masking);
1464
1465 qdescr_table_pa =
1466 VMXNET3_READ_DRV_SHARED64(d, s->drv_shmem, devRead.misc.queueDescPA);
1467 VMW_CFPRN("TX queues descriptors table is at 0x%" PRIx64, qdescr_table_pa);
1468
1469
1470
1471
1472
1473 s->max_tx_frags = 0;
1474
1475
1476 for (i = 0; i < s->txq_num; i++) {
1477 hwaddr qdescr_pa =
1478 qdescr_table_pa + i * sizeof(struct Vmxnet3_TxQueueDesc);
1479
1480
1481 s->txq_descr[i].intr_idx =
1482 VMXNET3_READ_TX_QUEUE_DESCR8(d, qdescr_pa, conf.intrIdx);
1483 assert(vmxnet3_verify_intx(s, s->txq_descr[i].intr_idx));
1484
1485 VMW_CFPRN("TX Queue %d interrupt: %d", i, s->txq_descr[i].intr_idx);
1486
1487
1488 pa = VMXNET3_READ_TX_QUEUE_DESCR64(d, qdescr_pa, conf.txRingBasePA);
1489 size = VMXNET3_READ_TX_QUEUE_DESCR32(d, qdescr_pa, conf.txRingSize);
1490 if (size > VMXNET3_TX_RING_MAX_SIZE) {
1491 size = VMXNET3_TX_RING_MAX_SIZE;
1492 }
1493
1494 vmxnet3_ring_init(d, &s->txq_descr[i].tx_ring, pa, size,
1495 sizeof(struct Vmxnet3_TxDesc), false);
1496 VMXNET3_RING_DUMP(VMW_CFPRN, "TX", i, &s->txq_descr[i].tx_ring);
1497
1498 s->max_tx_frags += size;
1499
1500
1501 pa = VMXNET3_READ_TX_QUEUE_DESCR64(d, qdescr_pa, conf.compRingBasePA);
1502 size = VMXNET3_READ_TX_QUEUE_DESCR32(d, qdescr_pa, conf.compRingSize);
1503 if (size > VMXNET3_TC_RING_MAX_SIZE) {
1504 size = VMXNET3_TC_RING_MAX_SIZE;
1505 }
1506 vmxnet3_ring_init(d, &s->txq_descr[i].comp_ring, pa, size,
1507 sizeof(struct Vmxnet3_TxCompDesc), true);
1508 VMXNET3_RING_DUMP(VMW_CFPRN, "TXC", i, &s->txq_descr[i].comp_ring);
1509
1510 s->txq_descr[i].tx_stats_pa =
1511 qdescr_pa + offsetof(struct Vmxnet3_TxQueueDesc, stats);
1512
1513 memset(&s->txq_descr[i].txq_stats, 0,
1514 sizeof(s->txq_descr[i].txq_stats));
1515
1516
1517 VMXNET3_WRITE_TX_QUEUE_DESCR32(d, qdescr_pa,
1518 ctrl.txThreshold,
1519 VMXNET3_DEF_TX_THRESHOLD);
1520 }
1521
1522
1523 VMW_CFPRN("Max TX fragments is %u", s->max_tx_frags);
1524 net_tx_pkt_init(&s->tx_pkt, PCI_DEVICE(s),
1525 s->max_tx_frags, s->peer_has_vhdr);
1526 net_rx_pkt_init(&s->rx_pkt, s->peer_has_vhdr);
1527
1528
1529 for (i = 0; i < s->rxq_num; i++) {
1530 int j;
1531 hwaddr qd_pa =
1532 qdescr_table_pa + s->txq_num * sizeof(struct Vmxnet3_TxQueueDesc) +
1533 i * sizeof(struct Vmxnet3_RxQueueDesc);
1534
1535
1536 s->rxq_descr[i].intr_idx =
1537 VMXNET3_READ_TX_QUEUE_DESCR8(d, qd_pa, conf.intrIdx);
1538 assert(vmxnet3_verify_intx(s, s->rxq_descr[i].intr_idx));
1539
1540 VMW_CFPRN("RX Queue %d interrupt: %d", i, s->rxq_descr[i].intr_idx);
1541
1542
1543 for (j = 0; j < VMXNET3_RX_RINGS_PER_QUEUE; j++) {
1544
1545 pa = VMXNET3_READ_RX_QUEUE_DESCR64(d, qd_pa, conf.rxRingBasePA[j]);
1546 size = VMXNET3_READ_RX_QUEUE_DESCR32(d, qd_pa, conf.rxRingSize[j]);
1547 if (size > VMXNET3_RX_RING_MAX_SIZE) {
1548 size = VMXNET3_RX_RING_MAX_SIZE;
1549 }
1550 vmxnet3_ring_init(d, &s->rxq_descr[i].rx_ring[j], pa, size,
1551 sizeof(struct Vmxnet3_RxDesc), false);
1552 VMW_CFPRN("RX queue %d:%d: Base: %" PRIx64 ", Size: %d",
1553 i, j, pa, size);
1554 }
1555
1556
1557 pa = VMXNET3_READ_RX_QUEUE_DESCR64(d, qd_pa, conf.compRingBasePA);
1558 size = VMXNET3_READ_RX_QUEUE_DESCR32(d, qd_pa, conf.compRingSize);
1559 if (size > VMXNET3_RC_RING_MAX_SIZE) {
1560 size = VMXNET3_RC_RING_MAX_SIZE;
1561 }
1562 vmxnet3_ring_init(d, &s->rxq_descr[i].comp_ring, pa, size,
1563 sizeof(struct Vmxnet3_RxCompDesc), true);
1564 VMW_CFPRN("RXC queue %d: Base: %" PRIx64 ", Size: %d", i, pa, size);
1565
1566 s->rxq_descr[i].rx_stats_pa =
1567 qd_pa + offsetof(struct Vmxnet3_RxQueueDesc, stats);
1568 memset(&s->rxq_descr[i].rxq_stats, 0,
1569 sizeof(s->rxq_descr[i].rxq_stats));
1570 }
1571
1572 vmxnet3_validate_interrupts(s);
1573
1574
1575 smp_wmb();
1576
1577 vmxnet3_reset_mac(s);
1578
1579 s->device_active = true;
1580}
1581
1582static void vmxnet3_handle_command(VMXNET3State *s, uint64_t cmd)
1583{
1584 s->last_command = cmd;
1585
1586 switch (cmd) {
1587 case VMXNET3_CMD_GET_PERM_MAC_HI:
1588 VMW_CBPRN("Set: Get upper part of permanent MAC");
1589 break;
1590
1591 case VMXNET3_CMD_GET_PERM_MAC_LO:
1592 VMW_CBPRN("Set: Get lower part of permanent MAC");
1593 break;
1594
1595 case VMXNET3_CMD_GET_STATS:
1596 VMW_CBPRN("Set: Get device statistics");
1597 vmxnet3_fill_stats(s);
1598 break;
1599
1600 case VMXNET3_CMD_ACTIVATE_DEV:
1601 VMW_CBPRN("Set: Activating vmxnet3 device");
1602 vmxnet3_activate_device(s);
1603 break;
1604
1605 case VMXNET3_CMD_UPDATE_RX_MODE:
1606 VMW_CBPRN("Set: Update rx mode");
1607 vmxnet3_update_rx_mode(s);
1608 break;
1609
1610 case VMXNET3_CMD_UPDATE_VLAN_FILTERS:
1611 VMW_CBPRN("Set: Update VLAN filters");
1612 vmxnet3_update_vlan_filters(s);
1613 break;
1614
1615 case VMXNET3_CMD_UPDATE_MAC_FILTERS:
1616 VMW_CBPRN("Set: Update MAC filters");
1617 vmxnet3_update_mcast_filters(s);
1618 break;
1619
1620 case VMXNET3_CMD_UPDATE_FEATURE:
1621 VMW_CBPRN("Set: Update features");
1622 vmxnet3_update_features(s);
1623 break;
1624
1625 case VMXNET3_CMD_UPDATE_PMCFG:
1626 VMW_CBPRN("Set: Update power management config");
1627 vmxnet3_update_pm_state(s);
1628 break;
1629
1630 case VMXNET3_CMD_GET_LINK:
1631 VMW_CBPRN("Set: Get link");
1632 break;
1633
1634 case VMXNET3_CMD_RESET_DEV:
1635 VMW_CBPRN("Set: Reset device");
1636 vmxnet3_reset(s);
1637 break;
1638
1639 case VMXNET3_CMD_QUIESCE_DEV:
1640 VMW_CBPRN("Set: VMXNET3_CMD_QUIESCE_DEV - deactivate the device");
1641 vmxnet3_deactivate_device(s);
1642 break;
1643
1644 case VMXNET3_CMD_GET_CONF_INTR:
1645 VMW_CBPRN("Set: VMXNET3_CMD_GET_CONF_INTR - interrupt configuration");
1646 break;
1647
1648 case VMXNET3_CMD_GET_ADAPTIVE_RING_INFO:
1649 VMW_CBPRN("Set: VMXNET3_CMD_GET_ADAPTIVE_RING_INFO - "
1650 "adaptive ring info flags");
1651 break;
1652
1653 case VMXNET3_CMD_GET_DID_LO:
1654 VMW_CBPRN("Set: Get lower part of device ID");
1655 break;
1656
1657 case VMXNET3_CMD_GET_DID_HI:
1658 VMW_CBPRN("Set: Get upper part of device ID");
1659 break;
1660
1661 case VMXNET3_CMD_GET_DEV_EXTRA_INFO:
1662 VMW_CBPRN("Set: Get device extra info");
1663 break;
1664
1665 default:
1666 VMW_CBPRN("Received unknown command: %" PRIx64, cmd);
1667 break;
1668 }
1669}
1670
1671static uint64_t vmxnet3_get_command_status(VMXNET3State *s)
1672{
1673 uint64_t ret;
1674
1675 switch (s->last_command) {
1676 case VMXNET3_CMD_ACTIVATE_DEV:
1677 ret = (s->device_active) ? 0 : 1;
1678 VMW_CFPRN("Device active: %" PRIx64, ret);
1679 break;
1680
1681 case VMXNET3_CMD_RESET_DEV:
1682 case VMXNET3_CMD_QUIESCE_DEV:
1683 case VMXNET3_CMD_GET_QUEUE_STATUS:
1684 case VMXNET3_CMD_GET_DEV_EXTRA_INFO:
1685 ret = 0;
1686 break;
1687
1688 case VMXNET3_CMD_GET_LINK:
1689 ret = s->link_status_and_speed;
1690 VMW_CFPRN("Link and speed: %" PRIx64, ret);
1691 break;
1692
1693 case VMXNET3_CMD_GET_PERM_MAC_LO:
1694 ret = vmxnet3_get_mac_low(&s->perm_mac);
1695 break;
1696
1697 case VMXNET3_CMD_GET_PERM_MAC_HI:
1698 ret = vmxnet3_get_mac_high(&s->perm_mac);
1699 break;
1700
1701 case VMXNET3_CMD_GET_CONF_INTR:
1702 ret = vmxnet3_get_interrupt_config(s);
1703 break;
1704
1705 case VMXNET3_CMD_GET_ADAPTIVE_RING_INFO:
1706 ret = VMXNET3_DISABLE_ADAPTIVE_RING;
1707 break;
1708
1709 case VMXNET3_CMD_GET_DID_LO:
1710 ret = PCI_DEVICE_ID_VMWARE_VMXNET3;
1711 break;
1712
1713 case VMXNET3_CMD_GET_DID_HI:
1714 ret = VMXNET3_DEVICE_REVISION;
1715 break;
1716
1717 default:
1718 VMW_WRPRN("Received request for unknown command: %x", s->last_command);
1719 ret = 0;
1720 break;
1721 }
1722
1723 return ret;
1724}
1725
1726static void vmxnet3_set_events(VMXNET3State *s, uint32_t val)
1727{
1728 uint32_t events;
1729 PCIDevice *d = PCI_DEVICE(s);
1730
1731 VMW_CBPRN("Setting events: 0x%x", val);
1732 events = VMXNET3_READ_DRV_SHARED32(d, s->drv_shmem, ecr) | val;
1733 VMXNET3_WRITE_DRV_SHARED32(d, s->drv_shmem, ecr, events);
1734}
1735
1736static void vmxnet3_ack_events(VMXNET3State *s, uint32_t val)
1737{
1738 PCIDevice *d = PCI_DEVICE(s);
1739 uint32_t events;
1740
1741 VMW_CBPRN("Clearing events: 0x%x", val);
1742 events = VMXNET3_READ_DRV_SHARED32(d, s->drv_shmem, ecr) & ~val;
1743 VMXNET3_WRITE_DRV_SHARED32(d, s->drv_shmem, ecr, events);
1744}
1745
1746static void
1747vmxnet3_io_bar1_write(void *opaque,
1748 hwaddr addr,
1749 uint64_t val,
1750 unsigned size)
1751{
1752 VMXNET3State *s = opaque;
1753
1754 switch (addr) {
1755
1756 case VMXNET3_REG_VRRS:
1757 VMW_CBPRN("Write BAR1 [VMXNET3_REG_VRRS] = %" PRIx64 ", size %d",
1758 val, size);
1759 break;
1760
1761
1762 case VMXNET3_REG_UVRS:
1763 VMW_CBPRN("Write BAR1 [VMXNET3_REG_UVRS] = %" PRIx64 ", size %d",
1764 val, size);
1765 break;
1766
1767
1768 case VMXNET3_REG_DSAL:
1769 VMW_CBPRN("Write BAR1 [VMXNET3_REG_DSAL] = %" PRIx64 ", size %d",
1770 val, size);
1771
1772
1773
1774
1775
1776 if (val == 0) {
1777 vmxnet3_deactivate_device(s);
1778 }
1779 s->temp_shared_guest_driver_memory = val;
1780 s->drv_shmem = 0;
1781 break;
1782
1783
1784 case VMXNET3_REG_DSAH:
1785 VMW_CBPRN("Write BAR1 [VMXNET3_REG_DSAH] = %" PRIx64 ", size %d",
1786 val, size);
1787
1788
1789
1790
1791 s->drv_shmem = s->temp_shared_guest_driver_memory | (val << 32);
1792 break;
1793
1794
1795 case VMXNET3_REG_CMD:
1796 VMW_CBPRN("Write BAR1 [VMXNET3_REG_CMD] = %" PRIx64 ", size %d",
1797 val, size);
1798 vmxnet3_handle_command(s, val);
1799 break;
1800
1801
1802 case VMXNET3_REG_MACL:
1803 VMW_CBPRN("Write BAR1 [VMXNET3_REG_MACL] = %" PRIx64 ", size %d",
1804 val, size);
1805 s->temp_mac = val;
1806 break;
1807
1808
1809 case VMXNET3_REG_MACH:
1810 VMW_CBPRN("Write BAR1 [VMXNET3_REG_MACH] = %" PRIx64 ", size %d",
1811 val, size);
1812 vmxnet3_set_variable_mac(s, val, s->temp_mac);
1813 break;
1814
1815
1816 case VMXNET3_REG_ICR:
1817 VMW_CBPRN("Write BAR1 [VMXNET3_REG_ICR] = %" PRIx64 ", size %d",
1818 val, size);
1819 g_assert_not_reached();
1820 break;
1821
1822
1823 case VMXNET3_REG_ECR:
1824 VMW_CBPRN("Write BAR1 [VMXNET3_REG_ECR] = %" PRIx64 ", size %d",
1825 val, size);
1826 vmxnet3_ack_events(s, val);
1827 break;
1828
1829 default:
1830 VMW_CBPRN("Unknown Write to BAR1 [%" PRIx64 "] = %" PRIx64 ", size %d",
1831 addr, val, size);
1832 break;
1833 }
1834}
1835
1836static uint64_t
1837vmxnet3_io_bar1_read(void *opaque, hwaddr addr, unsigned size)
1838{
1839 VMXNET3State *s = opaque;
1840 uint64_t ret = 0;
1841
1842 switch (addr) {
1843
1844 case VMXNET3_REG_VRRS:
1845 VMW_CBPRN("Read BAR1 [VMXNET3_REG_VRRS], size %d", size);
1846 ret = VMXNET3_DEVICE_REVISION;
1847 break;
1848
1849
1850 case VMXNET3_REG_UVRS:
1851 VMW_CBPRN("Read BAR1 [VMXNET3_REG_UVRS], size %d", size);
1852 ret = VMXNET3_UPT_REVISION;
1853 break;
1854
1855
1856 case VMXNET3_REG_CMD:
1857 VMW_CBPRN("Read BAR1 [VMXNET3_REG_CMD], size %d", size);
1858 ret = vmxnet3_get_command_status(s);
1859 break;
1860
1861
1862 case VMXNET3_REG_MACL:
1863 VMW_CBPRN("Read BAR1 [VMXNET3_REG_MACL], size %d", size);
1864 ret = vmxnet3_get_mac_low(&s->conf.macaddr);
1865 break;
1866
1867
1868 case VMXNET3_REG_MACH:
1869 VMW_CBPRN("Read BAR1 [VMXNET3_REG_MACH], size %d", size);
1870 ret = vmxnet3_get_mac_high(&s->conf.macaddr);
1871 break;
1872
1873
1874
1875
1876
1877 case VMXNET3_REG_ICR:
1878 VMW_CBPRN("Read BAR1 [VMXNET3_REG_ICR], size %d", size);
1879 if (vmxnet3_interrupt_asserted(s, 0)) {
1880 vmxnet3_clear_interrupt(s, 0);
1881 ret = true;
1882 } else {
1883 ret = false;
1884 }
1885 break;
1886
1887 default:
1888 VMW_CBPRN("Unknow read BAR1[%" PRIx64 "], %d bytes", addr, size);
1889 break;
1890 }
1891
1892 return ret;
1893}
1894
1895static int
1896vmxnet3_can_receive(NetClientState *nc)
1897{
1898 VMXNET3State *s = qemu_get_nic_opaque(nc);
1899 return s->device_active &&
1900 VMXNET_FLAG_IS_SET(s->link_status_and_speed, VMXNET3_LINK_STATUS_UP);
1901}
1902
1903static inline bool
1904vmxnet3_is_registered_vlan(VMXNET3State *s, const void *data)
1905{
1906 uint16_t vlan_tag = eth_get_pkt_tci(data) & VLAN_VID_MASK;
1907 if (IS_SPECIAL_VLAN_ID(vlan_tag)) {
1908 return true;
1909 }
1910
1911 return VMXNET3_VFTABLE_ENTRY_IS_SET(s->vlan_table, vlan_tag);
1912}
1913
1914static bool
1915vmxnet3_is_allowed_mcast_group(VMXNET3State *s, const uint8_t *group_mac)
1916{
1917 int i;
1918 for (i = 0; i < s->mcast_list_len; i++) {
1919 if (!memcmp(group_mac, s->mcast_list[i].a, sizeof(s->mcast_list[i]))) {
1920 return true;
1921 }
1922 }
1923 return false;
1924}
1925
1926static bool
1927vmxnet3_rx_filter_may_indicate(VMXNET3State *s, const void *data,
1928 size_t size)
1929{
1930 struct eth_header *ehdr = PKT_GET_ETH_HDR(data);
1931
1932 if (VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_PROMISC)) {
1933 return true;
1934 }
1935
1936 if (!vmxnet3_is_registered_vlan(s, data)) {
1937 return false;
1938 }
1939
1940 switch (net_rx_pkt_get_packet_type(s->rx_pkt)) {
1941 case ETH_PKT_UCAST:
1942 if (!VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_UCAST)) {
1943 return false;
1944 }
1945 if (memcmp(s->conf.macaddr.a, ehdr->h_dest, ETH_ALEN)) {
1946 return false;
1947 }
1948 break;
1949
1950 case ETH_PKT_BCAST:
1951 if (!VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_BCAST)) {
1952 return false;
1953 }
1954 break;
1955
1956 case ETH_PKT_MCAST:
1957 if (VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_ALL_MULTI)) {
1958 return true;
1959 }
1960 if (!VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_MCAST)) {
1961 return false;
1962 }
1963 if (!vmxnet3_is_allowed_mcast_group(s, ehdr->h_dest)) {
1964 return false;
1965 }
1966 break;
1967
1968 default:
1969 g_assert_not_reached();
1970 }
1971
1972 return true;
1973}
1974
1975static ssize_t
1976vmxnet3_receive(NetClientState *nc, const uint8_t *buf, size_t size)
1977{
1978 VMXNET3State *s = qemu_get_nic_opaque(nc);
1979 size_t bytes_indicated;
1980 uint8_t min_buf[MIN_BUF_SIZE];
1981
1982 if (!vmxnet3_can_receive(nc)) {
1983 VMW_PKPRN("Cannot receive now");
1984 return -1;
1985 }
1986
1987 if (s->peer_has_vhdr) {
1988 net_rx_pkt_set_vhdr(s->rx_pkt, (struct virtio_net_hdr *)buf);
1989 buf += sizeof(struct virtio_net_hdr);
1990 size -= sizeof(struct virtio_net_hdr);
1991 }
1992
1993
1994 if (size < sizeof(min_buf)) {
1995 memcpy(min_buf, buf, size);
1996 memset(&min_buf[size], 0, sizeof(min_buf) - size);
1997 buf = min_buf;
1998 size = sizeof(min_buf);
1999 }
2000
2001 net_rx_pkt_set_packet_type(s->rx_pkt,
2002 get_eth_packet_type(PKT_GET_ETH_HDR(buf)));
2003
2004 if (vmxnet3_rx_filter_may_indicate(s, buf, size)) {
2005 net_rx_pkt_set_protocols(s->rx_pkt, buf, size);
2006 vmxnet3_rx_need_csum_calculate(s->rx_pkt, buf, size);
2007 net_rx_pkt_attach_data(s->rx_pkt, buf, size, s->rx_vlan_stripping);
2008 bytes_indicated = vmxnet3_indicate_packet(s) ? size : -1;
2009 if (bytes_indicated < size) {
2010 VMW_PKPRN("RX: %zu of %zu bytes indicated", bytes_indicated, size);
2011 }
2012 } else {
2013 VMW_PKPRN("Packet dropped by RX filter");
2014 bytes_indicated = size;
2015 }
2016
2017 assert(size > 0);
2018 assert(bytes_indicated != 0);
2019 return bytes_indicated;
2020}
2021
2022static void vmxnet3_set_link_status(NetClientState *nc)
2023{
2024 VMXNET3State *s = qemu_get_nic_opaque(nc);
2025
2026 if (nc->link_down) {
2027 s->link_status_and_speed &= ~VMXNET3_LINK_STATUS_UP;
2028 } else {
2029 s->link_status_and_speed |= VMXNET3_LINK_STATUS_UP;
2030 }
2031
2032 vmxnet3_set_events(s, VMXNET3_ECR_LINK);
2033 vmxnet3_trigger_interrupt(s, s->event_int_idx);
2034}
2035
2036static NetClientInfo net_vmxnet3_info = {
2037 .type = NET_CLIENT_DRIVER_NIC,
2038 .size = sizeof(NICState),
2039 .receive = vmxnet3_receive,
2040 .link_status_changed = vmxnet3_set_link_status,
2041};
2042
2043static bool vmxnet3_peer_has_vnet_hdr(VMXNET3State *s)
2044{
2045 NetClientState *nc = qemu_get_queue(s->nic);
2046
2047 if (qemu_has_vnet_hdr(nc->peer)) {
2048 return true;
2049 }
2050
2051 return false;
2052}
2053
2054static void vmxnet3_net_uninit(VMXNET3State *s)
2055{
2056 g_free(s->mcast_list);
2057 vmxnet3_deactivate_device(s);
2058 qemu_del_nic(s->nic);
2059}
2060
2061static void vmxnet3_net_init(VMXNET3State *s)
2062{
2063 DeviceState *d = DEVICE(s);
2064
2065 VMW_CBPRN("vmxnet3_net_init called...");
2066
2067 qemu_macaddr_default_if_unset(&s->conf.macaddr);
2068
2069
2070 memcpy(&s->perm_mac.a, &s->conf.macaddr.a, sizeof(s->perm_mac.a));
2071
2072 s->mcast_list = NULL;
2073 s->mcast_list_len = 0;
2074
2075 s->link_status_and_speed = VMXNET3_LINK_SPEED | VMXNET3_LINK_STATUS_UP;
2076
2077 VMW_CFPRN("Permanent MAC: " MAC_FMT, MAC_ARG(s->perm_mac.a));
2078
2079 s->nic = qemu_new_nic(&net_vmxnet3_info, &s->conf,
2080 object_get_typename(OBJECT(s)),
2081 d->id, s);
2082
2083 s->peer_has_vhdr = vmxnet3_peer_has_vnet_hdr(s);
2084 s->tx_sop = true;
2085 s->skip_current_tx_pkt = false;
2086 s->tx_pkt = NULL;
2087 s->rx_pkt = NULL;
2088 s->rx_vlan_stripping = false;
2089 s->lro_supported = false;
2090
2091 if (s->peer_has_vhdr) {
2092 qemu_set_vnet_hdr_len(qemu_get_queue(s->nic)->peer,
2093 sizeof(struct virtio_net_hdr));
2094
2095 qemu_using_vnet_hdr(qemu_get_queue(s->nic)->peer, 1);
2096 }
2097
2098 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
2099}
2100
2101static void
2102vmxnet3_unuse_msix_vectors(VMXNET3State *s, int num_vectors)
2103{
2104 PCIDevice *d = PCI_DEVICE(s);
2105 int i;
2106 for (i = 0; i < num_vectors; i++) {
2107 msix_vector_unuse(d, i);
2108 }
2109}
2110
2111static bool
2112vmxnet3_use_msix_vectors(VMXNET3State *s, int num_vectors)
2113{
2114 PCIDevice *d = PCI_DEVICE(s);
2115 int i;
2116 for (i = 0; i < num_vectors; i++) {
2117 int res = msix_vector_use(d, i);
2118 if (0 > res) {
2119 VMW_WRPRN("Failed to use MSI-X vector %d, error %d", i, res);
2120 vmxnet3_unuse_msix_vectors(s, i);
2121 return false;
2122 }
2123 }
2124 return true;
2125}
2126
2127static bool
2128vmxnet3_init_msix(VMXNET3State *s)
2129{
2130 PCIDevice *d = PCI_DEVICE(s);
2131 int res = msix_init(d, VMXNET3_MAX_INTRS,
2132 &s->msix_bar,
2133 VMXNET3_MSIX_BAR_IDX, VMXNET3_OFF_MSIX_TABLE,
2134 &s->msix_bar,
2135 VMXNET3_MSIX_BAR_IDX, VMXNET3_OFF_MSIX_PBA(s),
2136 VMXNET3_MSIX_OFFSET(s), NULL);
2137
2138 if (0 > res) {
2139 VMW_WRPRN("Failed to initialize MSI-X, error %d", res);
2140 s->msix_used = false;
2141 } else {
2142 if (!vmxnet3_use_msix_vectors(s, VMXNET3_MAX_INTRS)) {
2143 VMW_WRPRN("Failed to use MSI-X vectors, error %d", res);
2144 msix_uninit(d, &s->msix_bar, &s->msix_bar);
2145 s->msix_used = false;
2146 } else {
2147 s->msix_used = true;
2148 }
2149 }
2150 return s->msix_used;
2151}
2152
2153static void
2154vmxnet3_cleanup_msix(VMXNET3State *s)
2155{
2156 PCIDevice *d = PCI_DEVICE(s);
2157
2158 if (s->msix_used) {
2159 vmxnet3_unuse_msix_vectors(s, VMXNET3_MAX_INTRS);
2160 msix_uninit(d, &s->msix_bar, &s->msix_bar);
2161 }
2162}
2163
2164static void
2165vmxnet3_cleanup_msi(VMXNET3State *s)
2166{
2167 PCIDevice *d = PCI_DEVICE(s);
2168
2169 msi_uninit(d);
2170}
2171
2172static const MemoryRegionOps b0_ops = {
2173 .read = vmxnet3_io_bar0_read,
2174 .write = vmxnet3_io_bar0_write,
2175 .endianness = DEVICE_LITTLE_ENDIAN,
2176 .impl = {
2177 .min_access_size = 4,
2178 .max_access_size = 4,
2179 },
2180};
2181
2182static const MemoryRegionOps b1_ops = {
2183 .read = vmxnet3_io_bar1_read,
2184 .write = vmxnet3_io_bar1_write,
2185 .endianness = DEVICE_LITTLE_ENDIAN,
2186 .impl = {
2187 .min_access_size = 4,
2188 .max_access_size = 4,
2189 },
2190};
2191
2192static uint64_t vmxnet3_device_serial_num(VMXNET3State *s)
2193{
2194 uint64_t dsn_payload;
2195 uint8_t *dsnp = (uint8_t *)&dsn_payload;
2196
2197 dsnp[0] = 0xfe;
2198 dsnp[1] = s->conf.macaddr.a[3];
2199 dsnp[2] = s->conf.macaddr.a[4];
2200 dsnp[3] = s->conf.macaddr.a[5];
2201 dsnp[4] = s->conf.macaddr.a[0];
2202 dsnp[5] = s->conf.macaddr.a[1];
2203 dsnp[6] = s->conf.macaddr.a[2];
2204 dsnp[7] = 0xff;
2205 return dsn_payload;
2206}
2207
2208
2209#define VMXNET3_USE_64BIT (true)
2210#define VMXNET3_PER_VECTOR_MASK (false)
2211
2212static void vmxnet3_pci_realize(PCIDevice *pci_dev, Error **errp)
2213{
2214 VMXNET3State *s = VMXNET3(pci_dev);
2215 int ret;
2216
2217 VMW_CBPRN("Starting init...");
2218
2219 memory_region_init_io(&s->bar0, OBJECT(s), &b0_ops, s,
2220 "vmxnet3-b0", VMXNET3_PT_REG_SIZE);
2221 pci_register_bar(pci_dev, VMXNET3_BAR0_IDX,
2222 PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0);
2223
2224 memory_region_init_io(&s->bar1, OBJECT(s), &b1_ops, s,
2225 "vmxnet3-b1", VMXNET3_VD_REG_SIZE);
2226 pci_register_bar(pci_dev, VMXNET3_BAR1_IDX,
2227 PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar1);
2228
2229 memory_region_init(&s->msix_bar, OBJECT(s), "vmxnet3-msix-bar",
2230 VMXNET3_MSIX_BAR_SIZE);
2231 pci_register_bar(pci_dev, VMXNET3_MSIX_BAR_IDX,
2232 PCI_BASE_ADDRESS_SPACE_MEMORY, &s->msix_bar);
2233
2234 vmxnet3_reset_interrupt_states(s);
2235
2236
2237 pci_dev->config[PCI_INTERRUPT_PIN] = 0x01;
2238
2239 ret = msi_init(pci_dev, VMXNET3_MSI_OFFSET(s), VMXNET3_MAX_NMSIX_INTRS,
2240 VMXNET3_USE_64BIT, VMXNET3_PER_VECTOR_MASK, NULL);
2241
2242
2243 assert(!ret || ret == -ENOTSUP);
2244
2245 if (!vmxnet3_init_msix(s)) {
2246 VMW_WRPRN("Failed to initialize MSI-X, configuration is inconsistent.");
2247 }
2248
2249 vmxnet3_net_init(s);
2250
2251 if (pci_is_express(pci_dev)) {
2252 if (pci_bus_is_express(pci_get_bus(pci_dev))) {
2253 pcie_endpoint_cap_init(pci_dev, VMXNET3_EXP_EP_OFFSET);
2254 }
2255
2256 pcie_dev_ser_num_init(pci_dev, VMXNET3_DSN_OFFSET,
2257 vmxnet3_device_serial_num(s));
2258 }
2259}
2260
2261static void vmxnet3_instance_init(Object *obj)
2262{
2263 VMXNET3State *s = VMXNET3(obj);
2264 device_add_bootindex_property(obj, &s->conf.bootindex,
2265 "bootindex", "/ethernet-phy@0",
2266 DEVICE(obj));
2267}
2268
2269static void vmxnet3_pci_uninit(PCIDevice *pci_dev)
2270{
2271 VMXNET3State *s = VMXNET3(pci_dev);
2272
2273 VMW_CBPRN("Starting uninit...");
2274
2275 vmxnet3_net_uninit(s);
2276
2277 vmxnet3_cleanup_msix(s);
2278
2279 vmxnet3_cleanup_msi(s);
2280}
2281
2282static void vmxnet3_qdev_reset(DeviceState *dev)
2283{
2284 PCIDevice *d = PCI_DEVICE(dev);
2285 VMXNET3State *s = VMXNET3(d);
2286
2287 VMW_CBPRN("Starting QDEV reset...");
2288 vmxnet3_reset(s);
2289}
2290
2291static bool vmxnet3_mc_list_needed(void *opaque)
2292{
2293 return true;
2294}
2295
2296static int vmxnet3_mcast_list_pre_load(void *opaque)
2297{
2298 VMXNET3State *s = opaque;
2299
2300 s->mcast_list = g_malloc(s->mcast_list_buff_size);
2301
2302 return 0;
2303}
2304
2305
2306static int vmxnet3_pre_save(void *opaque)
2307{
2308 VMXNET3State *s = opaque;
2309
2310 s->mcast_list_buff_size = s->mcast_list_len * sizeof(MACAddr);
2311
2312 return 0;
2313}
2314
2315static const VMStateDescription vmxstate_vmxnet3_mcast_list = {
2316 .name = "vmxnet3/mcast_list",
2317 .version_id = 1,
2318 .minimum_version_id = 1,
2319 .pre_load = vmxnet3_mcast_list_pre_load,
2320 .needed = vmxnet3_mc_list_needed,
2321 .fields = (VMStateField[]) {
2322 VMSTATE_VBUFFER_UINT32(mcast_list, VMXNET3State, 0, NULL,
2323 mcast_list_buff_size),
2324 VMSTATE_END_OF_LIST()
2325 }
2326};
2327
2328static const VMStateDescription vmstate_vmxnet3_ring = {
2329 .name = "vmxnet3-ring",
2330 .version_id = 0,
2331 .fields = (VMStateField[]) {
2332 VMSTATE_UINT64(pa, Vmxnet3Ring),
2333 VMSTATE_UINT32(size, Vmxnet3Ring),
2334 VMSTATE_UINT32(cell_size, Vmxnet3Ring),
2335 VMSTATE_UINT32(next, Vmxnet3Ring),
2336 VMSTATE_UINT8(gen, Vmxnet3Ring),
2337 VMSTATE_END_OF_LIST()
2338 }
2339};
2340
2341static const VMStateDescription vmstate_vmxnet3_tx_stats = {
2342 .name = "vmxnet3-tx-stats",
2343 .version_id = 0,
2344 .fields = (VMStateField[]) {
2345 VMSTATE_UINT64(TSOPktsTxOK, struct UPT1_TxStats),
2346 VMSTATE_UINT64(TSOBytesTxOK, struct UPT1_TxStats),
2347 VMSTATE_UINT64(ucastPktsTxOK, struct UPT1_TxStats),
2348 VMSTATE_UINT64(ucastBytesTxOK, struct UPT1_TxStats),
2349 VMSTATE_UINT64(mcastPktsTxOK, struct UPT1_TxStats),
2350 VMSTATE_UINT64(mcastBytesTxOK, struct UPT1_TxStats),
2351 VMSTATE_UINT64(bcastPktsTxOK, struct UPT1_TxStats),
2352 VMSTATE_UINT64(bcastBytesTxOK, struct UPT1_TxStats),
2353 VMSTATE_UINT64(pktsTxError, struct UPT1_TxStats),
2354 VMSTATE_UINT64(pktsTxDiscard, struct UPT1_TxStats),
2355 VMSTATE_END_OF_LIST()
2356 }
2357};
2358
2359static const VMStateDescription vmstate_vmxnet3_txq_descr = {
2360 .name = "vmxnet3-txq-descr",
2361 .version_id = 0,
2362 .fields = (VMStateField[]) {
2363 VMSTATE_STRUCT(tx_ring, Vmxnet3TxqDescr, 0, vmstate_vmxnet3_ring,
2364 Vmxnet3Ring),
2365 VMSTATE_STRUCT(comp_ring, Vmxnet3TxqDescr, 0, vmstate_vmxnet3_ring,
2366 Vmxnet3Ring),
2367 VMSTATE_UINT8(intr_idx, Vmxnet3TxqDescr),
2368 VMSTATE_UINT64(tx_stats_pa, Vmxnet3TxqDescr),
2369 VMSTATE_STRUCT(txq_stats, Vmxnet3TxqDescr, 0, vmstate_vmxnet3_tx_stats,
2370 struct UPT1_TxStats),
2371 VMSTATE_END_OF_LIST()
2372 }
2373};
2374
2375static const VMStateDescription vmstate_vmxnet3_rx_stats = {
2376 .name = "vmxnet3-rx-stats",
2377 .version_id = 0,
2378 .fields = (VMStateField[]) {
2379 VMSTATE_UINT64(LROPktsRxOK, struct UPT1_RxStats),
2380 VMSTATE_UINT64(LROBytesRxOK, struct UPT1_RxStats),
2381 VMSTATE_UINT64(ucastPktsRxOK, struct UPT1_RxStats),
2382 VMSTATE_UINT64(ucastBytesRxOK, struct UPT1_RxStats),
2383 VMSTATE_UINT64(mcastPktsRxOK, struct UPT1_RxStats),
2384 VMSTATE_UINT64(mcastBytesRxOK, struct UPT1_RxStats),
2385 VMSTATE_UINT64(bcastPktsRxOK, struct UPT1_RxStats),
2386 VMSTATE_UINT64(bcastBytesRxOK, struct UPT1_RxStats),
2387 VMSTATE_UINT64(pktsRxOutOfBuf, struct UPT1_RxStats),
2388 VMSTATE_UINT64(pktsRxError, struct UPT1_RxStats),
2389 VMSTATE_END_OF_LIST()
2390 }
2391};
2392
2393static const VMStateDescription vmstate_vmxnet3_rxq_descr = {
2394 .name = "vmxnet3-rxq-descr",
2395 .version_id = 0,
2396 .fields = (VMStateField[]) {
2397 VMSTATE_STRUCT_ARRAY(rx_ring, Vmxnet3RxqDescr,
2398 VMXNET3_RX_RINGS_PER_QUEUE, 0,
2399 vmstate_vmxnet3_ring, Vmxnet3Ring),
2400 VMSTATE_STRUCT(comp_ring, Vmxnet3RxqDescr, 0, vmstate_vmxnet3_ring,
2401 Vmxnet3Ring),
2402 VMSTATE_UINT8(intr_idx, Vmxnet3RxqDescr),
2403 VMSTATE_UINT64(rx_stats_pa, Vmxnet3RxqDescr),
2404 VMSTATE_STRUCT(rxq_stats, Vmxnet3RxqDescr, 0, vmstate_vmxnet3_rx_stats,
2405 struct UPT1_RxStats),
2406 VMSTATE_END_OF_LIST()
2407 }
2408};
2409
2410static int vmxnet3_post_load(void *opaque, int version_id)
2411{
2412 VMXNET3State *s = opaque;
2413 PCIDevice *d = PCI_DEVICE(s);
2414
2415 net_tx_pkt_init(&s->tx_pkt, PCI_DEVICE(s),
2416 s->max_tx_frags, s->peer_has_vhdr);
2417 net_rx_pkt_init(&s->rx_pkt, s->peer_has_vhdr);
2418
2419 if (s->msix_used) {
2420 if (!vmxnet3_use_msix_vectors(s, VMXNET3_MAX_INTRS)) {
2421 VMW_WRPRN("Failed to re-use MSI-X vectors");
2422 msix_uninit(d, &s->msix_bar, &s->msix_bar);
2423 s->msix_used = false;
2424 return -1;
2425 }
2426 }
2427
2428 if (!vmxnet3_validate_queues(s)) {
2429 return -1;
2430 }
2431 vmxnet3_validate_interrupts(s);
2432
2433 return 0;
2434}
2435
2436static const VMStateDescription vmstate_vmxnet3_int_state = {
2437 .name = "vmxnet3-int-state",
2438 .version_id = 0,
2439 .fields = (VMStateField[]) {
2440 VMSTATE_BOOL(is_masked, Vmxnet3IntState),
2441 VMSTATE_BOOL(is_pending, Vmxnet3IntState),
2442 VMSTATE_BOOL(is_asserted, Vmxnet3IntState),
2443 VMSTATE_END_OF_LIST()
2444 }
2445};
2446
2447static const VMStateDescription vmstate_vmxnet3 = {
2448 .name = "vmxnet3",
2449 .version_id = 1,
2450 .minimum_version_id = 1,
2451 .pre_save = vmxnet3_pre_save,
2452 .post_load = vmxnet3_post_load,
2453 .fields = (VMStateField[]) {
2454 VMSTATE_PCI_DEVICE(parent_obj, VMXNET3State),
2455 VMSTATE_MSIX(parent_obj, VMXNET3State),
2456 VMSTATE_BOOL(rx_packets_compound, VMXNET3State),
2457 VMSTATE_BOOL(rx_vlan_stripping, VMXNET3State),
2458 VMSTATE_BOOL(lro_supported, VMXNET3State),
2459 VMSTATE_UINT32(rx_mode, VMXNET3State),
2460 VMSTATE_UINT32(mcast_list_len, VMXNET3State),
2461 VMSTATE_UINT32(mcast_list_buff_size, VMXNET3State),
2462 VMSTATE_UINT32_ARRAY(vlan_table, VMXNET3State, VMXNET3_VFT_SIZE),
2463 VMSTATE_UINT32(mtu, VMXNET3State),
2464 VMSTATE_UINT16(max_rx_frags, VMXNET3State),
2465 VMSTATE_UINT32(max_tx_frags, VMXNET3State),
2466 VMSTATE_UINT8(event_int_idx, VMXNET3State),
2467 VMSTATE_BOOL(auto_int_masking, VMXNET3State),
2468 VMSTATE_UINT8(txq_num, VMXNET3State),
2469 VMSTATE_UINT8(rxq_num, VMXNET3State),
2470 VMSTATE_UINT32(device_active, VMXNET3State),
2471 VMSTATE_UINT32(last_command, VMXNET3State),
2472 VMSTATE_UINT32(link_status_and_speed, VMXNET3State),
2473 VMSTATE_UINT32(temp_mac, VMXNET3State),
2474 VMSTATE_UINT64(drv_shmem, VMXNET3State),
2475 VMSTATE_UINT64(temp_shared_guest_driver_memory, VMXNET3State),
2476
2477 VMSTATE_STRUCT_ARRAY(txq_descr, VMXNET3State,
2478 VMXNET3_DEVICE_MAX_TX_QUEUES, 0, vmstate_vmxnet3_txq_descr,
2479 Vmxnet3TxqDescr),
2480 VMSTATE_STRUCT_ARRAY(rxq_descr, VMXNET3State,
2481 VMXNET3_DEVICE_MAX_RX_QUEUES, 0, vmstate_vmxnet3_rxq_descr,
2482 Vmxnet3RxqDescr),
2483 VMSTATE_STRUCT_ARRAY(interrupt_states, VMXNET3State,
2484 VMXNET3_MAX_INTRS, 0, vmstate_vmxnet3_int_state,
2485 Vmxnet3IntState),
2486
2487 VMSTATE_END_OF_LIST()
2488 },
2489 .subsections = (const VMStateDescription*[]) {
2490 &vmxstate_vmxnet3_mcast_list,
2491 NULL
2492 }
2493};
2494
2495static Property vmxnet3_properties[] = {
2496 DEFINE_NIC_PROPERTIES(VMXNET3State, conf),
2497 DEFINE_PROP_BIT("x-old-msi-offsets", VMXNET3State, compat_flags,
2498 VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS_BIT, false),
2499 DEFINE_PROP_BIT("x-disable-pcie", VMXNET3State, compat_flags,
2500 VMXNET3_COMPAT_FLAG_DISABLE_PCIE_BIT, false),
2501 DEFINE_PROP_END_OF_LIST(),
2502};
2503
2504static void vmxnet3_realize(DeviceState *qdev, Error **errp)
2505{
2506 VMXNET3Class *vc = VMXNET3_DEVICE_GET_CLASS(qdev);
2507 PCIDevice *pci_dev = PCI_DEVICE(qdev);
2508 VMXNET3State *s = VMXNET3(qdev);
2509
2510 if (!(s->compat_flags & VMXNET3_COMPAT_FLAG_DISABLE_PCIE)) {
2511 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
2512 }
2513
2514 vc->parent_dc_realize(qdev, errp);
2515}
2516
2517static void vmxnet3_class_init(ObjectClass *class, void *data)
2518{
2519 DeviceClass *dc = DEVICE_CLASS(class);
2520 PCIDeviceClass *c = PCI_DEVICE_CLASS(class);
2521 VMXNET3Class *vc = VMXNET3_DEVICE_CLASS(class);
2522
2523 c->realize = vmxnet3_pci_realize;
2524 c->exit = vmxnet3_pci_uninit;
2525 c->vendor_id = PCI_VENDOR_ID_VMWARE;
2526 c->device_id = PCI_DEVICE_ID_VMWARE_VMXNET3;
2527 c->revision = PCI_DEVICE_ID_VMWARE_VMXNET3_REVISION;
2528 c->romfile = "efi-vmxnet3.rom";
2529 c->class_id = PCI_CLASS_NETWORK_ETHERNET;
2530 c->subsystem_vendor_id = PCI_VENDOR_ID_VMWARE;
2531 c->subsystem_id = PCI_DEVICE_ID_VMWARE_VMXNET3;
2532 device_class_set_parent_realize(dc, vmxnet3_realize,
2533 &vc->parent_dc_realize);
2534 dc->desc = "VMWare Paravirtualized Ethernet v3";
2535 dc->reset = vmxnet3_qdev_reset;
2536 dc->vmsd = &vmstate_vmxnet3;
2537 device_class_set_props(dc, vmxnet3_properties);
2538 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
2539}
2540
2541static const TypeInfo vmxnet3_info = {
2542 .name = TYPE_VMXNET3,
2543 .parent = TYPE_PCI_DEVICE,
2544 .class_size = sizeof(VMXNET3Class),
2545 .instance_size = sizeof(VMXNET3State),
2546 .class_init = vmxnet3_class_init,
2547 .instance_init = vmxnet3_instance_init,
2548 .interfaces = (InterfaceInfo[]) {
2549 { INTERFACE_PCIE_DEVICE },
2550 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
2551 { }
2552 },
2553};
2554
2555static void vmxnet3_register_types(void)
2556{
2557 VMW_CBPRN("vmxnet3_register_types called...");
2558 type_register_static(&vmxnet3_info);
2559}
2560
2561type_init(vmxnet3_register_types)
2562
