LXR qemu/hw/pci-bridge/simba.c

   1/*
   2 * QEMU Simba PCI bridge
   3 *
   4 * Copyright (c) 2006 Fabrice Bellard
   5 * Copyright (c) 2012,2013 Artyom Tarasenko
   6 * Copyright (c) 2018 Mark Cave-Ayland
   7 *
   8 * Permission is hereby granted, free of charge, to any person obtaining a copy
   9 * of this software and associated documentation files (the "Software"), to deal
  10 * in the Software without restriction, including without limitation the rights
  11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12 * copies of the Software, and to permit persons to whom the Software is
  13 * furnished to do so, subject to the following conditions:
  14 *
  15 * The above copyright notice and this permission notice shall be included in
  16 * all copies or substantial portions of the Software.
  17 *
  18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24 * THE SOFTWARE.
  25 */
  26
  27#include "qemu/osdep.h"
  28#include "hw/pci/pci.h"
  29#include "hw/pci/pci_bridge.h"
  30#include "hw/pci/pci_bus.h"
  31#include "qemu/module.h"
  32#include "hw/pci-bridge/simba.h"
  33
  34/*
  35 * Chipset docs:
  36 * APB: "Advanced PCI Bridge (APB) User's Manual",
  37 * http://www.sun.com/processors/manuals/805-1251.pdf
  38 */
  39
  40static void simba_pci_bridge_realize(PCIDevice *dev, Error **errp)
  41{
  42    /*
  43     * command register:
  44     * According to PCI bridge spec, after reset
  45     *   bus master bit is off
  46     *   memory space enable bit is off
  47     * According to manual (805-1251.pdf).
  48     *   the reset value should be zero unless the boot pin is tied high
  49     *   (which is true) and thus it should be PCI_COMMAND_MEMORY.
  50     */
  51    SimbaPCIBridge *br = SIMBA_PCI_BRIDGE(dev);
  52
  53    pci_bridge_initfn(dev, TYPE_PCI_BUS);
  54
  55    pci_set_word(dev->config + PCI_COMMAND, PCI_COMMAND_MEMORY);
  56    pci_set_word(dev->config + PCI_STATUS,
  57                 PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ |
  58                 PCI_STATUS_DEVSEL_MEDIUM);
  59
  60    /* Allow 32-bit IO addresses */
  61    pci_set_word(dev->config + PCI_IO_BASE, PCI_IO_RANGE_TYPE_32);
  62    pci_set_word(dev->config + PCI_IO_LIMIT, PCI_IO_RANGE_TYPE_32);
  63    pci_set_word(dev->wmask + PCI_IO_BASE_UPPER16, 0xffff);
  64    pci_set_word(dev->wmask + PCI_IO_LIMIT_UPPER16, 0xffff);
  65
  66    pci_bridge_update_mappings(PCI_BRIDGE(br));
  67}
  68
  69static void simba_pci_bridge_class_init(ObjectClass *klass, void *data)
  70{
  71    DeviceClass *dc = DEVICE_CLASS(klass);
  72    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
  73
  74    k->realize = simba_pci_bridge_realize;
  75    k->exit = pci_bridge_exitfn;
  76    k->vendor_id = PCI_VENDOR_ID_SUN;
  77    k->device_id = PCI_DEVICE_ID_SUN_SIMBA;
  78    k->revision = 0x11;
  79    k->config_write = pci_bridge_write_config;
  80    k->is_bridge = true;
  81    set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
  82    dc->reset = pci_bridge_reset;
  83    dc->vmsd = &vmstate_pci_device;
  84}
  85
  86static const TypeInfo simba_pci_bridge_info = {
  87    .name          = TYPE_SIMBA_PCI_BRIDGE,
  88    .parent        = TYPE_PCI_BRIDGE,
  89    .class_init    = simba_pci_bridge_class_init,
  90    .instance_size = sizeof(SimbaPCIBridge),
  91    .interfaces = (InterfaceInfo[]) {
  92        { INTERFACE_CONVENTIONAL_PCI_DEVICE },
  93        { },
  94    },
  95};
  96
  97static void simba_register_types(void)
  98{
  99    type_register_static(&simba_pci_bridge_info);
 100}
 101
 102type_init(simba_register_types)
 103