LXR qemu/hw/pci/pci

   1/*
   2 * QEMU PCI bus manager
   3 *
   4 * Copyright (c) 2004 Fabrice Bellard
   5 *
   6 * Permission is hereby granted, free of charge, to any person obtaining a copy
   7 * of this software and associated documentation files (the "Software"), to dea
   8
   9 * in the Software without restriction, including without limitation the rights
  10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11 * copies of the Software, and to permit persons to whom the Software is
  12 * furnished to do so, subject to the following conditions:
  13 *
  14 * The above copyright notice and this permission notice shall be included in
  15 * all copies or substantial portions of the Software.
  16 *
  17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM
  22
  23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24 * THE SOFTWARE.
  25 */
  26/*
  27 * split out from pci.c
  28 * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
  29 *                    VA Linux Systems Japan K.K.
  30 */
  31
  32#include "qemu/osdep.h"
  33#include "qemu/units.h"
  34#include "hw/pci/pci_bridge.h"
  35#include "hw/pci/pci_bus.h"
  36#include "qemu/module.h"
  37#include "qemu/range.h"
  38#include "qapi/error.h"
  39
  40/* PCI bridge subsystem vendor ID helper functions */
  41#define PCI_SSVID_SIZEOF        8
  42#define PCI_SSVID_SVID          4
  43#define PCI_SSVID_SSID          6
  44
  45int pci_bridge_ssvid_init(PCIDevice *dev, uint8_t offset,
  46                          uint16_t svid, uint16_t ssid,
  47                          Error **errp)
  48{
  49    int pos;
  50
  51    pos = pci_add_capability(dev, PCI_CAP_ID_SSVID, offset,
  52                             PCI_SSVID_SIZEOF, errp);
  53    if (pos < 0) {
  54        return pos;
  55    }
  56
  57    pci_set_word(dev->config + pos + PCI_SSVID_SVID, svid);
  58    pci_set_word(dev->config + pos + PCI_SSVID_SSID, ssid);
  59    return pos;
  60}
  61
  62/* Accessor function to get parent bridge device from pci bus. */
  63PCIDevice *pci_bridge_get_device(PCIBus *bus)
  64{
  65    return bus->parent_dev;
  66}
  67
  68/* Accessor function to get secondary bus from pci-to-pci bridge device */
  69PCIBus *pci_bridge_get_sec_bus(PCIBridge *br)
  70{
  71    return &br->sec_bus;
  72}
  73
  74static uint32_t pci_config_get_io_base(const PCIDevice *d,
  75                                       uint32_t base, uint32_t base_upper16)
  76{
  77    uint32_t val;
  78
  79    val = ((uint32_t)d->config[base] & PCI_IO_RANGE_MASK) << 8;
  80    if (d->config[base] & PCI_IO_RANGE_TYPE_32) {
  81        val |= (uint32_t)pci_get_word(d->config + base_upper16) << 16;
  82    }
  83    return val;
  84}
  85
  86static pcibus_t pci_config_get_memory_base(const PCIDevice *d, uint32_t base)
  87{
  88    return ((pcibus_t)pci_get_word(d->config + base) & PCI_MEMORY_RANGE_MASK)
  89        << 16;
  90}
  91
  92static pcibus_t pci_config_get_pref_base(const PCIDevice *d,
  93                                         uint32_t base, uint32_t upper)
  94{
  95    pcibus_t tmp;
  96    pcibus_t val;
  97
  98    tmp = (pcibus_t)pci_get_word(d->config + base);
  99    val = (tmp & PCI_PREF_RANGE_MASK) << 16;
 100    if (tmp & PCI_PREF_RANGE_TYPE_64) {
 101        val |= (pcibus_t)pci_get_long(d->config + upper) << 32;
 102    }
 103    return val;
 104}
 105
 106/* accessor function to get bridge filtering base address */
 107pcibus_t pci_bridge_get_base(const PCIDevice *bridge, uint8_t type)
 108{
 109    pcibus_t base;
 110    if (type & PCI_BASE_ADDRESS_SPACE_IO) {
 111        base = pci_config_get_io_base(bridge,
 112                                      PCI_IO_BASE, PCI_IO_BASE_UPPER16);
 113    } else {
 114        if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
 115            base = pci_config_get_pref_base(
 116                bridge, PCI_PREF_MEMORY_BASE, PCI_PREF_BASE_UPPER32);
 117        } else {
 118            base = pci_config_get_memory_base(bridge, PCI_MEMORY_BASE);
 119        }
 120    }
 121
 122    return base;
 123}
 124
 125/* accessor function to get bridge filtering limit */
 126pcibus_t pci_bridge_get_limit(const PCIDevice *bridge, uint8_t type)
 127{
 128    pcibus_t limit;
 129    if (type & PCI_BASE_ADDRESS_SPACE_IO) {
 130        limit = pci_config_get_io_base(bridge,
 131                                      PCI_IO_LIMIT, PCI_IO_LIMIT_UPPER16);
 132        limit |= 0xfff;         /* PCI bridge spec 3.2.5.6. */
 133    } else {
 134        if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
 135            limit = pci_config_get_pref_base(
 136                bridge, PCI_PREF_MEMORY_LIMIT, PCI_PREF_LIMIT_UPPER32);
 137        } else {
 138            limit = pci_config_get_memory_base(bridge, PCI_MEMORY_LIMIT);
 139        }
 140        limit |= 0xfffff;       /* PCI bridge spec 3.2.5.{1, 8}. */
 141    }
 142    return limit;
 143}
 144
 145static void pci_bridge_init_alias(PCIBridge *bridge, MemoryRegion *alias,
 146                                  uint8_t type, const char *name,
 147                                  MemoryRegion *space,
 148                                  MemoryRegion *parent_space,
 149                                  bool enabled)
 150{
 151    PCIDevice *bridge_dev = PCI_DEVICE(bridge);
 152    pcibus_t base = pci_bridge_get_base(bridge_dev, type);
 153    pcibus_t limit = pci_bridge_get_limit(bridge_dev, type);
 154    /* TODO: this doesn't handle base = 0 limit = 2^64 - 1 correctly.
 155     * Apparently no way to do this with existing memory APIs. */
 156    pcibus_t size = enabled && limit >= base ? limit + 1 - base : 0;
 157
 158    memory_region_init_alias(alias, OBJECT(bridge), name, space, base, size);
 159    memory_region_add_subregion_overlap(parent_space, base, alias, 1);
 160}
 161
 162static void pci_bridge_init_vga_aliases(PCIBridge *br, PCIBus *parent,
 163                                        MemoryRegion *alias_vga)
 164{
 165    PCIDevice *pd = PCI_DEVICE(br);
 166    uint16_t brctl = pci_get_word(pd->config + PCI_BRIDGE_CONTROL);
 167
 168    memory_region_init_alias(&alias_vga[QEMU_PCI_VGA_IO_LO], OBJECT(br),
 169                             "pci_bridge_vga_io_lo", &br->address_space_io,
 170                             QEMU_PCI_VGA_IO_LO_BASE, QEMU_PCI_VGA_IO_LO_SIZE);
 171    memory_region_init_alias(&alias_vga[QEMU_PCI_VGA_IO_HI], OBJECT(br),
 172                             "pci_bridge_vga_io_hi", &br->address_space_io,
 173                             QEMU_PCI_VGA_IO_HI_BASE, QEMU_PCI_VGA_IO_HI_SIZE);
 174    memory_region_init_alias(&alias_vga[QEMU_PCI_VGA_MEM], OBJECT(br),
 175                             "pci_bridge_vga_mem", &br->address_space_mem,
 176                             QEMU_PCI_VGA_MEM_BASE, QEMU_PCI_VGA_MEM_SIZE);
 177
 178    if (brctl & PCI_BRIDGE_CTL_VGA) {
 179        pci_register_vga(pd, &alias_vga[QEMU_PCI_VGA_MEM],
 180                         &alias_vga[QEMU_PCI_VGA_IO_LO],
 181                         &alias_vga[QEMU_PCI_VGA_IO_HI]);
 182    }
 183}
 184
 185static PCIBridgeWindows *pci_bridge_region_init(PCIBridge *br)
 186{
 187    PCIDevice *pd = PCI_DEVICE(br);
 188    PCIBus *parent = pci_get_bus(pd);
 189    PCIBridgeWindows *w = g_new(PCIBridgeWindows, 1);
 190    uint16_t cmd = pci_get_word(pd->config + PCI_COMMAND);
 191
 192    pci_bridge_init_alias(br, &w->alias_pref_mem,
 193                          PCI_BASE_ADDRESS_MEM_PREFETCH,
 194                          "pci_bridge_pref_mem",
 195                          &br->address_space_mem,
 196                          parent->address_space_mem,
 197                          cmd & PCI_COMMAND_MEMORY);
 198    pci_bridge_init_alias(br, &w->alias_mem,
 199                          PCI_BASE_ADDRESS_SPACE_MEMORY,
 200                          "pci_bridge_mem",
 201                          &br->address_space_mem,
 202                          parent->address_space_mem,
 203                          cmd & PCI_COMMAND_MEMORY);
 204    pci_bridge_init_alias(br, &w->alias_io,
 205                          PCI_BASE_ADDRESS_SPACE_IO,
 206                          "pci_bridge_io",
 207                          &br->address_space_io,
 208                          parent->address_space_io,
 209                          cmd & PCI_COMMAND_IO);
 210
 211    pci_bridge_init_vga_aliases(br, parent, w->alias_vga);
 212
 213    return w;
 214}
 215
 216static void pci_bridge_region_del(PCIBridge *br, PCIBridgeWindows *w)
 217{
 218    PCIDevice *pd = PCI_DEVICE(br);
 219    PCIBus *parent = pci_get_bus(pd);
 220
 221    memory_region_del_subregion(parent->address_space_io, &w->alias_io);
 222    memory_region_del_subregion(parent->address_space_mem, &w->alias_mem);
 223    memory_region_del_subregion(parent->address_space_mem, &w->alias_pref_mem);
 224    pci_unregister_vga(pd);
 225}
 226
 227static void pci_bridge_region_cleanup(PCIBridge *br, PCIBridgeWindows *w)
 228{
 229    object_unparent(OBJECT(&w->alias_io));
 230    object_unparent(OBJECT(&w->alias_mem));
 231    object_unparent(OBJECT(&w->alias_pref_mem));
 232    object_unparent(OBJECT(&w->alias_vga[QEMU_PCI_VGA_IO_LO]));
 233    object_unparent(OBJECT(&w->alias_vga[QEMU_PCI_VGA_IO_HI]));
 234    object_unparent(OBJECT(&w->alias_vga[QEMU_PCI_VGA_MEM]));
 235    g_free(w);
 236}
 237
 238void pci_bridge_update_mappings(PCIBridge *br)
 239{
 240    PCIBridgeWindows *w = br->windows;
 241
 242    /* Make updates atomic to: handle the case of one VCPU updating the bridge
 243     * while another accesses an unaffected region. */
 244    memory_region_transaction_begin();
 245    pci_bridge_region_del(br, br->windows);
 246    pci_bridge_region_cleanup(br, w);
 247    br->windows = pci_bridge_region_init(br);
 248    memory_region_transaction_commit();
 249}
 250
 251/* default write_config function for PCI-to-PCI bridge */
 252void pci_bridge_write_config(PCIDevice *d,
 253                             uint32_t address, uint32_t val, int len)
 254{
 255    PCIBridge *s = PCI_BRIDGE(d);
 256    uint16_t oldctl = pci_get_word(d->config + PCI_BRIDGE_CONTROL);
 257    uint16_t newctl;
 258
 259    pci_default_write_config(d, address, val, len);
 260
 261    if (ranges_overlap(address, len, PCI_COMMAND, 2) ||
 262
 263        /* io base/limit */
 264        ranges_overlap(address, len, PCI_IO_BASE, 2) ||
 265
 266        /* memory base/limit, prefetchable base/limit and
 267           io base/limit upper 16 */
 268        ranges_overlap(address, len, PCI_MEMORY_BASE, 20) ||
 269
 270        /* vga enable */
 271        ranges_overlap(address, len, PCI_BRIDGE_CONTROL, 2)) {
 272        pci_bridge_update_mappings(s);
 273    }
 274
 275    newctl = pci_get_word(d->config + PCI_BRIDGE_CONTROL);
 276    if (~oldctl & newctl & PCI_BRIDGE_CTL_BUS_RESET) {
 277        /* Trigger hot reset on 0->1 transition. */
 278        qbus_reset_all(BUS(&s->sec_bus));
 279    }
 280}
 281
 282void pci_bridge_disable_base_limit(PCIDevice *dev)
 283{
 284    uint8_t *conf = dev->config;
 285
 286    pci_byte_test_and_set_mask(conf + PCI_IO_BASE,
 287                               PCI_IO_RANGE_MASK & 0xff);
 288    pci_byte_test_and_clear_mask(conf + PCI_IO_LIMIT,
 289                                 PCI_IO_RANGE_MASK & 0xff);
 290    pci_word_test_and_set_mask(conf + PCI_MEMORY_BASE,
 291                               PCI_MEMORY_RANGE_MASK & 0xffff);
 292    pci_word_test_and_clear_mask(conf + PCI_MEMORY_LIMIT,
 293                                 PCI_MEMORY_RANGE_MASK & 0xffff);
 294    pci_word_test_and_set_mask(conf + PCI_PREF_MEMORY_BASE,
 295                               PCI_PREF_RANGE_MASK & 0xffff);
 296    pci_word_test_and_clear_mask(conf + PCI_PREF_MEMORY_LIMIT,
 297                                 PCI_PREF_RANGE_MASK & 0xffff);
 298    pci_set_long(conf + PCI_PREF_BASE_UPPER32, 0);
 299    pci_set_long(conf + PCI_PREF_LIMIT_UPPER32, 0);
 300}
 301
 302/* reset bridge specific configuration registers */
 303void pci_bridge_reset(DeviceState *qdev)
 304{
 305    PCIDevice *dev = PCI_DEVICE(qdev);
 306    uint8_t *conf = dev->config;
 307
 308    conf[PCI_PRIMARY_BUS] = 0;
 309    conf[PCI_SECONDARY_BUS] = 0;
 310    conf[PCI_SUBORDINATE_BUS] = 0;
 311    conf[PCI_SEC_LATENCY_TIMER] = 0;
 312
 313    /*
 314     * the default values for base/limit registers aren't specified
 315     * in the PCI-to-PCI-bridge spec. So we don't touch them here.
 316     * Each implementation can override it.
 317     * typical implementation does
 318     * zero base/limit registers or
 319     * disable forwarding: pci_bridge_disable_base_limit()
 320     * If disable forwarding is wanted, call pci_bridge_disable_base_limit()
 321     * after this function.
 322     */
 323    pci_byte_test_and_clear_mask(conf + PCI_IO_BASE,
 324                                 PCI_IO_RANGE_MASK & 0xff);
 325    pci_byte_test_and_clear_mask(conf + PCI_IO_LIMIT,
 326                                 PCI_IO_RANGE_MASK & 0xff);
 327    pci_word_test_and_clear_mask(conf + PCI_MEMORY_BASE,
 328                                 PCI_MEMORY_RANGE_MASK & 0xffff);
 329    pci_word_test_and_clear_mask(conf + PCI_MEMORY_LIMIT,
 330                                 PCI_MEMORY_RANGE_MASK & 0xffff);
 331    pci_word_test_and_clear_mask(conf + PCI_PREF_MEMORY_BASE,
 332                                 PCI_PREF_RANGE_MASK & 0xffff);
 333    pci_word_test_and_clear_mask(conf + PCI_PREF_MEMORY_LIMIT,
 334                                 PCI_PREF_RANGE_MASK & 0xffff);
 335    pci_set_long(conf + PCI_PREF_BASE_UPPER32, 0);
 336    pci_set_long(conf + PCI_PREF_LIMIT_UPPER32, 0);
 337
 338    pci_set_word(conf + PCI_BRIDGE_CONTROL, 0);
 339}
 340
 341/* default qdev initialization function for PCI-to-PCI bridge */
 342void pci_bridge_initfn(PCIDevice *dev, const char *typename)
 343{
 344    PCIBus *parent = pci_get_bus(dev);
 345    PCIBridge *br = PCI_BRIDGE(dev);
 346    PCIBus *sec_bus = &br->sec_bus;
 347
 348    pci_word_test_and_set_mask(dev->config + PCI_STATUS,
 349                               PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK);
 350
 351    /*
 352     * TODO: We implement VGA Enable in the Bridge Control Register
 353     * therefore per the PCI to PCI bridge spec we must also implement
 354     * VGA Palette Snooping.  When done, set this bit writable:
 355     *
 356     * pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND,
 357     *                            PCI_COMMAND_VGA_PALETTE);
 358     */
 359
 360    pci_config_set_class(dev->config, PCI_CLASS_BRIDGE_PCI);
 361    dev->config[PCI_HEADER_TYPE] =
 362        (dev->config[PCI_HEADER_TYPE] & PCI_HEADER_TYPE_MULTI_FUNCTION) |
 363        PCI_HEADER_TYPE_BRIDGE;
 364    pci_set_word(dev->config + PCI_SEC_STATUS,
 365                 PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK);
 366
 367    /*
 368     * If we don't specify the name, the bus will be addressed as <id>.0, where
 369     * id is the device id.
 370     * Since PCI Bridge devices have a single bus each, we don't need the index:
 371     * let users address the bus using the device name.
 372     */
 373    if (!br->bus_name && dev->qdev.id && *dev->qdev.id) {
 374            br->bus_name = dev->qdev.id;
 375    }
 376
 377    qbus_init(sec_bus, sizeof(br->sec_bus), typename, DEVICE(dev),
 378              br->bus_name);
 379    sec_bus->parent_dev = dev;
 380    sec_bus->map_irq = br->map_irq ? br->map_irq : pci_swizzle_map_irq_fn;
 381    sec_bus->address_space_mem = &br->address_space_mem;
 382    memory_region_init(&br->address_space_mem, OBJECT(br), "pci_bridge_pci", UINT64_MAX);
 383    sec_bus->address_space_io = &br->address_space_io;
 384    memory_region_init(&br->address_space_io, OBJECT(br), "pci_bridge_io",
 385                       4 * GiB);
 386    br->windows = pci_bridge_region_init(br);
 387    QLIST_INIT(&sec_bus->child);
 388    QLIST_INSERT_HEAD(&parent->child, sec_bus, sibling);
 389}
 390
 391/* default qdev clean up function for PCI-to-PCI bridge */
 392void pci_bridge_exitfn(PCIDevice *pci_dev)
 393{
 394    PCIBridge *s = PCI_BRIDGE(pci_dev);
 395    assert(QLIST_EMPTY(&s->sec_bus.child));
 396    QLIST_REMOVE(&s->sec_bus, sibling);
 397    pci_bridge_region_del(s, s->windows);
 398    pci_bridge_region_cleanup(s, s->windows);
 399    /* object_unparent() is called automatically during device deletion */
 400}
 401
 402/*
 403 * before qdev initialization(qdev_init()), this function sets bus_name and
 404 * map_irq callback which are necessary for pci_bridge_initfn() to
 405 * initialize bus.
 406 */
 407void pci_bridge_map_irq(PCIBridge *br, const char* bus_name,
 408                        pci_map_irq_fn map_irq)
 409{
 410    br->map_irq = map_irq;
 411    br->bus_name = bus_name;
 412}
 413
 414
 415int pci_bridge_qemu_reserve_cap_init(PCIDevice *dev, int cap_offset,
 416                                     PCIResReserve res_reserve, Error **errp)
 417{
 418    if (res_reserve.mem_pref_32 != (uint64_t)-1 &&
 419        res_reserve.mem_pref_64 != (uint64_t)-1) {
 420        error_setg(errp,
 421                   "PCI resource reserve cap: PREF32 and PREF64 conflict");
 422        return -EINVAL;
 423    }
 424
 425    if (res_reserve.mem_non_pref != (uint64_t)-1 &&
 426        res_reserve.mem_non_pref >= 4 * GiB) {
 427        error_setg(errp,
 428                   "PCI resource reserve cap: mem-reserve must be less than 4G");
 429        return -EINVAL;
 430    }
 431
 432    if (res_reserve.mem_pref_32 != (uint64_t)-1 &&
 433        res_reserve.mem_pref_32 >= 4 * GiB) {
 434        error_setg(errp,
 435                   "PCI resource reserve cap: pref32-reserve  must be less than 4G");
 436        return -EINVAL;
 437    }
 438
 439    if (res_reserve.bus == (uint32_t)-1 &&
 440        res_reserve.io == (uint64_t)-1 &&
 441        res_reserve.mem_non_pref == (uint64_t)-1 &&
 442        res_reserve.mem_pref_32 == (uint64_t)-1 &&
 443        res_reserve.mem_pref_64 == (uint64_t)-1) {
 444        return 0;
 445    }
 446
 447    size_t cap_len = sizeof(PCIBridgeQemuCap);
 448    PCIBridgeQemuCap cap = {
 449            .len = cap_len,
 450            .type = REDHAT_PCI_CAP_RESOURCE_RESERVE,
 451            .bus_res = cpu_to_le32(res_reserve.bus),
 452            .io = cpu_to_le64(res_reserve.io),
 453            .mem = cpu_to_le32(res_reserve.mem_non_pref),
 454            .mem_pref_32 = cpu_to_le32(res_reserve.mem_pref_32),
 455            .mem_pref_64 = cpu_to_le64(res_reserve.mem_pref_64)
 456    };
 457
 458    int offset = pci_add_capability(dev, PCI_CAP_ID_VNDR,
 459                                    cap_offset, cap_len, errp);
 460    if (offset < 0) {
 461        return offset;
 462    }
 463
 464    memcpy(dev->config + offset + PCI_CAP_FLAGS,
 465           (char *)&cap + PCI_CAP_FLAGS,
 466           cap_len - PCI_CAP_FLAGS);
 467    return 0;
 468}
 469
 470static const TypeInfo pci_bridge_type_info = {
 471    .name = TYPE_PCI_BRIDGE,
 472    .parent = TYPE_PCI_DEVICE,
 473    .instance_size = sizeof(PCIBridge),
 474    .abstract = true,
 475};
 476
 477static void pci_bridge_register_types(void)
 478{
 479    type_register_static(&pci_bridge_type_info);
 480}
 481
 482type_init(pci_bridge_register_types)
 483