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21#include "qemu/osdep.h"
22#include "hw/pci/pci.h"
23#include "hw/pci/pci_bridge.h"
24#include "hw/pci/pci_host.h"
25#include "hw/qdev-properties.h"
26#include "qemu/module.h"
27#include "hw/pci/pci_bus.h"
28#include "migration/vmstate.h"
29#include "trace.h"
30
31
32
33
34#ifdef DEBUG_PCI
35#define PCI_DPRINTF(fmt, ...) \
36do { printf("pci_host_data: " fmt , ## __VA_ARGS__); } while (0)
37#else
38#define PCI_DPRINTF(fmt, ...)
39#endif
40
41
42
43
44
45
46
47
48
49static inline PCIDevice *pci_dev_find_by_addr(PCIBus *bus, uint32_t addr)
50{
51 uint8_t bus_num = addr >> 16;
52 uint8_t devfn = addr >> 8;
53
54 return pci_find_device(bus, bus_num, devfn);
55}
56
57static void pci_adjust_config_limit(PCIBus *bus, uint32_t *limit)
58{
59 if ((*limit > PCI_CONFIG_SPACE_SIZE) &&
60 !pci_bus_allows_extended_config_space(bus)) {
61 *limit = PCI_CONFIG_SPACE_SIZE;
62 }
63}
64
65void pci_host_config_write_common(PCIDevice *pci_dev, uint32_t addr,
66 uint32_t limit, uint32_t val, uint32_t len)
67{
68 pci_adjust_config_limit(pci_get_bus(pci_dev), &limit);
69 if (limit <= addr) {
70 return;
71 }
72
73 assert(len <= 4);
74
75
76
77 if ((pci_dev->qdev.hotplugged && !pci_get_function_0(pci_dev)) ||
78 !pci_dev->has_power) {
79 return;
80 }
81
82 trace_pci_cfg_write(pci_dev->name, PCI_SLOT(pci_dev->devfn),
83 PCI_FUNC(pci_dev->devfn), addr, val);
84 pci_dev->config_write(pci_dev, addr, val, MIN(len, limit - addr));
85}
86
87uint32_t pci_host_config_read_common(PCIDevice *pci_dev, uint32_t addr,
88 uint32_t limit, uint32_t len)
89{
90 uint32_t ret;
91
92 pci_adjust_config_limit(pci_get_bus(pci_dev), &limit);
93 if (limit <= addr) {
94 return ~0x0;
95 }
96
97 assert(len <= 4);
98
99
100
101 if ((pci_dev->qdev.hotplugged && !pci_get_function_0(pci_dev)) ||
102 !pci_dev->has_power) {
103 return ~0x0;
104 }
105
106 ret = pci_dev->config_read(pci_dev, addr, MIN(len, limit - addr));
107 trace_pci_cfg_read(pci_dev->name, PCI_SLOT(pci_dev->devfn),
108 PCI_FUNC(pci_dev->devfn), addr, ret);
109
110 return ret;
111}
112
113void pci_data_write(PCIBus *s, uint32_t addr, uint32_t val, unsigned len)
114{
115 PCIDevice *pci_dev = pci_dev_find_by_addr(s, addr);
116 uint32_t config_addr = addr & (PCI_CONFIG_SPACE_SIZE - 1);
117
118 if (!pci_dev) {
119 return;
120 }
121
122 pci_host_config_write_common(pci_dev, config_addr, PCI_CONFIG_SPACE_SIZE,
123 val, len);
124}
125
126uint32_t pci_data_read(PCIBus *s, uint32_t addr, unsigned len)
127{
128 PCIDevice *pci_dev = pci_dev_find_by_addr(s, addr);
129 uint32_t config_addr = addr & (PCI_CONFIG_SPACE_SIZE - 1);
130
131 if (!pci_dev) {
132 return ~0x0;
133 }
134
135 return pci_host_config_read_common(pci_dev, config_addr,
136 PCI_CONFIG_SPACE_SIZE, len);
137}
138
139static void pci_host_config_write(void *opaque, hwaddr addr,
140 uint64_t val, unsigned len)
141{
142 PCIHostState *s = opaque;
143
144 PCI_DPRINTF("%s addr " TARGET_FMT_plx " len %d val %"PRIx64"\n",
145 __func__, addr, len, val);
146 if (addr != 0 || len != 4) {
147 return;
148 }
149 s->config_reg = val;
150}
151
152static uint64_t pci_host_config_read(void *opaque, hwaddr addr,
153 unsigned len)
154{
155 PCIHostState *s = opaque;
156 uint32_t val = s->config_reg;
157
158 PCI_DPRINTF("%s addr " TARGET_FMT_plx " len %d val %"PRIx32"\n",
159 __func__, addr, len, val);
160 return val;
161}
162
163static void pci_host_data_write(void *opaque, hwaddr addr,
164 uint64_t val, unsigned len)
165{
166 PCIHostState *s = opaque;
167
168 if (s->config_reg & (1u << 31))
169 pci_data_write(s->bus, s->config_reg | (addr & 3), val, len);
170}
171
172static uint64_t pci_host_data_read(void *opaque,
173 hwaddr addr, unsigned len)
174{
175 PCIHostState *s = opaque;
176
177 if (!(s->config_reg & (1U << 31))) {
178 return 0xffffffff;
179 }
180 return pci_data_read(s->bus, s->config_reg | (addr & 3), len);
181}
182
183const MemoryRegionOps pci_host_conf_le_ops = {
184 .read = pci_host_config_read,
185 .write = pci_host_config_write,
186 .endianness = DEVICE_LITTLE_ENDIAN,
187};
188
189const MemoryRegionOps pci_host_conf_be_ops = {
190 .read = pci_host_config_read,
191 .write = pci_host_config_write,
192 .endianness = DEVICE_BIG_ENDIAN,
193};
194
195const MemoryRegionOps pci_host_data_le_ops = {
196 .read = pci_host_data_read,
197 .write = pci_host_data_write,
198 .endianness = DEVICE_LITTLE_ENDIAN,
199};
200
201const MemoryRegionOps pci_host_data_be_ops = {
202 .read = pci_host_data_read,
203 .write = pci_host_data_write,
204 .endianness = DEVICE_BIG_ENDIAN,
205};
206
207static bool pci_host_needed(void *opaque)
208{
209 PCIHostState *s = opaque;
210 return s->mig_enabled;
211}
212
213const VMStateDescription vmstate_pcihost = {
214 .name = "PCIHost",
215 .needed = pci_host_needed,
216 .version_id = 1,
217 .minimum_version_id = 1,
218 .fields = (VMStateField[]) {
219 VMSTATE_UINT32(config_reg, PCIHostState),
220 VMSTATE_END_OF_LIST()
221 }
222};
223
224static Property pci_host_properties_common[] = {
225 DEFINE_PROP_BOOL("x-config-reg-migration-enabled", PCIHostState,
226 mig_enabled, true),
227 DEFINE_PROP_BOOL("bypass-iommu", PCIHostState, bypass_iommu, false),
228 DEFINE_PROP_END_OF_LIST(),
229};
230
231static void pci_host_class_init(ObjectClass *klass, void *data)
232{
233 DeviceClass *dc = DEVICE_CLASS(klass);
234 device_class_set_props(dc, pci_host_properties_common);
235 dc->vmsd = &vmstate_pcihost;
236}
237
238static const TypeInfo pci_host_type_info = {
239 .name = TYPE_PCI_HOST_BRIDGE,
240 .parent = TYPE_SYS_BUS_DEVICE,
241 .abstract = true,
242 .class_size = sizeof(PCIHostBridgeClass),
243 .instance_size = sizeof(PCIHostState),
244 .class_init = pci_host_class_init,
245};
246
247static void pci_host_register_types(void)
248{
249 type_register_static(&pci_host_type_info);
250}
251
252type_init(pci_host_register_types)
253