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22#include "qemu/osdep.h"
23#include "hw/irq.h"
24#include "hw/ppc/ppc.h"
25#include "hw/ppc/ppc4xx.h"
26#include "migration/vmstate.h"
27#include "qemu/module.h"
28#include "sysemu/reset.h"
29#include "hw/pci/pci.h"
30#include "hw/pci/pci_host.h"
31#include "trace.h"
32#include "qom/object.h"
33
34struct PCIMasterMap {
35 uint32_t la;
36 uint32_t ma;
37 uint32_t pcila;
38 uint32_t pciha;
39};
40
41struct PCITargetMap {
42 uint32_t ms;
43 uint32_t la;
44};
45
46OBJECT_DECLARE_SIMPLE_TYPE(PPC4xxPCIState, PPC4xx_PCI_HOST_BRIDGE)
47
48#define PPC4xx_PCI_NR_PMMS 3
49#define PPC4xx_PCI_NR_PTMS 2
50
51#define PPC4xx_PCI_NUM_DEVS 5
52
53struct PPC4xxPCIState {
54 PCIHostState parent_obj;
55
56 struct PCIMasterMap pmm[PPC4xx_PCI_NR_PMMS];
57 struct PCITargetMap ptm[PPC4xx_PCI_NR_PTMS];
58 qemu_irq irq[PPC4xx_PCI_NUM_DEVS];
59
60 MemoryRegion container;
61 MemoryRegion iomem;
62};
63
64#define PCIC0_CFGADDR 0x0
65#define PCIC0_CFGDATA 0x4
66
67
68
69#define PCIL0_PMM0LA 0x0
70#define PCIL0_PMM0MA 0x4
71#define PCIL0_PMM0PCILA 0x8
72#define PCIL0_PMM0PCIHA 0xc
73#define PCIL0_PMM1LA 0x10
74#define PCIL0_PMM1MA 0x14
75#define PCIL0_PMM1PCILA 0x18
76#define PCIL0_PMM1PCIHA 0x1c
77#define PCIL0_PMM2LA 0x20
78#define PCIL0_PMM2MA 0x24
79#define PCIL0_PMM2PCILA 0x28
80#define PCIL0_PMM2PCIHA 0x2c
81
82
83
84#define PCIL0_PTM1MS 0x30
85#define PCIL0_PTM1LA 0x34
86#define PCIL0_PTM2MS 0x38
87#define PCIL0_PTM2LA 0x3c
88#define PCI_REG_BASE 0x800000
89#define PCI_REG_SIZE 0x40
90
91#define PCI_ALL_SIZE (PCI_REG_BASE + PCI_REG_SIZE)
92
93static void ppc4xx_pci_reg_write4(void *opaque, hwaddr offset,
94 uint64_t value, unsigned size)
95{
96 struct PPC4xxPCIState *pci = opaque;
97
98
99
100
101 switch (offset) {
102 case PCIL0_PMM0LA:
103 pci->pmm[0].la = value;
104 break;
105 case PCIL0_PMM0MA:
106 pci->pmm[0].ma = value;
107 break;
108 case PCIL0_PMM0PCIHA:
109 pci->pmm[0].pciha = value;
110 break;
111 case PCIL0_PMM0PCILA:
112 pci->pmm[0].pcila = value;
113 break;
114
115 case PCIL0_PMM1LA:
116 pci->pmm[1].la = value;
117 break;
118 case PCIL0_PMM1MA:
119 pci->pmm[1].ma = value;
120 break;
121 case PCIL0_PMM1PCIHA:
122 pci->pmm[1].pciha = value;
123 break;
124 case PCIL0_PMM1PCILA:
125 pci->pmm[1].pcila = value;
126 break;
127
128 case PCIL0_PMM2LA:
129 pci->pmm[2].la = value;
130 break;
131 case PCIL0_PMM2MA:
132 pci->pmm[2].ma = value;
133 break;
134 case PCIL0_PMM2PCIHA:
135 pci->pmm[2].pciha = value;
136 break;
137 case PCIL0_PMM2PCILA:
138 pci->pmm[2].pcila = value;
139 break;
140
141 case PCIL0_PTM1MS:
142 pci->ptm[0].ms = value;
143 break;
144 case PCIL0_PTM1LA:
145 pci->ptm[0].la = value;
146 break;
147 case PCIL0_PTM2MS:
148 pci->ptm[1].ms = value;
149 break;
150 case PCIL0_PTM2LA:
151 pci->ptm[1].la = value;
152 break;
153
154 default:
155 printf("%s: unhandled PCI internal register 0x%lx\n", __func__,
156 (unsigned long)offset);
157 break;
158 }
159}
160
161static uint64_t ppc4xx_pci_reg_read4(void *opaque, hwaddr offset,
162 unsigned size)
163{
164 struct PPC4xxPCIState *pci = opaque;
165 uint32_t value;
166
167 switch (offset) {
168 case PCIL0_PMM0LA:
169 value = pci->pmm[0].la;
170 break;
171 case PCIL0_PMM0MA:
172 value = pci->pmm[0].ma;
173 break;
174 case PCIL0_PMM0PCIHA:
175 value = pci->pmm[0].pciha;
176 break;
177 case PCIL0_PMM0PCILA:
178 value = pci->pmm[0].pcila;
179 break;
180
181 case PCIL0_PMM1LA:
182 value = pci->pmm[1].la;
183 break;
184 case PCIL0_PMM1MA:
185 value = pci->pmm[1].ma;
186 break;
187 case PCIL0_PMM1PCIHA:
188 value = pci->pmm[1].pciha;
189 break;
190 case PCIL0_PMM1PCILA:
191 value = pci->pmm[1].pcila;
192 break;
193
194 case PCIL0_PMM2LA:
195 value = pci->pmm[2].la;
196 break;
197 case PCIL0_PMM2MA:
198 value = pci->pmm[2].ma;
199 break;
200 case PCIL0_PMM2PCIHA:
201 value = pci->pmm[2].pciha;
202 break;
203 case PCIL0_PMM2PCILA:
204 value = pci->pmm[2].pcila;
205 break;
206
207 case PCIL0_PTM1MS:
208 value = pci->ptm[0].ms;
209 break;
210 case PCIL0_PTM1LA:
211 value = pci->ptm[0].la;
212 break;
213 case PCIL0_PTM2MS:
214 value = pci->ptm[1].ms;
215 break;
216 case PCIL0_PTM2LA:
217 value = pci->ptm[1].la;
218 break;
219
220 default:
221 printf("%s: invalid PCI internal register 0x%lx\n", __func__,
222 (unsigned long)offset);
223 value = 0;
224 }
225
226 return value;
227}
228
229static const MemoryRegionOps pci_reg_ops = {
230 .read = ppc4xx_pci_reg_read4,
231 .write = ppc4xx_pci_reg_write4,
232 .endianness = DEVICE_LITTLE_ENDIAN,
233};
234
235static void ppc4xx_pci_reset(void *opaque)
236{
237 struct PPC4xxPCIState *pci = opaque;
238
239 memset(pci->pmm, 0, sizeof(pci->pmm));
240 memset(pci->ptm, 0, sizeof(pci->ptm));
241}
242
243
244
245static int ppc4xx_pci_map_irq(PCIDevice *pci_dev, int irq_num)
246{
247 int slot = PCI_SLOT(pci_dev->devfn);
248
249 trace_ppc4xx_pci_map_irq(pci_dev->devfn, irq_num, slot);
250
251 return slot > 0 ? slot - 1 : PPC4xx_PCI_NUM_DEVS - 1;
252}
253
254static void ppc4xx_pci_set_irq(void *opaque, int irq_num, int level)
255{
256 qemu_irq *pci_irqs = opaque;
257
258 trace_ppc4xx_pci_set_irq(irq_num);
259 assert(irq_num >= 0 && irq_num < PPC4xx_PCI_NUM_DEVS);
260 qemu_set_irq(pci_irqs[irq_num], level);
261}
262
263static const VMStateDescription vmstate_pci_master_map = {
264 .name = "pci_master_map",
265 .version_id = 0,
266 .minimum_version_id = 0,
267 .fields = (VMStateField[]) {
268 VMSTATE_UINT32(la, struct PCIMasterMap),
269 VMSTATE_UINT32(ma, struct PCIMasterMap),
270 VMSTATE_UINT32(pcila, struct PCIMasterMap),
271 VMSTATE_UINT32(pciha, struct PCIMasterMap),
272 VMSTATE_END_OF_LIST()
273 }
274};
275
276static const VMStateDescription vmstate_pci_target_map = {
277 .name = "pci_target_map",
278 .version_id = 0,
279 .minimum_version_id = 0,
280 .fields = (VMStateField[]) {
281 VMSTATE_UINT32(ms, struct PCITargetMap),
282 VMSTATE_UINT32(la, struct PCITargetMap),
283 VMSTATE_END_OF_LIST()
284 }
285};
286
287static const VMStateDescription vmstate_ppc4xx_pci = {
288 .name = "ppc4xx_pci",
289 .version_id = 1,
290 .minimum_version_id = 1,
291 .fields = (VMStateField[]) {
292 VMSTATE_STRUCT_ARRAY(pmm, PPC4xxPCIState, PPC4xx_PCI_NR_PMMS, 1,
293 vmstate_pci_master_map,
294 struct PCIMasterMap),
295 VMSTATE_STRUCT_ARRAY(ptm, PPC4xxPCIState, PPC4xx_PCI_NR_PTMS, 1,
296 vmstate_pci_target_map,
297 struct PCITargetMap),
298 VMSTATE_END_OF_LIST()
299 }
300};
301
302
303static void ppc4xx_pcihost_realize(DeviceState *dev, Error **errp)
304{
305 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
306 PPC4xxPCIState *s;
307 PCIHostState *h;
308 PCIBus *b;
309 int i;
310
311 h = PCI_HOST_BRIDGE(dev);
312 s = PPC4xx_PCI_HOST_BRIDGE(dev);
313
314 for (i = 0; i < ARRAY_SIZE(s->irq); i++) {
315 sysbus_init_irq(sbd, &s->irq[i]);
316 }
317
318 b = pci_register_root_bus(dev, NULL, ppc4xx_pci_set_irq,
319 ppc4xx_pci_map_irq, s->irq, get_system_memory(),
320 get_system_io(), 0, ARRAY_SIZE(s->irq),
321 TYPE_PCI_BUS);
322 h->bus = b;
323
324 pci_create_simple(b, 0, "ppc4xx-host-bridge");
325
326
327 memory_region_init(&s->container, OBJECT(s), "pci-container", PCI_ALL_SIZE);
328 memory_region_init_io(&h->conf_mem, OBJECT(s), &pci_host_conf_le_ops, h,
329 "pci-conf-idx", 4);
330 memory_region_init_io(&h->data_mem, OBJECT(s), &pci_host_data_le_ops, h,
331 "pci-conf-data", 4);
332 memory_region_init_io(&s->iomem, OBJECT(s), &pci_reg_ops, s,
333 "pci.reg", PCI_REG_SIZE);
334 memory_region_add_subregion(&s->container, PCIC0_CFGADDR, &h->conf_mem);
335 memory_region_add_subregion(&s->container, PCIC0_CFGDATA, &h->data_mem);
336 memory_region_add_subregion(&s->container, PCI_REG_BASE, &s->iomem);
337 sysbus_init_mmio(sbd, &s->container);
338 qemu_register_reset(ppc4xx_pci_reset, s);
339}
340
341static void ppc4xx_host_bridge_class_init(ObjectClass *klass, void *data)
342{
343 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
344 DeviceClass *dc = DEVICE_CLASS(klass);
345
346 dc->desc = "Host bridge";
347 k->vendor_id = PCI_VENDOR_ID_IBM;
348 k->device_id = PCI_DEVICE_ID_IBM_440GX;
349 k->class_id = PCI_CLASS_BRIDGE_OTHER;
350
351
352
353
354 dc->user_creatable = false;
355}
356
357static const TypeInfo ppc4xx_host_bridge_info = {
358 .name = "ppc4xx-host-bridge",
359 .parent = TYPE_PCI_DEVICE,
360 .instance_size = sizeof(PCIDevice),
361 .class_init = ppc4xx_host_bridge_class_init,
362 .interfaces = (InterfaceInfo[]) {
363 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
364 { },
365 },
366};
367
368static void ppc4xx_pcihost_class_init(ObjectClass *klass, void *data)
369{
370 DeviceClass *dc = DEVICE_CLASS(klass);
371
372 dc->realize = ppc4xx_pcihost_realize;
373 dc->vmsd = &vmstate_ppc4xx_pci;
374}
375
376static const TypeInfo ppc4xx_pcihost_info = {
377 .name = TYPE_PPC4xx_PCI_HOST_BRIDGE,
378 .parent = TYPE_PCI_HOST_BRIDGE,
379 .instance_size = sizeof(PPC4xxPCIState),
380 .class_init = ppc4xx_pcihost_class_init,
381};
382
383static void ppc4xx_pci_register_types(void)
384{
385 type_register_static(&ppc4xx_pcihost_info);
386 type_register_static(&ppc4xx_host_bridge_info);
387}
388
389type_init(ppc4xx_pci_register_types)
390
