1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26#include "qemu/osdep.h"
27#include "hw/rtc/m48t59.h"
28#include "hw/char/serial.h"
29#include "hw/block/fdc.h"
30#include "net/net.h"
31#include "hw/isa/isa.h"
32#include "hw/pci/pci.h"
33#include "hw/pci/pci_host.h"
34#include "hw/ppc/ppc.h"
35#include "hw/boards.h"
36#include "qapi/error.h"
37#include "qemu/error-report.h"
38#include "qemu/log.h"
39#include "hw/loader.h"
40#include "hw/rtc/mc146818rtc.h"
41#include "hw/isa/pc87312.h"
42#include "hw/qdev-properties.h"
43#include "sysemu/kvm.h"
44#include "sysemu/reset.h"
45#include "trace.h"
46#include "elf.h"
47#include "qemu/units.h"
48#include "kvm_ppc.h"
49
50
51#define MAX_CPUS 1
52
53#define MAX_IDE_BUS 2
54
55#define CFG_ADDR 0xf0000510
56
57#define KERNEL_LOAD_ADDR 0x01000000
58#define INITRD_LOAD_ADDR 0x01800000
59
60#define NVRAM_SIZE 0x2000
61
62static void fw_cfg_boot_set(void *opaque, const char *boot_device,
63 Error **errp)
64{
65 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
66}
67
68static void ppc_prep_reset(void *opaque)
69{
70 PowerPCCPU *cpu = opaque;
71
72 cpu_reset(CPU(cpu));
73}
74
75
76
77
78static inline uint32_t nvram_read(Nvram *nvram, uint32_t addr)
79{
80 NvramClass *k = NVRAM_GET_CLASS(nvram);
81 return (k->read)(nvram, addr);
82}
83
84static inline void nvram_write(Nvram *nvram, uint32_t addr, uint32_t val)
85{
86 NvramClass *k = NVRAM_GET_CLASS(nvram);
87 (k->write)(nvram, addr, val);
88}
89
90static void NVRAM_set_byte(Nvram *nvram, uint32_t addr, uint8_t value)
91{
92 nvram_write(nvram, addr, value);
93}
94
95static uint8_t NVRAM_get_byte(Nvram *nvram, uint32_t addr)
96{
97 return nvram_read(nvram, addr);
98}
99
100static void NVRAM_set_word(Nvram *nvram, uint32_t addr, uint16_t value)
101{
102 nvram_write(nvram, addr, value >> 8);
103 nvram_write(nvram, addr + 1, value & 0xFF);
104}
105
106static uint16_t NVRAM_get_word(Nvram *nvram, uint32_t addr)
107{
108 uint16_t tmp;
109
110 tmp = nvram_read(nvram, addr) << 8;
111 tmp |= nvram_read(nvram, addr + 1);
112
113 return tmp;
114}
115
116static void NVRAM_set_lword(Nvram *nvram, uint32_t addr, uint32_t value)
117{
118 nvram_write(nvram, addr, value >> 24);
119 nvram_write(nvram, addr + 1, (value >> 16) & 0xFF);
120 nvram_write(nvram, addr + 2, (value >> 8) & 0xFF);
121 nvram_write(nvram, addr + 3, value & 0xFF);
122}
123
124static void NVRAM_set_string(Nvram *nvram, uint32_t addr, const char *str,
125 uint32_t max)
126{
127 int i;
128
129 for (i = 0; i < max && str[i] != '\0'; i++) {
130 nvram_write(nvram, addr + i, str[i]);
131 }
132 nvram_write(nvram, addr + i, str[i]);
133 nvram_write(nvram, addr + max - 1, '\0');
134}
135
136static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value)
137{
138 uint16_t tmp;
139 uint16_t pd, pd1, pd2;
140
141 tmp = prev >> 8;
142 pd = prev ^ value;
143 pd1 = pd & 0x000F;
144 pd2 = ((pd >> 4) & 0x000F) ^ pd1;
145 tmp ^= (pd1 << 3) | (pd1 << 8);
146 tmp ^= pd2 | (pd2 << 7) | (pd2 << 12);
147
148 return tmp;
149}
150
151static uint16_t NVRAM_compute_crc (Nvram *nvram, uint32_t start, uint32_t count)
152{
153 uint32_t i;
154 uint16_t crc = 0xFFFF;
155 int odd;
156
157 odd = count & 1;
158 count &= ~1;
159 for (i = 0; i != count; i++) {
160 crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i));
161 }
162 if (odd) {
163 crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8);
164 }
165
166 return crc;
167}
168
169#define CMDLINE_ADDR 0x017ff000
170
171static int PPC_NVRAM_set_params (Nvram *nvram, uint16_t NVRAM_size,
172 const char *arch,
173 uint32_t RAM_size, int boot_device,
174 uint32_t kernel_image, uint32_t kernel_size,
175 const char *cmdline,
176 uint32_t initrd_image, uint32_t initrd_size,
177 uint32_t NVRAM_image,
178 int width, int height, int depth)
179{
180 uint16_t crc;
181
182
183 NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16);
184 NVRAM_set_lword(nvram, 0x10, 0x00000002);
185 NVRAM_set_word(nvram, 0x14, NVRAM_size);
186 NVRAM_set_string(nvram, 0x20, arch, 16);
187 NVRAM_set_lword(nvram, 0x30, RAM_size);
188 NVRAM_set_byte(nvram, 0x34, boot_device);
189 NVRAM_set_lword(nvram, 0x38, kernel_image);
190 NVRAM_set_lword(nvram, 0x3C, kernel_size);
191 if (cmdline) {
192
193 pstrcpy_targphys("cmdline", CMDLINE_ADDR, RAM_size - CMDLINE_ADDR,
194 cmdline);
195 NVRAM_set_lword(nvram, 0x40, CMDLINE_ADDR);
196 NVRAM_set_lword(nvram, 0x44, strlen(cmdline));
197 } else {
198 NVRAM_set_lword(nvram, 0x40, 0);
199 NVRAM_set_lword(nvram, 0x44, 0);
200 }
201 NVRAM_set_lword(nvram, 0x48, initrd_image);
202 NVRAM_set_lword(nvram, 0x4C, initrd_size);
203 NVRAM_set_lword(nvram, 0x50, NVRAM_image);
204
205 NVRAM_set_word(nvram, 0x54, width);
206 NVRAM_set_word(nvram, 0x56, height);
207 NVRAM_set_word(nvram, 0x58, depth);
208 crc = NVRAM_compute_crc(nvram, 0x00, 0xF8);
209 NVRAM_set_word(nvram, 0xFC, crc);
210
211 return 0;
212}
213
214static int prep_set_cmos_checksum(DeviceState *dev, void *opaque)
215{
216 uint16_t checksum = *(uint16_t *)opaque;
217 ISADevice *rtc;
218
219 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) {
220 rtc = ISA_DEVICE(dev);
221 rtc_set_memory(rtc, 0x2e, checksum & 0xff);
222 rtc_set_memory(rtc, 0x3e, checksum & 0xff);
223 rtc_set_memory(rtc, 0x2f, checksum >> 8);
224 rtc_set_memory(rtc, 0x3f, checksum >> 8);
225
226 object_property_add_alias(qdev_get_machine(), "rtc-time", OBJECT(rtc),
227 "date");
228 }
229 return 0;
230}
231
232static void ibm_40p_init(MachineState *machine)
233{
234 const char *bios_name = machine->firmware ?: "openbios-ppc";
235 CPUPPCState *env = NULL;
236 uint16_t cmos_checksum;
237 PowerPCCPU *cpu;
238 DeviceState *dev, *i82378_dev;
239 SysBusDevice *pcihost, *s;
240 Nvram *m48t59 = NULL;
241 PCIBus *pci_bus;
242 ISADevice *isa_dev;
243 ISABus *isa_bus;
244 void *fw_cfg;
245 int i;
246 uint32_t kernel_base = 0, initrd_base = 0;
247 long kernel_size = 0, initrd_size = 0;
248 char boot_device;
249
250
251 cpu = POWERPC_CPU(cpu_create(machine->cpu_type));
252 env = &cpu->env;
253 if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
254 error_report("only 6xx bus is supported on this machine");
255 exit(1);
256 }
257
258 if (env->flags & POWERPC_FLAG_RTC_CLK) {
259
260 cpu_ppc_tb_init(env, 7812500UL);
261 } else {
262
263 cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
264 }
265 qemu_register_reset(ppc_prep_reset, cpu);
266
267
268 dev = qdev_new("raven-pcihost");
269 qdev_prop_set_string(dev, "bios-name", bios_name);
270 qdev_prop_set_uint32(dev, "elf-machine", PPC_ELF_MACHINE);
271 pcihost = SYS_BUS_DEVICE(dev);
272 object_property_add_child(qdev_get_machine(), "raven", OBJECT(dev));
273 sysbus_realize_and_unref(pcihost, &error_fatal);
274 pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci.0"));
275 if (!pci_bus) {
276 error_report("could not create PCI host controller");
277 exit(1);
278 }
279
280
281 i82378_dev = DEVICE(pci_create_simple(pci_bus, PCI_DEVFN(11, 0), "i82378"));
282 qdev_connect_gpio_out(i82378_dev, 0,
283 cpu->env.irq_inputs[PPC6xx_INPUT_INT]);
284 sysbus_connect_irq(pcihost, 0, qdev_get_gpio_in(i82378_dev, 15));
285 isa_bus = ISA_BUS(qdev_get_child_bus(i82378_dev, "isa.0"));
286
287
288 isa_dev = isa_new("rs6000-mc");
289 dev = DEVICE(isa_dev);
290 qdev_prop_set_uint32(dev, "ram-size", machine->ram_size);
291 isa_realize_and_unref(isa_dev, isa_bus, &error_fatal);
292
293
294 isa_dev = isa_new(TYPE_MC146818_RTC);
295 dev = DEVICE(isa_dev);
296 qdev_prop_set_int32(dev, "base_year", 1900);
297 isa_realize_and_unref(isa_dev, isa_bus, &error_fatal);
298
299
300 cmos_checksum = 0x6aa9;
301 qbus_walk_children(BUS(isa_bus), prep_set_cmos_checksum, NULL, NULL, NULL,
302 &cmos_checksum);
303
304
305 if (defaults_enabled()) {
306 m48t59 = NVRAM(isa_create_simple(isa_bus, "isa-m48t59"));
307
308 isa_dev = isa_new("cs4231a");
309 dev = DEVICE(isa_dev);
310 qdev_prop_set_uint32(dev, "iobase", 0x830);
311 qdev_prop_set_uint32(dev, "irq", 10);
312 isa_realize_and_unref(isa_dev, isa_bus, &error_fatal);
313
314 isa_dev = isa_new("pc87312");
315 dev = DEVICE(isa_dev);
316 qdev_prop_set_uint32(dev, "config", 12);
317 isa_realize_and_unref(isa_dev, isa_bus, &error_fatal);
318
319 isa_dev = isa_new("prep-systemio");
320 dev = DEVICE(isa_dev);
321 qdev_prop_set_uint32(dev, "ibm-planar-id", 0xfc);
322 qdev_prop_set_uint32(dev, "equipment", 0xc0);
323 isa_realize_and_unref(isa_dev, isa_bus, &error_fatal);
324
325 dev = DEVICE(pci_create_simple(pci_bus, PCI_DEVFN(1, 0),
326 "lsi53c810"));
327 lsi53c8xx_handle_legacy_cmdline(dev);
328 qdev_connect_gpio_out(dev, 0, qdev_get_gpio_in(i82378_dev, 13));
329
330
331 pci_vga_init(pci_bus);
332
333 for (i = 0; i < nb_nics; i++) {
334 pci_nic_init_nofail(&nd_table[i], pci_bus, "pcnet",
335 i == 0 ? "3" : NULL);
336 }
337 }
338
339
340 dev = qdev_new(TYPE_FW_CFG_MEM);
341 fw_cfg = FW_CFG(dev);
342 qdev_prop_set_uint32(dev, "data_width", 1);
343 qdev_prop_set_bit(dev, "dma_enabled", false);
344 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG,
345 OBJECT(fw_cfg));
346 s = SYS_BUS_DEVICE(dev);
347 sysbus_realize_and_unref(s, &error_fatal);
348 sysbus_mmio_map(s, 0, CFG_ADDR);
349 sysbus_mmio_map(s, 1, CFG_ADDR + 2);
350
351 if (machine->kernel_filename) {
352
353 kernel_base = KERNEL_LOAD_ADDR;
354 kernel_size = load_image_targphys(machine->kernel_filename,
355 kernel_base,
356 machine->ram_size - kernel_base);
357 if (kernel_size < 0) {
358 error_report("could not load kernel '%s'",
359 machine->kernel_filename);
360 exit(1);
361 }
362 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base);
363 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
364
365 if (machine->initrd_filename) {
366 initrd_base = INITRD_LOAD_ADDR;
367 initrd_size = load_image_targphys(machine->initrd_filename,
368 initrd_base,
369 machine->ram_size - initrd_base);
370 if (initrd_size < 0) {
371 error_report("could not load initial ram disk '%s'",
372 machine->initrd_filename);
373 exit(1);
374 }
375 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base);
376 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
377 }
378 if (machine->kernel_cmdline && *machine->kernel_cmdline) {
379 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
380 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE,
381 machine->kernel_cmdline);
382 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA,
383 machine->kernel_cmdline);
384 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
385 strlen(machine->kernel_cmdline) + 1);
386 }
387 boot_device = 'm';
388 } else {
389 boot_device = machine->boot_order[0];
390 }
391
392 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)machine->smp.max_cpus);
393 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size);
394 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_PREP);
395
396 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width);
397 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height);
398 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth);
399
400 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled());
401 if (kvm_enabled()) {
402 uint8_t *hypercall;
403
404 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, kvmppc_get_tbfreq());
405 hypercall = g_malloc(16);
406 kvmppc_get_hypercall(env, hypercall, 16);
407 fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16);
408 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid());
409 } else {
410 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, NANOSECONDS_PER_SECOND);
411 }
412 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device);
413 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
414
415
416 if (m48t59) {
417 PPC_NVRAM_set_params(m48t59, NVRAM_SIZE, "PREP", machine->ram_size,
418 boot_device,
419 kernel_base, kernel_size,
420 machine->kernel_cmdline,
421 initrd_base, initrd_size,
422
423 0,
424 graphic_width, graphic_height, graphic_depth);
425 }
426}
427
428static void ibm_40p_machine_init(MachineClass *mc)
429{
430 mc->desc = "IBM RS/6000 7020 (40p)",
431 mc->init = ibm_40p_init;
432 mc->max_cpus = 1;
433 mc->default_ram_size = 128 * MiB;
434 mc->block_default_type = IF_SCSI;
435 mc->default_boot_order = "c";
436 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("604");
437 mc->default_display = "std";
438}
439
440DEFINE_MACHINE("40p", ibm_40p_machine_init)
441
