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20#include "qemu/osdep.h"
21#include "qemu-common.h"
22#include "qemu/datadir.h"
23#include "qemu/units.h"
24#include "qemu/error-report.h"
25#include "exec/cpu-defs.h"
26#include "hw/boards.h"
27#include "hw/loader.h"
28#include "hw/riscv/boot.h"
29#include "hw/riscv/boot_opensbi.h"
30#include "elf.h"
31#include "sysemu/device_tree.h"
32#include "sysemu/qtest.h"
33
34#include <libfdt.h>
35
36bool riscv_is_32bit(RISCVHartArrayState *harts)
37{
38 return harts->harts[0].env.misa_mxl_max == MXL_RV32;
39}
40
41
42
43
44
45char *riscv_plic_hart_config_string(int hart_count)
46{
47 g_autofree const char **vals = g_new(const char *, hart_count + 1);
48 int i;
49
50 for (i = 0; i < hart_count; i++) {
51 CPUState *cs = qemu_get_cpu(i);
52 CPURISCVState *env = &RISCV_CPU(cs)->env;
53
54 if (riscv_has_ext(env, RVS)) {
55 vals[i] = "MS";
56 } else {
57 vals[i] = "M";
58 }
59 }
60 vals[i] = NULL;
61
62
63 return g_strjoinv(",", (char **)vals);
64}
65
66target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts,
67 target_ulong firmware_end_addr) {
68 if (riscv_is_32bit(harts)) {
69 return QEMU_ALIGN_UP(firmware_end_addr, 4 * MiB);
70 } else {
71 return QEMU_ALIGN_UP(firmware_end_addr, 2 * MiB);
72 }
73}
74
75target_ulong riscv_find_and_load_firmware(MachineState *machine,
76 const char *default_machine_firmware,
77 hwaddr firmware_load_addr,
78 symbol_fn_t sym_cb)
79{
80 char *firmware_filename = NULL;
81 target_ulong firmware_end_addr = firmware_load_addr;
82
83 if ((!machine->firmware) || (!strcmp(machine->firmware, "default"))) {
84
85
86
87
88
89 firmware_filename = riscv_find_firmware(default_machine_firmware);
90 } else if (strcmp(machine->firmware, "none")) {
91 firmware_filename = riscv_find_firmware(machine->firmware);
92 }
93
94 if (firmware_filename) {
95
96 firmware_end_addr = riscv_load_firmware(firmware_filename,
97 firmware_load_addr, sym_cb);
98 g_free(firmware_filename);
99 }
100
101 return firmware_end_addr;
102}
103
104char *riscv_find_firmware(const char *firmware_filename)
105{
106 char *filename;
107
108 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, firmware_filename);
109 if (filename == NULL) {
110 if (!qtest_enabled()) {
111
112
113
114
115
116
117 error_report("Unable to load the RISC-V firmware \"%s\"",
118 firmware_filename);
119 exit(1);
120 }
121 }
122
123 return filename;
124}
125
126target_ulong riscv_load_firmware(const char *firmware_filename,
127 hwaddr firmware_load_addr,
128 symbol_fn_t sym_cb)
129{
130 uint64_t firmware_entry, firmware_size, firmware_end;
131
132 if (load_elf_ram_sym(firmware_filename, NULL, NULL, NULL,
133 &firmware_entry, NULL, &firmware_end, NULL,
134 0, EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) {
135 return firmware_end;
136 }
137
138 firmware_size = load_image_targphys_as(firmware_filename,
139 firmware_load_addr,
140 current_machine->ram_size, NULL);
141
142 if (firmware_size > 0) {
143 return firmware_load_addr + firmware_size;
144 }
145
146 error_report("could not load firmware '%s'", firmware_filename);
147 exit(1);
148}
149
150target_ulong riscv_load_kernel(const char *kernel_filename,
151 target_ulong kernel_start_addr,
152 symbol_fn_t sym_cb)
153{
154 uint64_t kernel_entry;
155
156 if (load_elf_ram_sym(kernel_filename, NULL, NULL, NULL,
157 &kernel_entry, NULL, NULL, NULL, 0,
158 EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) {
159 return kernel_entry;
160 }
161
162 if (load_uimage_as(kernel_filename, &kernel_entry, NULL, NULL,
163 NULL, NULL, NULL) > 0) {
164 return kernel_entry;
165 }
166
167 if (load_image_targphys_as(kernel_filename, kernel_start_addr,
168 current_machine->ram_size, NULL) > 0) {
169 return kernel_start_addr;
170 }
171
172 error_report("could not load kernel '%s'", kernel_filename);
173 exit(1);
174}
175
176hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size,
177 uint64_t kernel_entry, hwaddr *start)
178{
179 int size;
180
181
182
183
184
185
186
187
188
189
190
191
192 *start = kernel_entry + MIN(mem_size / 2, 128 * MiB);
193
194 size = load_ramdisk(filename, *start, mem_size - *start);
195 if (size == -1) {
196 size = load_image_targphys(filename, *start, mem_size - *start);
197 if (size == -1) {
198 error_report("could not load ramdisk '%s'", filename);
199 exit(1);
200 }
201 }
202
203 return *start + size;
204}
205
206uint32_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt)
207{
208 uint32_t temp, fdt_addr;
209 hwaddr dram_end = dram_base + mem_size;
210 int ret, fdtsize = fdt_totalsize(fdt);
211
212 if (fdtsize <= 0) {
213 error_report("invalid device-tree");
214 exit(1);
215 }
216
217
218
219
220
221
222
223 temp = MIN(dram_end, 3072 * MiB);
224 fdt_addr = QEMU_ALIGN_DOWN(temp - fdtsize, 16 * MiB);
225
226 ret = fdt_pack(fdt);
227
228 g_assert(ret == 0);
229
230 qemu_fdt_dumpdtb(fdt, fdtsize);
231
232 rom_add_blob_fixed_as("fdt", fdt, fdtsize, fdt_addr,
233 &address_space_memory);
234
235 return fdt_addr;
236}
237
238void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base,
239 hwaddr rom_size, uint32_t reset_vec_size,
240 uint64_t kernel_entry)
241{
242 struct fw_dynamic_info dinfo;
243 size_t dinfo_len;
244
245 if (sizeof(dinfo.magic) == 4) {
246 dinfo.magic = cpu_to_le32(FW_DYNAMIC_INFO_MAGIC_VALUE);
247 dinfo.version = cpu_to_le32(FW_DYNAMIC_INFO_VERSION);
248 dinfo.next_mode = cpu_to_le32(FW_DYNAMIC_INFO_NEXT_MODE_S);
249 dinfo.next_addr = cpu_to_le32(kernel_entry);
250 } else {
251 dinfo.magic = cpu_to_le64(FW_DYNAMIC_INFO_MAGIC_VALUE);
252 dinfo.version = cpu_to_le64(FW_DYNAMIC_INFO_VERSION);
253 dinfo.next_mode = cpu_to_le64(FW_DYNAMIC_INFO_NEXT_MODE_S);
254 dinfo.next_addr = cpu_to_le64(kernel_entry);
255 }
256 dinfo.options = 0;
257 dinfo.boot_hart = 0;
258 dinfo_len = sizeof(dinfo);
259
260
261
262
263
264
265 if (dinfo_len > (rom_size - reset_vec_size)) {
266 error_report("not enough space to store dynamic firmware info");
267 exit(1);
268 }
269
270 rom_add_blob_fixed_as("mrom.finfo", &dinfo, dinfo_len,
271 rom_base + reset_vec_size,
272 &address_space_memory);
273}
274
275void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts,
276 hwaddr start_addr,
277 hwaddr rom_base, hwaddr rom_size,
278 uint64_t kernel_entry,
279 uint32_t fdt_load_addr, void *fdt)
280{
281 int i;
282 uint32_t start_addr_hi32 = 0x00000000;
283
284 if (!riscv_is_32bit(harts)) {
285 start_addr_hi32 = start_addr >> 32;
286 }
287
288 uint32_t reset_vec[10] = {
289 0x00000297,
290 0x02828613,
291 0xf1402573,
292 0,
293 0,
294 0x00028067,
295 start_addr,
296 start_addr_hi32,
297 fdt_load_addr,
298 0x00000000,
299
300 };
301 if (riscv_is_32bit(harts)) {
302 reset_vec[3] = 0x0202a583;
303 reset_vec[4] = 0x0182a283;
304 } else {
305 reset_vec[3] = 0x0202b583;
306 reset_vec[4] = 0x0182b283;
307 }
308
309
310 for (i = 0; i < ARRAY_SIZE(reset_vec); i++) {
311 reset_vec[i] = cpu_to_le32(reset_vec[i]);
312 }
313 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
314 rom_base, &address_space_memory);
315 riscv_rom_copy_firmware_info(machine, rom_base, rom_size, sizeof(reset_vec),
316 kernel_entry);
317
318 return;
319}
320