LXR qemu/hw/riscv/microchip

   1/*
   2 * QEMU RISC-V Board Compatible with Microchip PolarFire SoC Icicle Kit
   3 *
   4 * Copyright (c) 2020 Wind River Systems, Inc.
   5 *
   6 * Author:
   7 *   Bin Meng <bin.meng@windriver.com>
   8 *
   9 * Provides a board compatible with the Microchip PolarFire SoC Icicle Kit
  10 *
  11 * 0) CLINT (Core Level Interruptor)
  12 * 1) PLIC (Platform Level Interrupt Controller)
  13 * 2) eNVM (Embedded Non-Volatile Memory)
  14 * 3) MMUARTs (Multi-Mode UART)
  15 * 4) Cadence eMMC/SDHC controller and an SD card connected to it
  16 * 5) SiFive Platform DMA (Direct Memory Access Controller)
  17 * 6) GEM (Gigabit Ethernet MAC Controller)
  18 * 7) DMC (DDR Memory Controller)
  19 * 8) IOSCB modules
  20 *
  21 * This board currently generates devicetree dynamically that indicates at least
  22 * two harts and up to five harts.
  23 *
  24 * This program is free software; you can redistribute it and/or modify it
  25 * under the terms and conditions of the GNU General Public License,
  26 * version 2 or later, as published by the Free Software Foundation.
  27 *
  28 * This program is distributed in the hope it will be useful, but WITHOUT
  29 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  30 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  31 * more details.
  32 *
  33 * You should have received a copy of the GNU General Public License along with
  34 * this program.  If not, see <http://www.gnu.org/licenses/>.
  35 */
  36
  37#include "qemu/osdep.h"
  38#include "qemu/error-report.h"
  39#include "qemu/units.h"
  40#include "qemu/cutils.h"
  41#include "qapi/error.h"
  42#include "hw/boards.h"
  43#include "hw/loader.h"
  44#include "hw/sysbus.h"
  45#include "chardev/char.h"
  46#include "hw/cpu/cluster.h"
  47#include "target/riscv/cpu.h"
  48#include "hw/misc/unimp.h"
  49#include "hw/riscv/boot.h"
  50#include "hw/riscv/riscv_hart.h"
  51#include "hw/riscv/microchip_pfsoc.h"
  52#include "hw/intc/riscv_aclint.h"
  53#include "hw/intc/sifive_plic.h"
  54#include "sysemu/device_tree.h"
  55#include "sysemu/sysemu.h"
  56
  57/*
  58 * The BIOS image used by this machine is called Hart Software Services (HSS).
  59 * See https://github.com/polarfire-soc/hart-software-services
  60 */
  61#define BIOS_FILENAME   "hss.bin"
  62#define RESET_VECTOR    0x20220000
  63
  64/* CLINT timebase frequency */
  65#define CLINT_TIMEBASE_FREQ 1000000
  66
  67/* GEM version */
  68#define GEM_REVISION    0x0107010c
  69
  70/*
  71 * The complete description of the whole PolarFire SoC memory map is scattered
  72 * in different documents. There are several places to look at for memory maps:
  73 *
  74 * 1 Chapter 11 "MSS Memory Map", in the doc "UG0880: PolarFire SoC FPGA
  75 *   Microprocessor Subsystem (MSS) User Guide", which can be downloaded from
  76 *   https://www.microsemi.com/document-portal/doc_download/
  77 *   1244570-ug0880-polarfire-soc-fpga-microprocessor-subsystem-mss-user-guide,
  78 *   describes the whole picture of the PolarFire SoC memory map.
  79 *
  80 * 2 A zip file for PolarFire soC memory map, which can be downloaded from
  81 *   https://www.microsemi.com/document-portal/doc_download/
  82 *   1244581-polarfire-soc-register-map, contains the following 2 major parts:
  83 *   - Register Map/PF_SoC_RegMap_V1_1/pfsoc_regmap.htm
  84 *     describes the complete integrated peripherals memory map
  85 *   - Register Map/PF_SoC_RegMap_V1_1/MPFS250T/mpfs250t_ioscb_memmap_dri.htm
  86 *     describes the complete IOSCB modules memory maps
  87 */
  88static const MemMapEntry microchip_pfsoc_memmap[] = {
  89    [MICROCHIP_PFSOC_RSVD0] =           {        0x0,      0x100 },
  90    [MICROCHIP_PFSOC_DEBUG] =           {      0x100,      0xf00 },
  91    [MICROCHIP_PFSOC_E51_DTIM] =        {  0x1000000,     0x2000 },
  92    [MICROCHIP_PFSOC_BUSERR_UNIT0] =    {  0x1700000,     0x1000 },
  93    [MICROCHIP_PFSOC_BUSERR_UNIT1] =    {  0x1701000,     0x1000 },
  94    [MICROCHIP_PFSOC_BUSERR_UNIT2] =    {  0x1702000,     0x1000 },
  95    [MICROCHIP_PFSOC_BUSERR_UNIT3] =    {  0x1703000,     0x1000 },
  96    [MICROCHIP_PFSOC_BUSERR_UNIT4] =    {  0x1704000,     0x1000 },
  97    [MICROCHIP_PFSOC_CLINT] =           {  0x2000000,    0x10000 },
  98    [MICROCHIP_PFSOC_L2CC] =            {  0x2010000,     0x1000 },
  99    [MICROCHIP_PFSOC_DMA] =             {  0x3000000,   0x100000 },
 100    [MICROCHIP_PFSOC_L2LIM] =           {  0x8000000,  0x2000000 },
 101    [MICROCHIP_PFSOC_PLIC] =            {  0xc000000,  0x4000000 },
 102    [MICROCHIP_PFSOC_MMUART0] =         { 0x20000000,     0x1000 },
 103    [MICROCHIP_PFSOC_SYSREG] =          { 0x20002000,     0x2000 },
 104    [MICROCHIP_PFSOC_MPUCFG] =          { 0x20005000,     0x1000 },
 105    [MICROCHIP_PFSOC_DDR_SGMII_PHY] =   { 0x20007000,     0x1000 },
 106    [MICROCHIP_PFSOC_EMMC_SD] =         { 0x20008000,     0x1000 },
 107    [MICROCHIP_PFSOC_DDR_CFG] =         { 0x20080000,    0x40000 },
 108    [MICROCHIP_PFSOC_MMUART1] =         { 0x20100000,     0x1000 },
 109    [MICROCHIP_PFSOC_MMUART2] =         { 0x20102000,     0x1000 },
 110    [MICROCHIP_PFSOC_MMUART3] =         { 0x20104000,     0x1000 },
 111    [MICROCHIP_PFSOC_MMUART4] =         { 0x20106000,     0x1000 },
 112    [MICROCHIP_PFSOC_SPI0] =            { 0x20108000,     0x1000 },
 113    [MICROCHIP_PFSOC_SPI1] =            { 0x20109000,     0x1000 },
 114    [MICROCHIP_PFSOC_I2C1] =            { 0x2010b000,     0x1000 },
 115    [MICROCHIP_PFSOC_GEM0] =            { 0x20110000,     0x2000 },
 116    [MICROCHIP_PFSOC_GEM1] =            { 0x20112000,     0x2000 },
 117    [MICROCHIP_PFSOC_GPIO0] =           { 0x20120000,     0x1000 },
 118    [MICROCHIP_PFSOC_GPIO1] =           { 0x20121000,     0x1000 },
 119    [MICROCHIP_PFSOC_GPIO2] =           { 0x20122000,     0x1000 },
 120    [MICROCHIP_PFSOC_ENVM_CFG] =        { 0x20200000,     0x1000 },
 121    [MICROCHIP_PFSOC_ENVM_DATA] =       { 0x20220000,    0x20000 },
 122    [MICROCHIP_PFSOC_QSPI_XIP] =        { 0x21000000,  0x1000000 },
 123    [MICROCHIP_PFSOC_IOSCB] =           { 0x30000000, 0x10000000 },
 124    [MICROCHIP_PFSOC_EMMC_SD_MUX] =     { 0x4f000000,        0x4 },
 125    [MICROCHIP_PFSOC_DRAM_LO] =         { 0x80000000, 0x40000000 },
 126    [MICROCHIP_PFSOC_DRAM_LO_ALIAS] =   { 0xc0000000, 0x40000000 },
 127    [MICROCHIP_PFSOC_DRAM_HI] =       { 0x1000000000,        0x0 },
 128    [MICROCHIP_PFSOC_DRAM_HI_ALIAS] = { 0x1400000000,        0x0 },
 129};
 130
 131static void microchip_pfsoc_soc_instance_init(Object *obj)
 132{
 133    MachineState *ms = MACHINE(qdev_get_machine());
 134    MicrochipPFSoCState *s = MICROCHIP_PFSOC(obj);
 135
 136    object_initialize_child(obj, "e-cluster", &s->e_cluster, TYPE_CPU_CLUSTER);
 137    qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0);
 138
 139    object_initialize_child(OBJECT(&s->e_cluster), "e-cpus", &s->e_cpus,
 140                            TYPE_RISCV_HART_ARRAY);
 141    qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1);
 142    qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0);
 143    qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type",
 144                         TYPE_RISCV_CPU_SIFIVE_E51);
 145    qdev_prop_set_uint64(DEVICE(&s->e_cpus), "resetvec", RESET_VECTOR);
 146
 147    object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUSTER);
 148    qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1);
 149
 150    object_initialize_child(OBJECT(&s->u_cluster), "u-cpus", &s->u_cpus,
 151                            TYPE_RISCV_HART_ARRAY);
 152    qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1);
 153    qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1);
 154    qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type",
 155                         TYPE_RISCV_CPU_SIFIVE_U54);
 156    qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", RESET_VECTOR);
 157
 158    object_initialize_child(obj, "dma-controller", &s->dma,
 159                            TYPE_SIFIVE_PDMA);
 160
 161    object_initialize_child(obj, "sysreg", &s->sysreg,
 162                            TYPE_MCHP_PFSOC_SYSREG);
 163
 164    object_initialize_child(obj, "ddr-sgmii-phy", &s->ddr_sgmii_phy,
 165                            TYPE_MCHP_PFSOC_DDR_SGMII_PHY);
 166    object_initialize_child(obj, "ddr-cfg", &s->ddr_cfg,
 167                            TYPE_MCHP_PFSOC_DDR_CFG);
 168
 169    object_initialize_child(obj, "gem0", &s->gem0, TYPE_CADENCE_GEM);
 170    object_initialize_child(obj, "gem1", &s->gem1, TYPE_CADENCE_GEM);
 171
 172    object_initialize_child(obj, "sd-controller", &s->sdhci,
 173                            TYPE_CADENCE_SDHCI);
 174
 175    object_initialize_child(obj, "ioscb", &s->ioscb, TYPE_MCHP_PFSOC_IOSCB);
 176}
 177
 178static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
 179{
 180    MachineState *ms = MACHINE(qdev_get_machine());
 181    MicrochipPFSoCState *s = MICROCHIP_PFSOC(dev);
 182    const MemMapEntry *memmap = microchip_pfsoc_memmap;
 183    MemoryRegion *system_memory = get_system_memory();
 184    MemoryRegion *rsvd0_mem = g_new(MemoryRegion, 1);
 185    MemoryRegion *e51_dtim_mem = g_new(MemoryRegion, 1);
 186    MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1);
 187    MemoryRegion *envm_data = g_new(MemoryRegion, 1);
 188    MemoryRegion *qspi_xip_mem = g_new(MemoryRegion, 1);
 189    char *plic_hart_config;
 190    NICInfo *nd;
 191    int i;
 192
 193    sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_abort);
 194    sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_abort);
 195    /*
 196     * The cluster must be realized after the RISC-V hart array container,
 197     * as the container's CPU object is only created on realize, and the
 198     * CPU must exist and have been parented into the cluster before the
 199     * cluster is realized.
 200     */
 201    qdev_realize(DEVICE(&s->e_cluster), NULL, &error_abort);
 202    qdev_realize(DEVICE(&s->u_cluster), NULL, &error_abort);
 203
 204    /* Reserved Memory at address 0 */
 205    memory_region_init_ram(rsvd0_mem, NULL, "microchip.pfsoc.rsvd0_mem",
 206                           memmap[MICROCHIP_PFSOC_RSVD0].size, &error_fatal);
 207    memory_region_add_subregion(system_memory,
 208                                memmap[MICROCHIP_PFSOC_RSVD0].base,
 209                                rsvd0_mem);
 210
 211    /* E51 DTIM */
 212    memory_region_init_ram(e51_dtim_mem, NULL, "microchip.pfsoc.e51_dtim_mem",
 213                           memmap[MICROCHIP_PFSOC_E51_DTIM].size, &error_fatal);
 214    memory_region_add_subregion(system_memory,
 215                                memmap[MICROCHIP_PFSOC_E51_DTIM].base,
 216                                e51_dtim_mem);
 217
 218    /* Bus Error Units */
 219    create_unimplemented_device("microchip.pfsoc.buserr_unit0_mem",
 220        memmap[MICROCHIP_PFSOC_BUSERR_UNIT0].base,
 221        memmap[MICROCHIP_PFSOC_BUSERR_UNIT0].size);
 222    create_unimplemented_device("microchip.pfsoc.buserr_unit1_mem",
 223        memmap[MICROCHIP_PFSOC_BUSERR_UNIT1].base,
 224        memmap[MICROCHIP_PFSOC_BUSERR_UNIT1].size);
 225    create_unimplemented_device("microchip.pfsoc.buserr_unit2_mem",
 226        memmap[MICROCHIP_PFSOC_BUSERR_UNIT2].base,
 227        memmap[MICROCHIP_PFSOC_BUSERR_UNIT2].size);
 228    create_unimplemented_device("microchip.pfsoc.buserr_unit3_mem",
 229        memmap[MICROCHIP_PFSOC_BUSERR_UNIT3].base,
 230        memmap[MICROCHIP_PFSOC_BUSERR_UNIT3].size);
 231    create_unimplemented_device("microchip.pfsoc.buserr_unit4_mem",
 232        memmap[MICROCHIP_PFSOC_BUSERR_UNIT4].base,
 233        memmap[MICROCHIP_PFSOC_BUSERR_UNIT4].size);
 234
 235    /* CLINT */
 236    riscv_aclint_swi_create(memmap[MICROCHIP_PFSOC_CLINT].base,
 237        0, ms->smp.cpus, false);
 238    riscv_aclint_mtimer_create(
 239        memmap[MICROCHIP_PFSOC_CLINT].base + RISCV_ACLINT_SWI_SIZE,
 240        RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, ms->smp.cpus,
 241        RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME,
 242        CLINT_TIMEBASE_FREQ, false);
 243
 244    /* L2 cache controller */
 245    create_unimplemented_device("microchip.pfsoc.l2cc",
 246        memmap[MICROCHIP_PFSOC_L2CC].base, memmap[MICROCHIP_PFSOC_L2CC].size);
 247
 248    /*
 249     * Add L2-LIM at reset size.
 250     * This should be reduced in size as the L2 Cache Controller WayEnable
 251     * register is incremented. Unfortunately I don't see a nice (or any) way
 252     * to handle reducing or blocking out the L2 LIM while still allowing it
 253     * be re returned to all enabled after a reset. For the time being, just
 254     * leave it enabled all the time. This won't break anything, but will be
 255     * too generous to misbehaving guests.
 256     */
 257    memory_region_init_ram(l2lim_mem, NULL, "microchip.pfsoc.l2lim",
 258                           memmap[MICROCHIP_PFSOC_L2LIM].size, &error_fatal);
 259    memory_region_add_subregion(system_memory,
 260                                memmap[MICROCHIP_PFSOC_L2LIM].base,
 261                                l2lim_mem);
 262
 263    /* create PLIC hart topology configuration string */
 264    plic_hart_config = riscv_plic_hart_config_string(ms->smp.cpus);
 265
 266    /* PLIC */
 267    s->plic = sifive_plic_create(memmap[MICROCHIP_PFSOC_PLIC].base,
 268        plic_hart_config, ms->smp.cpus, 0,
 269        MICROCHIP_PFSOC_PLIC_NUM_SOURCES,
 270        MICROCHIP_PFSOC_PLIC_NUM_PRIORITIES,
 271        MICROCHIP_PFSOC_PLIC_PRIORITY_BASE,
 272        MICROCHIP_PFSOC_PLIC_PENDING_BASE,
 273        MICROCHIP_PFSOC_PLIC_ENABLE_BASE,
 274        MICROCHIP_PFSOC_PLIC_ENABLE_STRIDE,
 275        MICROCHIP_PFSOC_PLIC_CONTEXT_BASE,
 276        MICROCHIP_PFSOC_PLIC_CONTEXT_STRIDE,
 277        memmap[MICROCHIP_PFSOC_PLIC].size);
 278    g_free(plic_hart_config);
 279
 280    /* DMA */
 281    sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp);
 282    sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0,
 283                    memmap[MICROCHIP_PFSOC_DMA].base);
 284    for (i = 0; i < SIFIVE_PDMA_IRQS; i++) {
 285        sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), i,
 286                           qdev_get_gpio_in(DEVICE(s->plic),
 287                                            MICROCHIP_PFSOC_DMA_IRQ0 + i));
 288    }
 289
 290    /* SYSREG */
 291    sysbus_realize(SYS_BUS_DEVICE(&s->sysreg), errp);
 292    sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysreg), 0,
 293                    memmap[MICROCHIP_PFSOC_SYSREG].base);
 294
 295    /* MPUCFG */
 296    create_unimplemented_device("microchip.pfsoc.mpucfg",
 297        memmap[MICROCHIP_PFSOC_MPUCFG].base,
 298        memmap[MICROCHIP_PFSOC_MPUCFG].size);
 299
 300    /* DDR SGMII PHY */
 301    sysbus_realize(SYS_BUS_DEVICE(&s->ddr_sgmii_phy), errp);
 302    sysbus_mmio_map(SYS_BUS_DEVICE(&s->ddr_sgmii_phy), 0,
 303                    memmap[MICROCHIP_PFSOC_DDR_SGMII_PHY].base);
 304
 305    /* DDR CFG */
 306    sysbus_realize(SYS_BUS_DEVICE(&s->ddr_cfg), errp);
 307    sysbus_mmio_map(SYS_BUS_DEVICE(&s->ddr_cfg), 0,
 308                    memmap[MICROCHIP_PFSOC_DDR_CFG].base);
 309
 310    /* SDHCI */
 311    sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp);
 312    sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0,
 313                    memmap[MICROCHIP_PFSOC_EMMC_SD].base);
 314    sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
 315        qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_EMMC_SD_IRQ));
 316
 317    /* MMUARTs */
 318    s->serial0 = mchp_pfsoc_mmuart_create(system_memory,
 319        memmap[MICROCHIP_PFSOC_MMUART0].base,
 320        qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART0_IRQ),
 321        serial_hd(0));
 322    s->serial1 = mchp_pfsoc_mmuart_create(system_memory,
 323        memmap[MICROCHIP_PFSOC_MMUART1].base,
 324        qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART1_IRQ),
 325        serial_hd(1));
 326    s->serial2 = mchp_pfsoc_mmuart_create(system_memory,
 327        memmap[MICROCHIP_PFSOC_MMUART2].base,
 328        qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART2_IRQ),
 329        serial_hd(2));
 330    s->serial3 = mchp_pfsoc_mmuart_create(system_memory,
 331        memmap[MICROCHIP_PFSOC_MMUART3].base,
 332        qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART3_IRQ),
 333        serial_hd(3));
 334    s->serial4 = mchp_pfsoc_mmuart_create(system_memory,
 335        memmap[MICROCHIP_PFSOC_MMUART4].base,
 336        qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART4_IRQ),
 337        serial_hd(4));
 338
 339    /* SPI */
 340    create_unimplemented_device("microchip.pfsoc.spi0",
 341        memmap[MICROCHIP_PFSOC_SPI0].base,
 342        memmap[MICROCHIP_PFSOC_SPI0].size);
 343    create_unimplemented_device("microchip.pfsoc.spi1",
 344        memmap[MICROCHIP_PFSOC_SPI1].base,
 345        memmap[MICROCHIP_PFSOC_SPI1].size);
 346
 347    /* I2C1 */
 348    create_unimplemented_device("microchip.pfsoc.i2c1",
 349        memmap[MICROCHIP_PFSOC_I2C1].base,
 350        memmap[MICROCHIP_PFSOC_I2C1].size);
 351
 352    /* GEMs */
 353
 354    nd = &nd_table[0];
 355    if (nd->used) {
 356        qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
 357        qdev_set_nic_properties(DEVICE(&s->gem0), nd);
 358    }
 359    nd = &nd_table[1];
 360    if (nd->used) {
 361        qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
 362        qdev_set_nic_properties(DEVICE(&s->gem1), nd);
 363    }
 364
 365    object_property_set_int(OBJECT(&s->gem0), "revision", GEM_REVISION, errp);
 366    object_property_set_int(OBJECT(&s->gem0), "phy-addr", 8, errp);
 367    sysbus_realize(SYS_BUS_DEVICE(&s->gem0), errp);
 368    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem0), 0,
 369                    memmap[MICROCHIP_PFSOC_GEM0].base);
 370    sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem0), 0,
 371        qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_GEM0_IRQ));
 372
 373    object_property_set_int(OBJECT(&s->gem1), "revision", GEM_REVISION, errp);
 374    object_property_set_int(OBJECT(&s->gem1), "phy-addr", 9, errp);
 375    sysbus_realize(SYS_BUS_DEVICE(&s->gem1), errp);
 376    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem1), 0,
 377                    memmap[MICROCHIP_PFSOC_GEM1].base);
 378    sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem1), 0,
 379        qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_GEM1_IRQ));
 380
 381    /* GPIOs */
 382    create_unimplemented_device("microchip.pfsoc.gpio0",
 383        memmap[MICROCHIP_PFSOC_GPIO0].base,
 384        memmap[MICROCHIP_PFSOC_GPIO0].size);
 385    create_unimplemented_device("microchip.pfsoc.gpio1",
 386        memmap[MICROCHIP_PFSOC_GPIO1].base,
 387        memmap[MICROCHIP_PFSOC_GPIO1].size);
 388    create_unimplemented_device("microchip.pfsoc.gpio2",
 389        memmap[MICROCHIP_PFSOC_GPIO2].base,
 390        memmap[MICROCHIP_PFSOC_GPIO2].size);
 391
 392    /* eNVM */
 393    memory_region_init_rom(envm_data, OBJECT(dev), "microchip.pfsoc.envm.data",
 394                           memmap[MICROCHIP_PFSOC_ENVM_DATA].size,
 395                           &error_fatal);
 396    memory_region_add_subregion(system_memory,
 397                                memmap[MICROCHIP_PFSOC_ENVM_DATA].base,
 398                                envm_data);
 399
 400    /* IOSCB */
 401    sysbus_realize(SYS_BUS_DEVICE(&s->ioscb), errp);
 402    sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioscb), 0,
 403                    memmap[MICROCHIP_PFSOC_IOSCB].base);
 404
 405    /* eMMC/SD mux */
 406    create_unimplemented_device("microchip.pfsoc.emmc_sd_mux",
 407        memmap[MICROCHIP_PFSOC_EMMC_SD_MUX].base,
 408        memmap[MICROCHIP_PFSOC_EMMC_SD_MUX].size);
 409
 410    /* QSPI Flash */
 411    memory_region_init_rom(qspi_xip_mem, OBJECT(dev),
 412                           "microchip.pfsoc.qspi_xip",
 413                           memmap[MICROCHIP_PFSOC_QSPI_XIP].size,
 414                           &error_fatal);
 415    memory_region_add_subregion(system_memory,
 416                                memmap[MICROCHIP_PFSOC_QSPI_XIP].base,
 417                                qspi_xip_mem);
 418}
 419
 420static void microchip_pfsoc_soc_class_init(ObjectClass *oc, void *data)
 421{
 422    DeviceClass *dc = DEVICE_CLASS(oc);
 423
 424    dc->realize = microchip_pfsoc_soc_realize;
 425    /* Reason: Uses serial_hds in realize function, thus can't be used twice */
 426    dc->user_creatable = false;
 427}
 428
 429static const TypeInfo microchip_pfsoc_soc_type_info = {
 430    .name = TYPE_MICROCHIP_PFSOC,
 431    .parent = TYPE_DEVICE,
 432    .instance_size = sizeof(MicrochipPFSoCState),
 433    .instance_init = microchip_pfsoc_soc_instance_init,
 434    .class_init = microchip_pfsoc_soc_class_init,
 435};
 436
 437static void microchip_pfsoc_soc_register_types(void)
 438{
 439    type_register_static(&microchip_pfsoc_soc_type_info);
 440}
 441
 442type_init(microchip_pfsoc_soc_register_types)
 443
 444static void microchip_icicle_kit_machine_init(MachineState *machine)
 445{
 446    MachineClass *mc = MACHINE_GET_CLASS(machine);
 447    const MemMapEntry *memmap = microchip_pfsoc_memmap;
 448    MicrochipIcicleKitState *s = MICROCHIP_ICICLE_KIT_MACHINE(machine);
 449    MemoryRegion *system_memory = get_system_memory();
 450    MemoryRegion *mem_low = g_new(MemoryRegion, 1);
 451    MemoryRegion *mem_low_alias = g_new(MemoryRegion, 1);
 452    MemoryRegion *mem_high = g_new(MemoryRegion, 1);
 453    MemoryRegion *mem_high_alias = g_new(MemoryRegion, 1);
 454    uint64_t mem_low_size, mem_high_size;
 455    hwaddr firmware_load_addr;
 456    const char *firmware_name;
 457    bool kernel_as_payload = false;
 458    target_ulong firmware_end_addr, kernel_start_addr;
 459    uint64_t kernel_entry;
 460    uint32_t fdt_load_addr;
 461    DriveInfo *dinfo = drive_get_next(IF_SD);
 462
 463    /* Sanity check on RAM size */
 464    if (machine->ram_size < mc->default_ram_size) {
 465        char *sz = size_to_str(mc->default_ram_size);
 466        error_report("Invalid RAM size, should be bigger than %s", sz);
 467        g_free(sz);
 468        exit(EXIT_FAILURE);
 469    }
 470
 471    /* Initialize SoC */
 472    object_initialize_child(OBJECT(machine), "soc", &s->soc,
 473                            TYPE_MICROCHIP_PFSOC);
 474    qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
 475
 476    /* Split RAM into low and high regions using aliases to machine->ram */
 477    mem_low_size = memmap[MICROCHIP_PFSOC_DRAM_LO].size;
 478    mem_high_size = machine->ram_size - mem_low_size;
 479    memory_region_init_alias(mem_low, NULL,
 480                             "microchip.icicle.kit.ram_low", machine->ram,
 481                             0, mem_low_size);
 482    memory_region_init_alias(mem_high, NULL,
 483                             "microchip.icicle.kit.ram_high", machine->ram,
 484                             mem_low_size, mem_high_size);
 485
 486    /* Register RAM */
 487    memory_region_add_subregion(system_memory,
 488                                memmap[MICROCHIP_PFSOC_DRAM_LO].base,
 489                                mem_low);
 490    memory_region_add_subregion(system_memory,
 491                                memmap[MICROCHIP_PFSOC_DRAM_HI].base,
 492                                mem_high);
 493
 494    /* Create aliases for the low and high RAM regions */
 495    memory_region_init_alias(mem_low_alias, NULL,
 496                             "microchip.icicle.kit.ram_low.alias",
 497                             mem_low, 0, mem_low_size);
 498    memory_region_add_subregion(system_memory,
 499                                memmap[MICROCHIP_PFSOC_DRAM_LO_ALIAS].base,
 500                                mem_low_alias);
 501    memory_region_init_alias(mem_high_alias, NULL,
 502                             "microchip.icicle.kit.ram_high.alias",
 503                             mem_high, 0, mem_high_size);
 504    memory_region_add_subregion(system_memory,
 505                                memmap[MICROCHIP_PFSOC_DRAM_HI_ALIAS].base,
 506                                mem_high_alias);
 507
 508    /* Attach an SD card */
 509    if (dinfo) {
 510        CadenceSDHCIState *sdhci = &(s->soc.sdhci);
 511        DeviceState *card = qdev_new(TYPE_SD_CARD);
 512
 513        qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo),
 514                                &error_fatal);
 515        qdev_realize_and_unref(card, sdhci->bus, &error_fatal);
 516    }
 517
 518    /*
 519     * We follow the following table to select which payload we execute.
 520     *
 521     *  -bios |    -kernel | payload
 522     * -------+------------+--------
 523     *      N |          N | HSS
 524     *      Y | don't care | HSS
 525     *      N |          Y | kernel
 526     *
 527     * This ensures backwards compatibility with how we used to expose -bios
 528     * to users but allows them to run through direct kernel booting as well.
 529     *
 530     * When -kernel is used for direct boot, -dtb must be present to provide
 531     * a valid device tree for the board, as we don't generate device tree.
 532     */
 533
 534    if (machine->kernel_filename && machine->dtb) {
 535        int fdt_size;
 536        machine->fdt = load_device_tree(machine->dtb, &fdt_size);
 537        if (!machine->fdt) {
 538            error_report("load_device_tree() failed");
 539            exit(1);
 540        }
 541
 542        firmware_name = RISCV64_BIOS_BIN;
 543        firmware_load_addr = memmap[MICROCHIP_PFSOC_DRAM_LO].base;
 544        kernel_as_payload = true;
 545    }
 546
 547    if (!kernel_as_payload) {
 548        firmware_name = BIOS_FILENAME;
 549        firmware_load_addr = RESET_VECTOR;
 550    }
 551
 552    /* Load the firmware */
 553    firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name,
 554                                                     firmware_load_addr, NULL);
 555
 556    if (kernel_as_payload) {
 557        kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus,
 558                                                         firmware_end_addr);
 559
 560        kernel_entry = riscv_load_kernel(machine->kernel_filename,
 561                                         kernel_start_addr, NULL);
 562
 563        if (machine->initrd_filename) {
 564            hwaddr start;
 565            hwaddr end = riscv_load_initrd(machine->initrd_filename,
 566                                           machine->ram_size, kernel_entry,
 567                                           &start);
 568            qemu_fdt_setprop_cell(machine->fdt, "/chosen",
 569                                  "linux,initrd-start", start);
 570            qemu_fdt_setprop_cell(machine->fdt, "/chosen",
 571                                  "linux,initrd-end", end);
 572        }
 573
 574        if (machine->kernel_cmdline) {
 575            qemu_fdt_setprop_string(machine->fdt, "/chosen",
 576                                    "bootargs", machine->kernel_cmdline);
 577        }
 578
 579        /* Compute the fdt load address in dram */
 580        fdt_load_addr = riscv_load_fdt(memmap[MICROCHIP_PFSOC_DRAM_LO].base,
 581                                       machine->ram_size, machine->fdt);
 582        /* Load the reset vector */
 583        riscv_setup_rom_reset_vec(machine, &s->soc.u_cpus, firmware_load_addr,
 584                                  memmap[MICROCHIP_PFSOC_ENVM_DATA].base,
 585                                  memmap[MICROCHIP_PFSOC_ENVM_DATA].size,
 586                                  kernel_entry, fdt_load_addr, machine->fdt);
 587    }
 588}
 589
 590static void microchip_icicle_kit_machine_class_init(ObjectClass *oc, void *data)
 591{
 592    MachineClass *mc = MACHINE_CLASS(oc);
 593
 594    mc->desc = "Microchip PolarFire SoC Icicle Kit";
 595    mc->init = microchip_icicle_kit_machine_init;
 596    mc->max_cpus = MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT +
 597                   MICROCHIP_PFSOC_COMPUTE_CPU_COUNT;
 598    mc->min_cpus = MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT + 1;
 599    mc->default_cpus = mc->min_cpus;
 600    mc->default_ram_id = "microchip.icicle.kit.ram";
 601
 602    /*
 603     * Map 513 MiB high memory, the mimimum required high memory size, because
 604     * HSS will do memory test against the high memory address range regardless
 605     * of physical memory installed.
 606     *
 607     * See memory_tests() in mss_ddr.c in the HSS source code.
 608     */
 609    mc->default_ram_size = 1537 * MiB;
 610}
 611
 612static const TypeInfo microchip_icicle_kit_machine_typeinfo = {
 613    .name       = MACHINE_TYPE_NAME("microchip-icicle-kit"),
 614    .parent     = TYPE_MACHINE,
 615    .class_init = microchip_icicle_kit_machine_class_init,
 616    .instance_size = sizeof(MicrochipIcicleKitState),
 617};
 618
 619static void microchip_icicle_kit_machine_init_register_types(void)
 620{
 621    type_register_static(&microchip_icicle_kit_machine_typeinfo);
 622}
 623
 624type_init(microchip_icicle_kit_machine_init_register_types)
 625