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26#include "qemu/osdep.h"
27#include "qemu/error-report.h"
28#include "qapi/error.h"
29#include "hw/boards.h"
30#include "hw/loader.h"
31#include "hw/sysbus.h"
32#include "target/riscv/cpu.h"
33#include "hw/riscv/riscv_hart.h"
34#include "hw/riscv/spike.h"
35#include "hw/riscv/boot.h"
36#include "hw/riscv/numa.h"
37#include "hw/char/riscv_htif.h"
38#include "hw/intc/riscv_aclint.h"
39#include "chardev/char.h"
40#include "sysemu/device_tree.h"
41#include "sysemu/sysemu.h"
42
43static const MemMapEntry spike_memmap[] = {
44 [SPIKE_MROM] = { 0x1000, 0xf000 },
45 [SPIKE_CLINT] = { 0x2000000, 0x10000 },
46 [SPIKE_DRAM] = { 0x80000000, 0x0 },
47};
48
49static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
50 uint64_t mem_size, const char *cmdline, bool is_32_bit)
51{
52 void *fdt;
53 uint64_t addr, size;
54 unsigned long clint_addr;
55 int cpu, socket;
56 MachineState *mc = MACHINE(s);
57 uint32_t *clint_cells;
58 uint32_t cpu_phandle, intc_phandle, phandle = 1;
59 char *name, *mem_name, *clint_name, *clust_name;
60 char *core_name, *cpu_name, *intc_name;
61 static const char * const clint_compat[2] = {
62 "sifive,clint0", "riscv,clint0"
63 };
64
65 fdt = s->fdt = create_device_tree(&s->fdt_size);
66 if (!fdt) {
67 error_report("create_device_tree() failed");
68 exit(1);
69 }
70
71 qemu_fdt_setprop_string(fdt, "/", "model", "ucbbar,spike-bare,qemu");
72 qemu_fdt_setprop_string(fdt, "/", "compatible", "ucbbar,spike-bare-dev");
73 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
74 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
75
76 qemu_fdt_add_subnode(fdt, "/htif");
77 qemu_fdt_setprop_string(fdt, "/htif", "compatible", "ucb,htif0");
78
79 qemu_fdt_add_subnode(fdt, "/soc");
80 qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
81 qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
82 qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
83 qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
84
85 qemu_fdt_add_subnode(fdt, "/cpus");
86 qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
87 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ);
88 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
89 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
90 qemu_fdt_add_subnode(fdt, "/cpus/cpu-map");
91
92 for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) {
93 clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket);
94 qemu_fdt_add_subnode(fdt, clust_name);
95
96 clint_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4);
97
98 for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) {
99 cpu_phandle = phandle++;
100
101 cpu_name = g_strdup_printf("/cpus/cpu@%d",
102 s->soc[socket].hartid_base + cpu);
103 qemu_fdt_add_subnode(fdt, cpu_name);
104 if (is_32_bit) {
105 qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv32");
106 } else {
107 qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv48");
108 }
109 name = riscv_isa_string(&s->soc[socket].harts[cpu]);
110 qemu_fdt_setprop_string(fdt, cpu_name, "riscv,isa", name);
111 g_free(name);
112 qemu_fdt_setprop_string(fdt, cpu_name, "compatible", "riscv");
113 qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay");
114 qemu_fdt_setprop_cell(fdt, cpu_name, "reg",
115 s->soc[socket].hartid_base + cpu);
116 qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu");
117 riscv_socket_fdt_write_id(mc, fdt, cpu_name, socket);
118 qemu_fdt_setprop_cell(fdt, cpu_name, "phandle", cpu_phandle);
119
120 intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name);
121 qemu_fdt_add_subnode(fdt, intc_name);
122 intc_phandle = phandle++;
123 qemu_fdt_setprop_cell(fdt, intc_name, "phandle", intc_phandle);
124 qemu_fdt_setprop_string(fdt, intc_name, "compatible",
125 "riscv,cpu-intc");
126 qemu_fdt_setprop(fdt, intc_name, "interrupt-controller", NULL, 0);
127 qemu_fdt_setprop_cell(fdt, intc_name, "#interrupt-cells", 1);
128
129 clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
130 clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
131 clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
132 clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
133
134 core_name = g_strdup_printf("%s/core%d", clust_name, cpu);
135 qemu_fdt_add_subnode(fdt, core_name);
136 qemu_fdt_setprop_cell(fdt, core_name, "cpu", cpu_phandle);
137
138 g_free(core_name);
139 g_free(intc_name);
140 g_free(cpu_name);
141 }
142
143 addr = memmap[SPIKE_DRAM].base + riscv_socket_mem_offset(mc, socket);
144 size = riscv_socket_mem_size(mc, socket);
145 mem_name = g_strdup_printf("/memory@%lx", (long)addr);
146 qemu_fdt_add_subnode(fdt, mem_name);
147 qemu_fdt_setprop_cells(fdt, mem_name, "reg",
148 addr >> 32, addr, size >> 32, size);
149 qemu_fdt_setprop_string(fdt, mem_name, "device_type", "memory");
150 riscv_socket_fdt_write_id(mc, fdt, mem_name, socket);
151 g_free(mem_name);
152
153 clint_addr = memmap[SPIKE_CLINT].base +
154 (memmap[SPIKE_CLINT].size * socket);
155 clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr);
156 qemu_fdt_add_subnode(fdt, clint_name);
157 qemu_fdt_setprop_string_array(fdt, clint_name, "compatible",
158 (char **)&clint_compat, ARRAY_SIZE(clint_compat));
159 qemu_fdt_setprop_cells(fdt, clint_name, "reg",
160 0x0, clint_addr, 0x0, memmap[SPIKE_CLINT].size);
161 qemu_fdt_setprop(fdt, clint_name, "interrupts-extended",
162 clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
163 riscv_socket_fdt_write_id(mc, fdt, clint_name, socket);
164
165 g_free(clint_name);
166 g_free(clint_cells);
167 g_free(clust_name);
168 }
169
170 riscv_socket_fdt_write_distance_matrix(mc, fdt);
171
172 if (cmdline) {
173 qemu_fdt_add_subnode(fdt, "/chosen");
174 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
175 }
176}
177
178static void spike_board_init(MachineState *machine)
179{
180 const MemMapEntry *memmap = spike_memmap;
181 SpikeState *s = SPIKE_MACHINE(machine);
182 MemoryRegion *system_memory = get_system_memory();
183 MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
184 target_ulong firmware_end_addr, kernel_start_addr;
185 uint32_t fdt_load_addr;
186 uint64_t kernel_entry;
187 char *soc_name;
188 int i, base_hartid, hart_count;
189
190
191 if (SPIKE_SOCKETS_MAX < riscv_socket_count(machine)) {
192 error_report("number of sockets/nodes should be less than %d",
193 SPIKE_SOCKETS_MAX);
194 exit(1);
195 }
196
197
198 for (i = 0; i < riscv_socket_count(machine); i++) {
199 if (!riscv_socket_check_hartids(machine, i)) {
200 error_report("discontinuous hartids in socket%d", i);
201 exit(1);
202 }
203
204 base_hartid = riscv_socket_first_hartid(machine, i);
205 if (base_hartid < 0) {
206 error_report("can't find hartid base for socket%d", i);
207 exit(1);
208 }
209
210 hart_count = riscv_socket_hart_count(machine, i);
211 if (hart_count < 0) {
212 error_report("can't find hart count for socket%d", i);
213 exit(1);
214 }
215
216 soc_name = g_strdup_printf("soc%d", i);
217 object_initialize_child(OBJECT(machine), soc_name, &s->soc[i],
218 TYPE_RISCV_HART_ARRAY);
219 g_free(soc_name);
220 object_property_set_str(OBJECT(&s->soc[i]), "cpu-type",
221 machine->cpu_type, &error_abort);
222 object_property_set_int(OBJECT(&s->soc[i]), "hartid-base",
223 base_hartid, &error_abort);
224 object_property_set_int(OBJECT(&s->soc[i]), "num-harts",
225 hart_count, &error_abort);
226 sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_abort);
227
228
229 riscv_aclint_swi_create(
230 memmap[SPIKE_CLINT].base + i * memmap[SPIKE_CLINT].size,
231 base_hartid, hart_count, false);
232 riscv_aclint_mtimer_create(
233 memmap[SPIKE_CLINT].base + i * memmap[SPIKE_CLINT].size +
234 RISCV_ACLINT_SWI_SIZE,
235 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count,
236 RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME,
237 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, false);
238 }
239
240
241 memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base,
242 machine->ram);
243
244
245 create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
246 riscv_is_32bit(&s->soc[0]));
247
248
249 memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom",
250 memmap[SPIKE_MROM].size, &error_fatal);
251 memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base,
252 mask_rom);
253
254
255
256
257
258
259 if (riscv_is_32bit(&s->soc[0])) {
260 firmware_end_addr = riscv_find_and_load_firmware(machine,
261 RISCV32_BIOS_ELF, memmap[SPIKE_DRAM].base,
262 htif_symbol_callback);
263 } else {
264 firmware_end_addr = riscv_find_and_load_firmware(machine,
265 RISCV64_BIOS_ELF, memmap[SPIKE_DRAM].base,
266 htif_symbol_callback);
267 }
268
269 if (machine->kernel_filename) {
270 kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0],
271 firmware_end_addr);
272
273 kernel_entry = riscv_load_kernel(machine->kernel_filename,
274 kernel_start_addr,
275 htif_symbol_callback);
276
277 if (machine->initrd_filename) {
278 hwaddr start;
279 hwaddr end = riscv_load_initrd(machine->initrd_filename,
280 machine->ram_size, kernel_entry,
281 &start);
282 qemu_fdt_setprop_cell(s->fdt, "/chosen",
283 "linux,initrd-start", start);
284 qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
285 end);
286 }
287 } else {
288
289
290
291
292 kernel_entry = 0;
293 }
294
295
296 fdt_load_addr = riscv_load_fdt(memmap[SPIKE_DRAM].base,
297 machine->ram_size, s->fdt);
298
299 riscv_setup_rom_reset_vec(machine, &s->soc[0], memmap[SPIKE_DRAM].base,
300 memmap[SPIKE_MROM].base,
301 memmap[SPIKE_MROM].size, kernel_entry,
302 fdt_load_addr, s->fdt);
303
304
305 htif_mm_init(system_memory, mask_rom,
306 &s->soc[0].harts[0].env, serial_hd(0));
307}
308
309static void spike_machine_instance_init(Object *obj)
310{
311}
312
313static void spike_machine_class_init(ObjectClass *oc, void *data)
314{
315 MachineClass *mc = MACHINE_CLASS(oc);
316
317 mc->desc = "RISC-V Spike board";
318 mc->init = spike_board_init;
319 mc->max_cpus = SPIKE_CPUS_MAX;
320 mc->is_default = true;
321 mc->default_cpu_type = TYPE_RISCV_CPU_BASE;
322 mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids;
323 mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
324 mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
325 mc->numa_mem_supported = true;
326 mc->default_ram_id = "riscv.spike.ram";
327}
328
329static const TypeInfo spike_machine_typeinfo = {
330 .name = MACHINE_TYPE_NAME("spike"),
331 .parent = TYPE_MACHINE,
332 .class_init = spike_machine_class_init,
333 .instance_init = spike_machine_instance_init,
334 .instance_size = sizeof(SpikeState),
335};
336
337static void spike_machine_init_register_types(void)
338{
339 type_register_static(&spike_machine_typeinfo);
340}
341
342type_init(spike_machine_init_register_types)
343
