qemu/hw/sparc/sun4m.c
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   1/*
   2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
   3 *
   4 * Copyright (c) 2003-2005 Fabrice Bellard
   5 *
   6 * Permission is hereby granted, free of charge, to any person obtaining a copy
   7 * of this software and associated documentation files (the "Software"), to deal
   8 * in the Software without restriction, including without limitation the rights
   9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10 * copies of the Software, and to permit persons to whom the Software is
  11 * furnished to do so, subject to the following conditions:
  12 *
  13 * The above copyright notice and this permission notice shall be included in
  14 * all copies or substantial portions of the Software.
  15 *
  16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22 * THE SOFTWARE.
  23 */
  24#include "qemu/osdep.h"
  25#include "qemu/units.h"
  26#include "qapi/error.h"
  27#include "qemu-common.h"
  28#include "cpu.h"
  29#include "hw/sysbus.h"
  30#include "qemu/error-report.h"
  31#include "qemu/timer.h"
  32#include "hw/sparc/sun4m_iommu.h"
  33#include "hw/timer/m48t59.h"
  34#include "hw/sparc/sparc32_dma.h"
  35#include "hw/block/fdc.h"
  36#include "sysemu/sysemu.h"
  37#include "net/net.h"
  38#include "hw/boards.h"
  39#include "hw/scsi/esp.h"
  40#include "hw/nvram/sun_nvram.h"
  41#include "hw/nvram/chrp_nvram.h"
  42#include "hw/nvram/fw_cfg.h"
  43#include "hw/char/escc.h"
  44#include "hw/empty_slot.h"
  45#include "hw/loader.h"
  46#include "elf.h"
  47#include "trace.h"
  48
  49/*
  50 * Sun4m architecture was used in the following machines:
  51 *
  52 * SPARCserver 6xxMP/xx
  53 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
  54 * SPARCclassic X (4/10)
  55 * SPARCstation LX/ZX (4/30)
  56 * SPARCstation Voyager
  57 * SPARCstation 10/xx, SPARCserver 10/xx
  58 * SPARCstation 5, SPARCserver 5
  59 * SPARCstation 20/xx, SPARCserver 20
  60 * SPARCstation 4
  61 *
  62 * See for example: http://www.sunhelp.org/faq/sunref1.html
  63 */
  64
  65#define KERNEL_LOAD_ADDR     0x00004000
  66#define CMDLINE_ADDR         0x007ff000
  67#define INITRD_LOAD_ADDR     0x00800000
  68#define PROM_SIZE_MAX        (1 * MiB)
  69#define PROM_VADDR           0xffd00000
  70#define PROM_FILENAME        "openbios-sparc32"
  71#define CFG_ADDR             0xd00000510ULL
  72#define FW_CFG_SUN4M_DEPTH   (FW_CFG_ARCH_LOCAL + 0x00)
  73#define FW_CFG_SUN4M_WIDTH   (FW_CFG_ARCH_LOCAL + 0x01)
  74#define FW_CFG_SUN4M_HEIGHT  (FW_CFG_ARCH_LOCAL + 0x02)
  75
  76#define MAX_CPUS 16
  77#define MAX_PILS 16
  78#define MAX_VSIMMS 4
  79
  80#define ESCC_CLOCK 4915200
  81
  82struct sun4m_hwdef {
  83    hwaddr iommu_base, iommu_pad_base, iommu_pad_len, slavio_base;
  84    hwaddr intctl_base, counter_base, nvram_base, ms_kb_base;
  85    hwaddr serial_base, fd_base;
  86    hwaddr afx_base, idreg_base, dma_base, esp_base, le_base;
  87    hwaddr tcx_base, cs_base, apc_base, aux1_base, aux2_base;
  88    hwaddr bpp_base, dbri_base, sx_base;
  89    struct {
  90        hwaddr reg_base, vram_base;
  91    } vsimm[MAX_VSIMMS];
  92    hwaddr ecc_base;
  93    uint64_t max_mem;
  94    uint32_t ecc_version;
  95    uint32_t iommu_version;
  96    uint16_t machine_id;
  97    uint8_t nvram_machine_id;
  98};
  99
 100const char *fw_cfg_arch_key_name(uint16_t key)
 101{
 102    static const struct {
 103        uint16_t key;
 104        const char *name;
 105    } fw_cfg_arch_wellknown_keys[] = {
 106        {FW_CFG_SUN4M_DEPTH, "depth"},
 107        {FW_CFG_SUN4M_WIDTH, "width"},
 108        {FW_CFG_SUN4M_HEIGHT, "height"},
 109    };
 110
 111    for (size_t i = 0; i < ARRAY_SIZE(fw_cfg_arch_wellknown_keys); i++) {
 112        if (fw_cfg_arch_wellknown_keys[i].key == key) {
 113            return fw_cfg_arch_wellknown_keys[i].name;
 114        }
 115    }
 116    return NULL;
 117}
 118
 119static void fw_cfg_boot_set(void *opaque, const char *boot_device,
 120                            Error **errp)
 121{
 122    fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
 123}
 124
 125static void nvram_init(Nvram *nvram, uint8_t *macaddr,
 126                       const char *cmdline, const char *boot_devices,
 127                       ram_addr_t RAM_size, uint32_t kernel_size,
 128                       int width, int height, int depth,
 129                       int nvram_machine_id, const char *arch)
 130{
 131    unsigned int i;
 132    int sysp_end;
 133    uint8_t image[0x1ff0];
 134    NvramClass *k = NVRAM_GET_CLASS(nvram);
 135
 136    memset(image, '\0', sizeof(image));
 137
 138    /* OpenBIOS nvram variables partition */
 139    sysp_end = chrp_nvram_create_system_partition(image, 0);
 140
 141    /* Free space partition */
 142    chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end);
 143
 144    Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
 145                    nvram_machine_id);
 146
 147    for (i = 0; i < sizeof(image); i++) {
 148        (k->write)(nvram, i, image[i]);
 149    }
 150}
 151
 152void cpu_check_irqs(CPUSPARCState *env)
 153{
 154    CPUState *cs;
 155
 156    /* We should be holding the BQL before we mess with IRQs */
 157    g_assert(qemu_mutex_iothread_locked());
 158
 159    if (env->pil_in && (env->interrupt_index == 0 ||
 160                        (env->interrupt_index & ~15) == TT_EXTINT)) {
 161        unsigned int i;
 162
 163        for (i = 15; i > 0; i--) {
 164            if (env->pil_in & (1 << i)) {
 165                int old_interrupt = env->interrupt_index;
 166
 167                env->interrupt_index = TT_EXTINT | i;
 168                if (old_interrupt != env->interrupt_index) {
 169                    cs = env_cpu(env);
 170                    trace_sun4m_cpu_interrupt(i);
 171                    cpu_interrupt(cs, CPU_INTERRUPT_HARD);
 172                }
 173                break;
 174            }
 175        }
 176    } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
 177        cs = env_cpu(env);
 178        trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15);
 179        env->interrupt_index = 0;
 180        cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
 181    }
 182}
 183
 184static void cpu_kick_irq(SPARCCPU *cpu)
 185{
 186    CPUSPARCState *env = &cpu->env;
 187    CPUState *cs = CPU(cpu);
 188
 189    cs->halted = 0;
 190    cpu_check_irqs(env);
 191    qemu_cpu_kick(cs);
 192}
 193
 194static void cpu_set_irq(void *opaque, int irq, int level)
 195{
 196    SPARCCPU *cpu = opaque;
 197    CPUSPARCState *env = &cpu->env;
 198
 199    if (level) {
 200        trace_sun4m_cpu_set_irq_raise(irq);
 201        env->pil_in |= 1 << irq;
 202        cpu_kick_irq(cpu);
 203    } else {
 204        trace_sun4m_cpu_set_irq_lower(irq);
 205        env->pil_in &= ~(1 << irq);
 206        cpu_check_irqs(env);
 207    }
 208}
 209
 210static void dummy_cpu_set_irq(void *opaque, int irq, int level)
 211{
 212}
 213
 214static void main_cpu_reset(void *opaque)
 215{
 216    SPARCCPU *cpu = opaque;
 217    CPUState *cs = CPU(cpu);
 218
 219    cpu_reset(cs);
 220    cs->halted = 0;
 221}
 222
 223static void secondary_cpu_reset(void *opaque)
 224{
 225    SPARCCPU *cpu = opaque;
 226    CPUState *cs = CPU(cpu);
 227
 228    cpu_reset(cs);
 229    cs->halted = 1;
 230}
 231
 232static void cpu_halt_signal(void *opaque, int irq, int level)
 233{
 234    if (level && current_cpu) {
 235        cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT);
 236    }
 237}
 238
 239static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
 240{
 241    return addr - 0xf0000000ULL;
 242}
 243
 244static unsigned long sun4m_load_kernel(const char *kernel_filename,
 245                                       const char *initrd_filename,
 246                                       ram_addr_t RAM_size,
 247                                       uint32_t *initrd_size)
 248{
 249    int linux_boot;
 250    unsigned int i;
 251    long kernel_size;
 252    uint8_t *ptr;
 253
 254    linux_boot = (kernel_filename != NULL);
 255
 256    kernel_size = 0;
 257    if (linux_boot) {
 258        int bswap_needed;
 259
 260#ifdef BSWAP_NEEDED
 261        bswap_needed = 1;
 262#else
 263        bswap_needed = 0;
 264#endif
 265        kernel_size = load_elf(kernel_filename, NULL,
 266                               translate_kernel_address, NULL,
 267                               NULL, NULL, NULL, 1, EM_SPARC, 0, 0);
 268        if (kernel_size < 0)
 269            kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
 270                                    RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
 271                                    TARGET_PAGE_SIZE);
 272        if (kernel_size < 0)
 273            kernel_size = load_image_targphys(kernel_filename,
 274                                              KERNEL_LOAD_ADDR,
 275                                              RAM_size - KERNEL_LOAD_ADDR);
 276        if (kernel_size < 0) {
 277            error_report("could not load kernel '%s'", kernel_filename);
 278            exit(1);
 279        }
 280
 281        /* load initrd */
 282        *initrd_size = 0;
 283        if (initrd_filename) {
 284            *initrd_size = load_image_targphys(initrd_filename,
 285                                               INITRD_LOAD_ADDR,
 286                                               RAM_size - INITRD_LOAD_ADDR);
 287            if ((int)*initrd_size < 0) {
 288                error_report("could not load initial ram disk '%s'",
 289                             initrd_filename);
 290                exit(1);
 291            }
 292        }
 293        if (*initrd_size > 0) {
 294            for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
 295                ptr = rom_ptr(KERNEL_LOAD_ADDR + i, 24);
 296                if (ptr && ldl_p(ptr) == 0x48647253) { /* HdrS */
 297                    stl_p(ptr + 16, INITRD_LOAD_ADDR);
 298                    stl_p(ptr + 20, *initrd_size);
 299                    break;
 300                }
 301            }
 302        }
 303    }
 304    return kernel_size;
 305}
 306
 307static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq)
 308{
 309    DeviceState *dev;
 310    SysBusDevice *s;
 311
 312    dev = qdev_create(NULL, TYPE_SUN4M_IOMMU);
 313    qdev_prop_set_uint32(dev, "version", version);
 314    qdev_init_nofail(dev);
 315    s = SYS_BUS_DEVICE(dev);
 316    sysbus_connect_irq(s, 0, irq);
 317    sysbus_mmio_map(s, 0, addr);
 318
 319    return s;
 320}
 321
 322static void *sparc32_dma_init(hwaddr dma_base,
 323                              hwaddr esp_base, qemu_irq espdma_irq,
 324                              hwaddr le_base, qemu_irq ledma_irq)
 325{
 326    DeviceState *dma;
 327    ESPDMADeviceState *espdma;
 328    LEDMADeviceState *ledma;
 329    SysBusESPState *esp;
 330    SysBusPCNetState *lance;
 331
 332    dma = qdev_create(NULL, TYPE_SPARC32_DMA);
 333    qdev_init_nofail(dma);
 334    sysbus_mmio_map(SYS_BUS_DEVICE(dma), 0, dma_base);
 335
 336    espdma = SPARC32_ESPDMA_DEVICE(object_resolve_path_component(
 337                                   OBJECT(dma), "espdma"));
 338    sysbus_connect_irq(SYS_BUS_DEVICE(espdma), 0, espdma_irq);
 339
 340    esp = ESP_STATE(object_resolve_path_component(OBJECT(espdma), "esp"));
 341    sysbus_mmio_map(SYS_BUS_DEVICE(esp), 0, esp_base);
 342    scsi_bus_legacy_handle_cmdline(&esp->esp.bus);
 343
 344    ledma = SPARC32_LEDMA_DEVICE(object_resolve_path_component(
 345                                 OBJECT(dma), "ledma"));
 346    sysbus_connect_irq(SYS_BUS_DEVICE(ledma), 0, ledma_irq);
 347
 348    lance = SYSBUS_PCNET(object_resolve_path_component(
 349                         OBJECT(ledma), "lance"));
 350    sysbus_mmio_map(SYS_BUS_DEVICE(lance), 0, le_base);
 351
 352    return dma;
 353}
 354
 355static DeviceState *slavio_intctl_init(hwaddr addr,
 356                                       hwaddr addrg,
 357                                       qemu_irq **parent_irq)
 358{
 359    DeviceState *dev;
 360    SysBusDevice *s;
 361    unsigned int i, j;
 362
 363    dev = qdev_create(NULL, "slavio_intctl");
 364    qdev_init_nofail(dev);
 365
 366    s = SYS_BUS_DEVICE(dev);
 367
 368    for (i = 0; i < MAX_CPUS; i++) {
 369        for (j = 0; j < MAX_PILS; j++) {
 370            sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]);
 371        }
 372    }
 373    sysbus_mmio_map(s, 0, addrg);
 374    for (i = 0; i < MAX_CPUS; i++) {
 375        sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE);
 376    }
 377
 378    return dev;
 379}
 380
 381#define SYS_TIMER_OFFSET      0x10000ULL
 382#define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
 383
 384static void slavio_timer_init_all(hwaddr addr, qemu_irq master_irq,
 385                                  qemu_irq *cpu_irqs, unsigned int num_cpus)
 386{
 387    DeviceState *dev;
 388    SysBusDevice *s;
 389    unsigned int i;
 390
 391    dev = qdev_create(NULL, "slavio_timer");
 392    qdev_prop_set_uint32(dev, "num_cpus", num_cpus);
 393    qdev_init_nofail(dev);
 394    s = SYS_BUS_DEVICE(dev);
 395    sysbus_connect_irq(s, 0, master_irq);
 396    sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);
 397
 398    for (i = 0; i < MAX_CPUS; i++) {
 399        sysbus_mmio_map(s, i + 1, addr + (hwaddr)CPU_TIMER_OFFSET(i));
 400        sysbus_connect_irq(s, i + 1, cpu_irqs[i]);
 401    }
 402}
 403
 404static qemu_irq  slavio_system_powerdown;
 405
 406static void slavio_powerdown_req(Notifier *n, void *opaque)
 407{
 408    qemu_irq_raise(slavio_system_powerdown);
 409}
 410
 411static Notifier slavio_system_powerdown_notifier = {
 412    .notify = slavio_powerdown_req
 413};
 414
 415#define MISC_LEDS 0x01600000
 416#define MISC_CFG  0x01800000
 417#define MISC_DIAG 0x01a00000
 418#define MISC_MDM  0x01b00000
 419#define MISC_SYS  0x01f00000
 420
 421static void slavio_misc_init(hwaddr base,
 422                             hwaddr aux1_base,
 423                             hwaddr aux2_base, qemu_irq irq,
 424                             qemu_irq fdc_tc)
 425{
 426    DeviceState *dev;
 427    SysBusDevice *s;
 428
 429    dev = qdev_create(NULL, "slavio_misc");
 430    qdev_init_nofail(dev);
 431    s = SYS_BUS_DEVICE(dev);
 432    if (base) {
 433        /* 8 bit registers */
 434        /* Slavio control */
 435        sysbus_mmio_map(s, 0, base + MISC_CFG);
 436        /* Diagnostics */
 437        sysbus_mmio_map(s, 1, base + MISC_DIAG);
 438        /* Modem control */
 439        sysbus_mmio_map(s, 2, base + MISC_MDM);
 440        /* 16 bit registers */
 441        /* ss600mp diag LEDs */
 442        sysbus_mmio_map(s, 3, base + MISC_LEDS);
 443        /* 32 bit registers */
 444        /* System control */
 445        sysbus_mmio_map(s, 4, base + MISC_SYS);
 446    }
 447    if (aux1_base) {
 448        /* AUX 1 (Misc System Functions) */
 449        sysbus_mmio_map(s, 5, aux1_base);
 450    }
 451    if (aux2_base) {
 452        /* AUX 2 (Software Powerdown Control) */
 453        sysbus_mmio_map(s, 6, aux2_base);
 454    }
 455    sysbus_connect_irq(s, 0, irq);
 456    sysbus_connect_irq(s, 1, fdc_tc);
 457    slavio_system_powerdown = qdev_get_gpio_in(dev, 0);
 458    qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier);
 459}
 460
 461static void ecc_init(hwaddr base, qemu_irq irq, uint32_t version)
 462{
 463    DeviceState *dev;
 464    SysBusDevice *s;
 465
 466    dev = qdev_create(NULL, "eccmemctl");
 467    qdev_prop_set_uint32(dev, "version", version);
 468    qdev_init_nofail(dev);
 469    s = SYS_BUS_DEVICE(dev);
 470    sysbus_connect_irq(s, 0, irq);
 471    sysbus_mmio_map(s, 0, base);
 472    if (version == 0) { // SS-600MP only
 473        sysbus_mmio_map(s, 1, base + 0x1000);
 474    }
 475}
 476
 477static void apc_init(hwaddr power_base, qemu_irq cpu_halt)
 478{
 479    DeviceState *dev;
 480    SysBusDevice *s;
 481
 482    dev = qdev_create(NULL, "apc");
 483    qdev_init_nofail(dev);
 484    s = SYS_BUS_DEVICE(dev);
 485    /* Power management (APC) XXX: not a Slavio device */
 486    sysbus_mmio_map(s, 0, power_base);
 487    sysbus_connect_irq(s, 0, cpu_halt);
 488}
 489
 490static void tcx_init(hwaddr addr, qemu_irq irq, int vram_size, int width,
 491                     int height, int depth)
 492{
 493    DeviceState *dev;
 494    SysBusDevice *s;
 495
 496    dev = qdev_create(NULL, "SUNW,tcx");
 497    qdev_prop_set_uint32(dev, "vram_size", vram_size);
 498    qdev_prop_set_uint16(dev, "width", width);
 499    qdev_prop_set_uint16(dev, "height", height);
 500    qdev_prop_set_uint16(dev, "depth", depth);
 501    qdev_init_nofail(dev);
 502    s = SYS_BUS_DEVICE(dev);
 503
 504    /* 10/ROM : FCode ROM */
 505    sysbus_mmio_map(s, 0, addr);
 506    /* 2/STIP : Stipple */
 507    sysbus_mmio_map(s, 1, addr + 0x04000000ULL);
 508    /* 3/BLIT : Blitter */
 509    sysbus_mmio_map(s, 2, addr + 0x06000000ULL);
 510    /* 5/RSTIP : Raw Stipple */
 511    sysbus_mmio_map(s, 3, addr + 0x0c000000ULL);
 512    /* 6/RBLIT : Raw Blitter */
 513    sysbus_mmio_map(s, 4, addr + 0x0e000000ULL);
 514    /* 7/TEC : Transform Engine */
 515    sysbus_mmio_map(s, 5, addr + 0x00700000ULL);
 516    /* 8/CMAP  : DAC */
 517    sysbus_mmio_map(s, 6, addr + 0x00200000ULL);
 518    /* 9/THC : */
 519    if (depth == 8) {
 520        sysbus_mmio_map(s, 7, addr + 0x00300000ULL);
 521    } else {
 522        sysbus_mmio_map(s, 7, addr + 0x00301000ULL);
 523    }
 524    /* 11/DHC : */
 525    sysbus_mmio_map(s, 8, addr + 0x00240000ULL);
 526    /* 12/ALT : */
 527    sysbus_mmio_map(s, 9, addr + 0x00280000ULL);
 528    /* 0/DFB8 : 8-bit plane */
 529    sysbus_mmio_map(s, 10, addr + 0x00800000ULL);
 530    /* 1/DFB24 : 24bit plane */
 531    sysbus_mmio_map(s, 11, addr + 0x02000000ULL);
 532    /* 4/RDFB32: Raw framebuffer. Control plane */
 533    sysbus_mmio_map(s, 12, addr + 0x0a000000ULL);
 534    /* 9/THC24bits : NetBSD writes here even with 8-bit display: dummy */
 535    if (depth == 8) {
 536        sysbus_mmio_map(s, 13, addr + 0x00301000ULL);
 537    }
 538
 539    sysbus_connect_irq(s, 0, irq);
 540}
 541
 542static void cg3_init(hwaddr addr, qemu_irq irq, int vram_size, int width,
 543                     int height, int depth)
 544{
 545    DeviceState *dev;
 546    SysBusDevice *s;
 547
 548    dev = qdev_create(NULL, "cgthree");
 549    qdev_prop_set_uint32(dev, "vram-size", vram_size);
 550    qdev_prop_set_uint16(dev, "width", width);
 551    qdev_prop_set_uint16(dev, "height", height);
 552    qdev_prop_set_uint16(dev, "depth", depth);
 553    qdev_init_nofail(dev);
 554    s = SYS_BUS_DEVICE(dev);
 555
 556    /* FCode ROM */
 557    sysbus_mmio_map(s, 0, addr);
 558    /* DAC */
 559    sysbus_mmio_map(s, 1, addr + 0x400000ULL);
 560    /* 8-bit plane */
 561    sysbus_mmio_map(s, 2, addr + 0x800000ULL);
 562
 563    sysbus_connect_irq(s, 0, irq);
 564}
 565
 566/* NCR89C100/MACIO Internal ID register */
 567
 568#define TYPE_MACIO_ID_REGISTER "macio_idreg"
 569
 570static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
 571
 572static void idreg_init(hwaddr addr)
 573{
 574    DeviceState *dev;
 575    SysBusDevice *s;
 576
 577    dev = qdev_create(NULL, TYPE_MACIO_ID_REGISTER);
 578    qdev_init_nofail(dev);
 579    s = SYS_BUS_DEVICE(dev);
 580
 581    sysbus_mmio_map(s, 0, addr);
 582    address_space_write_rom(&address_space_memory, addr,
 583                            MEMTXATTRS_UNSPECIFIED,
 584                            idreg_data, sizeof(idreg_data));
 585}
 586
 587#define MACIO_ID_REGISTER(obj) \
 588    OBJECT_CHECK(IDRegState, (obj), TYPE_MACIO_ID_REGISTER)
 589
 590typedef struct IDRegState {
 591    SysBusDevice parent_obj;
 592
 593    MemoryRegion mem;
 594} IDRegState;
 595
 596static void idreg_realize(DeviceState *ds, Error **errp)
 597{
 598    IDRegState *s = MACIO_ID_REGISTER(ds);
 599    SysBusDevice *dev = SYS_BUS_DEVICE(ds);
 600    Error *local_err = NULL;
 601
 602    memory_region_init_ram_nomigrate(&s->mem, OBJECT(ds), "sun4m.idreg",
 603                                     sizeof(idreg_data), &local_err);
 604    if (local_err) {
 605        error_propagate(errp, local_err);
 606        return;
 607    }
 608
 609    vmstate_register_ram_global(&s->mem);
 610    memory_region_set_readonly(&s->mem, true);
 611    sysbus_init_mmio(dev, &s->mem);
 612}
 613
 614static void idreg_class_init(ObjectClass *oc, void *data)
 615{
 616    DeviceClass *dc = DEVICE_CLASS(oc);
 617
 618    dc->realize = idreg_realize;
 619}
 620
 621static const TypeInfo idreg_info = {
 622    .name          = TYPE_MACIO_ID_REGISTER,
 623    .parent        = TYPE_SYS_BUS_DEVICE,
 624    .instance_size = sizeof(IDRegState),
 625    .class_init    = idreg_class_init,
 626};
 627
 628#define TYPE_TCX_AFX "tcx_afx"
 629#define TCX_AFX(obj) OBJECT_CHECK(AFXState, (obj), TYPE_TCX_AFX)
 630
 631typedef struct AFXState {
 632    SysBusDevice parent_obj;
 633
 634    MemoryRegion mem;
 635} AFXState;
 636
 637/* SS-5 TCX AFX register */
 638static void afx_init(hwaddr addr)
 639{
 640    DeviceState *dev;
 641    SysBusDevice *s;
 642
 643    dev = qdev_create(NULL, TYPE_TCX_AFX);
 644    qdev_init_nofail(dev);
 645    s = SYS_BUS_DEVICE(dev);
 646
 647    sysbus_mmio_map(s, 0, addr);
 648}
 649
 650static void afx_realize(DeviceState *ds, Error **errp)
 651{
 652    AFXState *s = TCX_AFX(ds);
 653    SysBusDevice *dev = SYS_BUS_DEVICE(ds);
 654    Error *local_err = NULL;
 655
 656    memory_region_init_ram_nomigrate(&s->mem, OBJECT(ds), "sun4m.afx", 4,
 657                                     &local_err);
 658    if (local_err) {
 659        error_propagate(errp, local_err);
 660        return;
 661    }
 662
 663    vmstate_register_ram_global(&s->mem);
 664    sysbus_init_mmio(dev, &s->mem);
 665}
 666
 667static void afx_class_init(ObjectClass *oc, void *data)
 668{
 669    DeviceClass *dc = DEVICE_CLASS(oc);
 670
 671    dc->realize = afx_realize;
 672}
 673
 674static const TypeInfo afx_info = {
 675    .name          = TYPE_TCX_AFX,
 676    .parent        = TYPE_SYS_BUS_DEVICE,
 677    .instance_size = sizeof(AFXState),
 678    .class_init    = afx_class_init,
 679};
 680
 681#define TYPE_OPENPROM "openprom"
 682#define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM)
 683
 684typedef struct PROMState {
 685    SysBusDevice parent_obj;
 686
 687    MemoryRegion prom;
 688} PROMState;
 689
 690/* Boot PROM (OpenBIOS) */
 691static uint64_t translate_prom_address(void *opaque, uint64_t addr)
 692{
 693    hwaddr *base_addr = (hwaddr *)opaque;
 694    return addr + *base_addr - PROM_VADDR;
 695}
 696
 697static void prom_init(hwaddr addr, const char *bios_name)
 698{
 699    DeviceState *dev;
 700    SysBusDevice *s;
 701    char *filename;
 702    int ret;
 703
 704    dev = qdev_create(NULL, TYPE_OPENPROM);
 705    qdev_init_nofail(dev);
 706    s = SYS_BUS_DEVICE(dev);
 707
 708    sysbus_mmio_map(s, 0, addr);
 709
 710    /* load boot prom */
 711    if (bios_name == NULL) {
 712        bios_name = PROM_FILENAME;
 713    }
 714    filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 715    if (filename) {
 716        ret = load_elf(filename, NULL,
 717                       translate_prom_address, &addr, NULL,
 718                       NULL, NULL, 1, EM_SPARC, 0, 0);
 719        if (ret < 0 || ret > PROM_SIZE_MAX) {
 720            ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
 721        }
 722        g_free(filename);
 723    } else {
 724        ret = -1;
 725    }
 726    if (ret < 0 || ret > PROM_SIZE_MAX) {
 727        error_report("could not load prom '%s'", bios_name);
 728        exit(1);
 729    }
 730}
 731
 732static void prom_realize(DeviceState *ds, Error **errp)
 733{
 734    PROMState *s = OPENPROM(ds);
 735    SysBusDevice *dev = SYS_BUS_DEVICE(ds);
 736    Error *local_err = NULL;
 737
 738    memory_region_init_ram_nomigrate(&s->prom, OBJECT(ds), "sun4m.prom",
 739                                     PROM_SIZE_MAX, &local_err);
 740    if (local_err) {
 741        error_propagate(errp, local_err);
 742        return;
 743    }
 744
 745    vmstate_register_ram_global(&s->prom);
 746    memory_region_set_readonly(&s->prom, true);
 747    sysbus_init_mmio(dev, &s->prom);
 748}
 749
 750static Property prom_properties[] = {
 751    {/* end of property list */},
 752};
 753
 754static void prom_class_init(ObjectClass *klass, void *data)
 755{
 756    DeviceClass *dc = DEVICE_CLASS(klass);
 757
 758    dc->props = prom_properties;
 759    dc->realize = prom_realize;
 760}
 761
 762static const TypeInfo prom_info = {
 763    .name          = TYPE_OPENPROM,
 764    .parent        = TYPE_SYS_BUS_DEVICE,
 765    .instance_size = sizeof(PROMState),
 766    .class_init    = prom_class_init,
 767};
 768
 769#define TYPE_SUN4M_MEMORY "memory"
 770#define SUN4M_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4M_MEMORY)
 771
 772typedef struct RamDevice {
 773    SysBusDevice parent_obj;
 774
 775    MemoryRegion ram;
 776    uint64_t size;
 777} RamDevice;
 778
 779/* System RAM */
 780static void ram_realize(DeviceState *dev, Error **errp)
 781{
 782    RamDevice *d = SUN4M_RAM(dev);
 783    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 784
 785    memory_region_allocate_system_memory(&d->ram, OBJECT(d), "sun4m.ram",
 786                                         d->size);
 787    sysbus_init_mmio(sbd, &d->ram);
 788}
 789
 790static void ram_init(hwaddr addr, ram_addr_t RAM_size,
 791                     uint64_t max_mem)
 792{
 793    DeviceState *dev;
 794    SysBusDevice *s;
 795    RamDevice *d;
 796
 797    /* allocate RAM */
 798    if ((uint64_t)RAM_size > max_mem) {
 799        error_report("Too much memory for this machine: %" PRId64 ","
 800                     " maximum %" PRId64,
 801                     RAM_size / MiB, max_mem / MiB);
 802        exit(1);
 803    }
 804    dev = qdev_create(NULL, "memory");
 805    s = SYS_BUS_DEVICE(dev);
 806
 807    d = SUN4M_RAM(dev);
 808    d->size = RAM_size;
 809    qdev_init_nofail(dev);
 810
 811    sysbus_mmio_map(s, 0, addr);
 812}
 813
 814static Property ram_properties[] = {
 815    DEFINE_PROP_UINT64("size", RamDevice, size, 0),
 816    DEFINE_PROP_END_OF_LIST(),
 817};
 818
 819static void ram_class_init(ObjectClass *klass, void *data)
 820{
 821    DeviceClass *dc = DEVICE_CLASS(klass);
 822
 823    dc->realize = ram_realize;
 824    dc->props = ram_properties;
 825}
 826
 827static const TypeInfo ram_info = {
 828    .name          = TYPE_SUN4M_MEMORY,
 829    .parent        = TYPE_SYS_BUS_DEVICE,
 830    .instance_size = sizeof(RamDevice),
 831    .class_init    = ram_class_init,
 832};
 833
 834static void cpu_devinit(const char *cpu_type, unsigned int id,
 835                        uint64_t prom_addr, qemu_irq **cpu_irqs)
 836{
 837    CPUState *cs;
 838    SPARCCPU *cpu;
 839    CPUSPARCState *env;
 840
 841    cpu = SPARC_CPU(cpu_create(cpu_type));
 842    env = &cpu->env;
 843
 844    cpu_sparc_set_id(env, id);
 845    if (id == 0) {
 846        qemu_register_reset(main_cpu_reset, cpu);
 847    } else {
 848        qemu_register_reset(secondary_cpu_reset, cpu);
 849        cs = CPU(cpu);
 850        cs->halted = 1;
 851    }
 852    *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS);
 853    env->prom_addr = prom_addr;
 854}
 855
 856static void dummy_fdc_tc(void *opaque, int irq, int level)
 857{
 858}
 859
 860static void sun4m_hw_init(const struct sun4m_hwdef *hwdef,
 861                          MachineState *machine)
 862{
 863    DeviceState *slavio_intctl;
 864    unsigned int i;
 865    void *nvram;
 866    qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS];
 867    qemu_irq fdc_tc;
 868    unsigned long kernel_size;
 869    uint32_t initrd_size;
 870    DriveInfo *fd[MAX_FD];
 871    FWCfgState *fw_cfg;
 872    DeviceState *dev;
 873    SysBusDevice *s;
 874    unsigned int smp_cpus = machine->smp.cpus;
 875    unsigned int max_cpus = machine->smp.max_cpus;
 876
 877    /* init CPUs */
 878    for(i = 0; i < smp_cpus; i++) {
 879        cpu_devinit(machine->cpu_type, i, hwdef->slavio_base, &cpu_irqs[i]);
 880    }
 881
 882    for (i = smp_cpus; i < MAX_CPUS; i++)
 883        cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
 884
 885
 886    /* set up devices */
 887    ram_init(0, machine->ram_size, hwdef->max_mem);
 888    /* models without ECC don't trap when missing ram is accessed */
 889    if (!hwdef->ecc_base) {
 890        empty_slot_init(machine->ram_size, hwdef->max_mem - machine->ram_size);
 891    }
 892
 893    prom_init(hwdef->slavio_base, bios_name);
 894
 895    slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
 896                                       hwdef->intctl_base + 0x10000ULL,
 897                                       cpu_irqs);
 898
 899    for (i = 0; i < 32; i++) {
 900        slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i);
 901    }
 902    for (i = 0; i < MAX_CPUS; i++) {
 903        slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i);
 904    }
 905
 906    if (hwdef->idreg_base) {
 907        idreg_init(hwdef->idreg_base);
 908    }
 909
 910    if (hwdef->afx_base) {
 911        afx_init(hwdef->afx_base);
 912    }
 913
 914    iommu_init(hwdef->iommu_base, hwdef->iommu_version, slavio_irq[30]);
 915
 916    if (hwdef->iommu_pad_base) {
 917        /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased.
 918           Software shouldn't use aliased addresses, neither should it crash
 919           when does. Using empty_slot instead of aliasing can help with
 920           debugging such accesses */
 921        empty_slot_init(hwdef->iommu_pad_base,hwdef->iommu_pad_len);
 922    }
 923
 924    sparc32_dma_init(hwdef->dma_base,
 925                     hwdef->esp_base, slavio_irq[18],
 926                     hwdef->le_base, slavio_irq[16]);
 927
 928    if (graphic_depth != 8 && graphic_depth != 24) {
 929        error_report("Unsupported depth: %d", graphic_depth);
 930        exit (1);
 931    }
 932    if (vga_interface_type != VGA_NONE) {
 933        if (vga_interface_type == VGA_CG3) {
 934            if (graphic_depth != 8) {
 935                error_report("Unsupported depth: %d", graphic_depth);
 936                exit(1);
 937            }
 938
 939            if (!(graphic_width == 1024 && graphic_height == 768) &&
 940                !(graphic_width == 1152 && graphic_height == 900)) {
 941                error_report("Unsupported resolution: %d x %d", graphic_width,
 942                             graphic_height);
 943                exit(1);
 944            }
 945
 946            /* sbus irq 5 */
 947            cg3_init(hwdef->tcx_base, slavio_irq[11], 0x00100000,
 948                     graphic_width, graphic_height, graphic_depth);
 949        } else {
 950            /* If no display specified, default to TCX */
 951            if (graphic_depth != 8 && graphic_depth != 24) {
 952                error_report("Unsupported depth: %d", graphic_depth);
 953                exit(1);
 954            }
 955
 956            if (!(graphic_width == 1024 && graphic_height == 768)) {
 957                error_report("Unsupported resolution: %d x %d",
 958                             graphic_width, graphic_height);
 959                exit(1);
 960            }
 961
 962            tcx_init(hwdef->tcx_base, slavio_irq[11], 0x00100000,
 963                     graphic_width, graphic_height, graphic_depth);
 964        }
 965    }
 966
 967    for (i = 0; i < MAX_VSIMMS; i++) {
 968        /* vsimm registers probed by OBP */
 969        if (hwdef->vsimm[i].reg_base) {
 970            empty_slot_init(hwdef->vsimm[i].reg_base, 0x2000);
 971        }
 972    }
 973
 974    if (hwdef->sx_base) {
 975        empty_slot_init(hwdef->sx_base, 0x2000);
 976    }
 977
 978    nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 1968, 8);
 979
 980    slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus);
 981
 982    /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
 983       Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
 984    dev = qdev_create(NULL, TYPE_ESCC);
 985    qdev_prop_set_uint32(dev, "disabled", !machine->enable_graphics);
 986    qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK);
 987    qdev_prop_set_uint32(dev, "it_shift", 1);
 988    qdev_prop_set_chr(dev, "chrB", NULL);
 989    qdev_prop_set_chr(dev, "chrA", NULL);
 990    qdev_prop_set_uint32(dev, "chnBtype", escc_mouse);
 991    qdev_prop_set_uint32(dev, "chnAtype", escc_kbd);
 992    qdev_init_nofail(dev);
 993    s = SYS_BUS_DEVICE(dev);
 994    sysbus_connect_irq(s, 0, slavio_irq[14]);
 995    sysbus_connect_irq(s, 1, slavio_irq[14]);
 996    sysbus_mmio_map(s, 0, hwdef->ms_kb_base);
 997
 998    dev = qdev_create(NULL, TYPE_ESCC);
 999    qdev_prop_set_uint32(dev, "disabled", 0);
1000    qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK);
1001    qdev_prop_set_uint32(dev, "it_shift", 1);
1002    qdev_prop_set_chr(dev, "chrB", serial_hd(1));
1003    qdev_prop_set_chr(dev, "chrA", serial_hd(0));
1004    qdev_prop_set_uint32(dev, "chnBtype", escc_serial);
1005    qdev_prop_set_uint32(dev, "chnAtype", escc_serial);
1006    qdev_init_nofail(dev);
1007
1008    s = SYS_BUS_DEVICE(dev);
1009    sysbus_connect_irq(s, 0, slavio_irq[15]);
1010    sysbus_connect_irq(s, 1,  slavio_irq[15]);
1011    sysbus_mmio_map(s, 0, hwdef->serial_base);
1012
1013    if (hwdef->apc_base) {
1014        apc_init(hwdef->apc_base, qemu_allocate_irq(cpu_halt_signal, NULL, 0));
1015    }
1016
1017    if (hwdef->fd_base) {
1018        /* there is zero or one floppy drive */
1019        memset(fd, 0, sizeof(fd));
1020        fd[0] = drive_get(IF_FLOPPY, 0, 0);
1021        sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd,
1022                          &fdc_tc);
1023    } else {
1024        fdc_tc = qemu_allocate_irq(dummy_fdc_tc, NULL, 0);
1025    }
1026
1027    slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base,
1028                     slavio_irq[30], fdc_tc);
1029
1030    if (hwdef->cs_base) {
1031        sysbus_create_simple("SUNW,CS4231", hwdef->cs_base,
1032                             slavio_irq[5]);
1033    }
1034
1035    if (hwdef->dbri_base) {
1036        /* ISDN chip with attached CS4215 audio codec */
1037        /* prom space */
1038        empty_slot_init(hwdef->dbri_base+0x1000, 0x30);
1039        /* reg space */
1040        empty_slot_init(hwdef->dbri_base+0x10000, 0x100);
1041    }
1042
1043    if (hwdef->bpp_base) {
1044        /* parallel port */
1045        empty_slot_init(hwdef->bpp_base, 0x20);
1046    }
1047
1048    initrd_size = 0;
1049    kernel_size = sun4m_load_kernel(machine->kernel_filename,
1050                                    machine->initrd_filename,
1051                                    machine->ram_size, &initrd_size);
1052
1053    nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, machine->kernel_cmdline,
1054               machine->boot_order, machine->ram_size, kernel_size,
1055               graphic_width, graphic_height, graphic_depth,
1056               hwdef->nvram_machine_id, "Sun4m");
1057
1058    if (hwdef->ecc_base)
1059        ecc_init(hwdef->ecc_base, slavio_irq[28],
1060                 hwdef->ecc_version);
1061
1062    dev = qdev_create(NULL, TYPE_FW_CFG_MEM);
1063    fw_cfg = FW_CFG(dev);
1064    qdev_prop_set_uint32(dev, "data_width", 1);
1065    qdev_prop_set_bit(dev, "dma_enabled", false);
1066    object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG,
1067                              OBJECT(fw_cfg), NULL);
1068    qdev_init_nofail(dev);
1069    s = SYS_BUS_DEVICE(dev);
1070    sysbus_mmio_map(s, 0, CFG_ADDR);
1071    sysbus_mmio_map(s, 1, CFG_ADDR + 2);
1072
1073    fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
1074    fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
1075    fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1076    fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1077    fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1078    fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_WIDTH, graphic_width);
1079    fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_HEIGHT, graphic_height);
1080    fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1081    fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1082    if (machine->kernel_cmdline) {
1083        fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1084        pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE,
1085                         machine->kernel_cmdline);
1086        fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline);
1087        fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
1088                       strlen(machine->kernel_cmdline) + 1);
1089    } else {
1090        fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1091        fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
1092    }
1093    fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1094    fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
1095    fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]);
1096    qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1097}
1098
1099enum {
1100    ss5_id = 32,
1101    vger_id,
1102    lx_id,
1103    ss4_id,
1104    scls_id,
1105    sbook_id,
1106    ss10_id = 64,
1107    ss20_id,
1108    ss600mp_id,
1109};
1110
1111static const struct sun4m_hwdef sun4m_hwdefs[] = {
1112    /* SS-5 */
1113    {
1114        .iommu_base   = 0x10000000,
1115        .iommu_pad_base = 0x10004000,
1116        .iommu_pad_len  = 0x0fffb000,
1117        .tcx_base     = 0x50000000,
1118        .cs_base      = 0x6c000000,
1119        .slavio_base  = 0x70000000,
1120        .ms_kb_base   = 0x71000000,
1121        .serial_base  = 0x71100000,
1122        .nvram_base   = 0x71200000,
1123        .fd_base      = 0x71400000,
1124        .counter_base = 0x71d00000,
1125        .intctl_base  = 0x71e00000,
1126        .idreg_base   = 0x78000000,
1127        .dma_base     = 0x78400000,
1128        .esp_base     = 0x78800000,
1129        .le_base      = 0x78c00000,
1130        .apc_base     = 0x6a000000,
1131        .afx_base     = 0x6e000000,
1132        .aux1_base    = 0x71900000,
1133        .aux2_base    = 0x71910000,
1134        .nvram_machine_id = 0x80,
1135        .machine_id = ss5_id,
1136        .iommu_version = 0x05000000,
1137        .max_mem = 0x10000000,
1138    },
1139    /* SS-10 */
1140    {
1141        .iommu_base   = 0xfe0000000ULL,
1142        .tcx_base     = 0xe20000000ULL,
1143        .slavio_base  = 0xff0000000ULL,
1144        .ms_kb_base   = 0xff1000000ULL,
1145        .serial_base  = 0xff1100000ULL,
1146        .nvram_base   = 0xff1200000ULL,
1147        .fd_base      = 0xff1700000ULL,
1148        .counter_base = 0xff1300000ULL,
1149        .intctl_base  = 0xff1400000ULL,
1150        .idreg_base   = 0xef0000000ULL,
1151        .dma_base     = 0xef0400000ULL,
1152        .esp_base     = 0xef0800000ULL,
1153        .le_base      = 0xef0c00000ULL,
1154        .apc_base     = 0xefa000000ULL, // XXX should not exist
1155        .aux1_base    = 0xff1800000ULL,
1156        .aux2_base    = 0xff1a01000ULL,
1157        .ecc_base     = 0xf00000000ULL,
1158        .ecc_version  = 0x10000000, // version 0, implementation 1
1159        .nvram_machine_id = 0x72,
1160        .machine_id = ss10_id,
1161        .iommu_version = 0x03000000,
1162        .max_mem = 0xf00000000ULL,
1163    },
1164    /* SS-600MP */
1165    {
1166        .iommu_base   = 0xfe0000000ULL,
1167        .tcx_base     = 0xe20000000ULL,
1168        .slavio_base  = 0xff0000000ULL,
1169        .ms_kb_base   = 0xff1000000ULL,
1170        .serial_base  = 0xff1100000ULL,
1171        .nvram_base   = 0xff1200000ULL,
1172        .counter_base = 0xff1300000ULL,
1173        .intctl_base  = 0xff1400000ULL,
1174        .dma_base     = 0xef0081000ULL,
1175        .esp_base     = 0xef0080000ULL,
1176        .le_base      = 0xef0060000ULL,
1177        .apc_base     = 0xefa000000ULL, // XXX should not exist
1178        .aux1_base    = 0xff1800000ULL,
1179        .aux2_base    = 0xff1a01000ULL, // XXX should not exist
1180        .ecc_base     = 0xf00000000ULL,
1181        .ecc_version  = 0x00000000, // version 0, implementation 0
1182        .nvram_machine_id = 0x71,
1183        .machine_id = ss600mp_id,
1184        .iommu_version = 0x01000000,
1185        .max_mem = 0xf00000000ULL,
1186    },
1187    /* SS-20 */
1188    {
1189        .iommu_base   = 0xfe0000000ULL,
1190        .tcx_base     = 0xe20000000ULL,
1191        .slavio_base  = 0xff0000000ULL,
1192        .ms_kb_base   = 0xff1000000ULL,
1193        .serial_base  = 0xff1100000ULL,
1194        .nvram_base   = 0xff1200000ULL,
1195        .fd_base      = 0xff1700000ULL,
1196        .counter_base = 0xff1300000ULL,
1197        .intctl_base  = 0xff1400000ULL,
1198        .idreg_base   = 0xef0000000ULL,
1199        .dma_base     = 0xef0400000ULL,
1200        .esp_base     = 0xef0800000ULL,
1201        .le_base      = 0xef0c00000ULL,
1202        .bpp_base     = 0xef4800000ULL,
1203        .apc_base     = 0xefa000000ULL, // XXX should not exist
1204        .aux1_base    = 0xff1800000ULL,
1205        .aux2_base    = 0xff1a01000ULL,
1206        .dbri_base    = 0xee0000000ULL,
1207        .sx_base      = 0xf80000000ULL,
1208        .vsimm        = {
1209            {
1210                .reg_base  = 0x9c000000ULL,
1211                .vram_base = 0xfc000000ULL
1212            }, {
1213                .reg_base  = 0x90000000ULL,
1214                .vram_base = 0xf0000000ULL
1215            }, {
1216                .reg_base  = 0x94000000ULL
1217            }, {
1218                .reg_base  = 0x98000000ULL
1219            }
1220        },
1221        .ecc_base     = 0xf00000000ULL,
1222        .ecc_version  = 0x20000000, // version 0, implementation 2
1223        .nvram_machine_id = 0x72,
1224        .machine_id = ss20_id,
1225        .iommu_version = 0x13000000,
1226        .max_mem = 0xf00000000ULL,
1227    },
1228    /* Voyager */
1229    {
1230        .iommu_base   = 0x10000000,
1231        .tcx_base     = 0x50000000,
1232        .slavio_base  = 0x70000000,
1233        .ms_kb_base   = 0x71000000,
1234        .serial_base  = 0x71100000,
1235        .nvram_base   = 0x71200000,
1236        .fd_base      = 0x71400000,
1237        .counter_base = 0x71d00000,
1238        .intctl_base  = 0x71e00000,
1239        .idreg_base   = 0x78000000,
1240        .dma_base     = 0x78400000,
1241        .esp_base     = 0x78800000,
1242        .le_base      = 0x78c00000,
1243        .apc_base     = 0x71300000, // pmc
1244        .aux1_base    = 0x71900000,
1245        .aux2_base    = 0x71910000,
1246        .nvram_machine_id = 0x80,
1247        .machine_id = vger_id,
1248        .iommu_version = 0x05000000,
1249        .max_mem = 0x10000000,
1250    },
1251    /* LX */
1252    {
1253        .iommu_base   = 0x10000000,
1254        .iommu_pad_base = 0x10004000,
1255        .iommu_pad_len  = 0x0fffb000,
1256        .tcx_base     = 0x50000000,
1257        .slavio_base  = 0x70000000,
1258        .ms_kb_base   = 0x71000000,
1259        .serial_base  = 0x71100000,
1260        .nvram_base   = 0x71200000,
1261        .fd_base      = 0x71400000,
1262        .counter_base = 0x71d00000,
1263        .intctl_base  = 0x71e00000,
1264        .idreg_base   = 0x78000000,
1265        .dma_base     = 0x78400000,
1266        .esp_base     = 0x78800000,
1267        .le_base      = 0x78c00000,
1268        .aux1_base    = 0x71900000,
1269        .aux2_base    = 0x71910000,
1270        .nvram_machine_id = 0x80,
1271        .machine_id = lx_id,
1272        .iommu_version = 0x04000000,
1273        .max_mem = 0x10000000,
1274    },
1275    /* SS-4 */
1276    {
1277        .iommu_base   = 0x10000000,
1278        .tcx_base     = 0x50000000,
1279        .cs_base      = 0x6c000000,
1280        .slavio_base  = 0x70000000,
1281        .ms_kb_base   = 0x71000000,
1282        .serial_base  = 0x71100000,
1283        .nvram_base   = 0x71200000,
1284        .fd_base      = 0x71400000,
1285        .counter_base = 0x71d00000,
1286        .intctl_base  = 0x71e00000,
1287        .idreg_base   = 0x78000000,
1288        .dma_base     = 0x78400000,
1289        .esp_base     = 0x78800000,
1290        .le_base      = 0x78c00000,
1291        .apc_base     = 0x6a000000,
1292        .aux1_base    = 0x71900000,
1293        .aux2_base    = 0x71910000,
1294        .nvram_machine_id = 0x80,
1295        .machine_id = ss4_id,
1296        .iommu_version = 0x05000000,
1297        .max_mem = 0x10000000,
1298    },
1299    /* SPARCClassic */
1300    {
1301        .iommu_base   = 0x10000000,
1302        .tcx_base     = 0x50000000,
1303        .slavio_base  = 0x70000000,
1304        .ms_kb_base   = 0x71000000,
1305        .serial_base  = 0x71100000,
1306        .nvram_base   = 0x71200000,
1307        .fd_base      = 0x71400000,
1308        .counter_base = 0x71d00000,
1309        .intctl_base  = 0x71e00000,
1310        .idreg_base   = 0x78000000,
1311        .dma_base     = 0x78400000,
1312        .esp_base     = 0x78800000,
1313        .le_base      = 0x78c00000,
1314        .apc_base     = 0x6a000000,
1315        .aux1_base    = 0x71900000,
1316        .aux2_base    = 0x71910000,
1317        .nvram_machine_id = 0x80,
1318        .machine_id = scls_id,
1319        .iommu_version = 0x05000000,
1320        .max_mem = 0x10000000,
1321    },
1322    /* SPARCbook */
1323    {
1324        .iommu_base   = 0x10000000,
1325        .tcx_base     = 0x50000000, // XXX
1326        .slavio_base  = 0x70000000,
1327        .ms_kb_base   = 0x71000000,
1328        .serial_base  = 0x71100000,
1329        .nvram_base   = 0x71200000,
1330        .fd_base      = 0x71400000,
1331        .counter_base = 0x71d00000,
1332        .intctl_base  = 0x71e00000,
1333        .idreg_base   = 0x78000000,
1334        .dma_base     = 0x78400000,
1335        .esp_base     = 0x78800000,
1336        .le_base      = 0x78c00000,
1337        .apc_base     = 0x6a000000,
1338        .aux1_base    = 0x71900000,
1339        .aux2_base    = 0x71910000,
1340        .nvram_machine_id = 0x80,
1341        .machine_id = sbook_id,
1342        .iommu_version = 0x05000000,
1343        .max_mem = 0x10000000,
1344    },
1345};
1346
1347/* SPARCstation 5 hardware initialisation */
1348static void ss5_init(MachineState *machine)
1349{
1350    sun4m_hw_init(&sun4m_hwdefs[0], machine);
1351}
1352
1353/* SPARCstation 10 hardware initialisation */
1354static void ss10_init(MachineState *machine)
1355{
1356    sun4m_hw_init(&sun4m_hwdefs[1], machine);
1357}
1358
1359/* SPARCserver 600MP hardware initialisation */
1360static void ss600mp_init(MachineState *machine)
1361{
1362    sun4m_hw_init(&sun4m_hwdefs[2], machine);
1363}
1364
1365/* SPARCstation 20 hardware initialisation */
1366static void ss20_init(MachineState *machine)
1367{
1368    sun4m_hw_init(&sun4m_hwdefs[3], machine);
1369}
1370
1371/* SPARCstation Voyager hardware initialisation */
1372static void vger_init(MachineState *machine)
1373{
1374    sun4m_hw_init(&sun4m_hwdefs[4], machine);
1375}
1376
1377/* SPARCstation LX hardware initialisation */
1378static void ss_lx_init(MachineState *machine)
1379{
1380    sun4m_hw_init(&sun4m_hwdefs[5], machine);
1381}
1382
1383/* SPARCstation 4 hardware initialisation */
1384static void ss4_init(MachineState *machine)
1385{
1386    sun4m_hw_init(&sun4m_hwdefs[6], machine);
1387}
1388
1389/* SPARCClassic hardware initialisation */
1390static void scls_init(MachineState *machine)
1391{
1392    sun4m_hw_init(&sun4m_hwdefs[7], machine);
1393}
1394
1395/* SPARCbook hardware initialisation */
1396static void sbook_init(MachineState *machine)
1397{
1398    sun4m_hw_init(&sun4m_hwdefs[8], machine);
1399}
1400
1401static void ss5_class_init(ObjectClass *oc, void *data)
1402{
1403    MachineClass *mc = MACHINE_CLASS(oc);
1404
1405    mc->desc = "Sun4m platform, SPARCstation 5";
1406    mc->init = ss5_init;
1407    mc->block_default_type = IF_SCSI;
1408    mc->is_default = 1;
1409    mc->default_boot_order = "c";
1410    mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
1411    mc->default_display = "tcx";
1412}
1413
1414static const TypeInfo ss5_type = {
1415    .name = MACHINE_TYPE_NAME("SS-5"),
1416    .parent = TYPE_MACHINE,
1417    .class_init = ss5_class_init,
1418};
1419
1420static void ss10_class_init(ObjectClass *oc, void *data)
1421{
1422    MachineClass *mc = MACHINE_CLASS(oc);
1423
1424    mc->desc = "Sun4m platform, SPARCstation 10";
1425    mc->init = ss10_init;
1426    mc->block_default_type = IF_SCSI;
1427    mc->max_cpus = 4;
1428    mc->default_boot_order = "c";
1429    mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
1430    mc->default_display = "tcx";
1431}
1432
1433static const TypeInfo ss10_type = {
1434    .name = MACHINE_TYPE_NAME("SS-10"),
1435    .parent = TYPE_MACHINE,
1436    .class_init = ss10_class_init,
1437};
1438
1439static void ss600mp_class_init(ObjectClass *oc, void *data)
1440{
1441    MachineClass *mc = MACHINE_CLASS(oc);
1442
1443    mc->desc = "Sun4m platform, SPARCserver 600MP";
1444    mc->init = ss600mp_init;
1445    mc->block_default_type = IF_SCSI;
1446    mc->max_cpus = 4;
1447    mc->default_boot_order = "c";
1448    mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
1449    mc->default_display = "tcx";
1450}
1451
1452static const TypeInfo ss600mp_type = {
1453    .name = MACHINE_TYPE_NAME("SS-600MP"),
1454    .parent = TYPE_MACHINE,
1455    .class_init = ss600mp_class_init,
1456};
1457
1458static void ss20_class_init(ObjectClass *oc, void *data)
1459{
1460    MachineClass *mc = MACHINE_CLASS(oc);
1461
1462    mc->desc = "Sun4m platform, SPARCstation 20";
1463    mc->init = ss20_init;
1464    mc->block_default_type = IF_SCSI;
1465    mc->max_cpus = 4;
1466    mc->default_boot_order = "c";
1467    mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
1468    mc->default_display = "tcx";
1469}
1470
1471static const TypeInfo ss20_type = {
1472    .name = MACHINE_TYPE_NAME("SS-20"),
1473    .parent = TYPE_MACHINE,
1474    .class_init = ss20_class_init,
1475};
1476
1477static void voyager_class_init(ObjectClass *oc, void *data)
1478{
1479    MachineClass *mc = MACHINE_CLASS(oc);
1480
1481    mc->desc = "Sun4m platform, SPARCstation Voyager";
1482    mc->init = vger_init;
1483    mc->block_default_type = IF_SCSI;
1484    mc->default_boot_order = "c";
1485    mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
1486    mc->default_display = "tcx";
1487}
1488
1489static const TypeInfo voyager_type = {
1490    .name = MACHINE_TYPE_NAME("Voyager"),
1491    .parent = TYPE_MACHINE,
1492    .class_init = voyager_class_init,
1493};
1494
1495static void ss_lx_class_init(ObjectClass *oc, void *data)
1496{
1497    MachineClass *mc = MACHINE_CLASS(oc);
1498
1499    mc->desc = "Sun4m platform, SPARCstation LX";
1500    mc->init = ss_lx_init;
1501    mc->block_default_type = IF_SCSI;
1502    mc->default_boot_order = "c";
1503    mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
1504    mc->default_display = "tcx";
1505}
1506
1507static const TypeInfo ss_lx_type = {
1508    .name = MACHINE_TYPE_NAME("LX"),
1509    .parent = TYPE_MACHINE,
1510    .class_init = ss_lx_class_init,
1511};
1512
1513static void ss4_class_init(ObjectClass *oc, void *data)
1514{
1515    MachineClass *mc = MACHINE_CLASS(oc);
1516
1517    mc->desc = "Sun4m platform, SPARCstation 4";
1518    mc->init = ss4_init;
1519    mc->block_default_type = IF_SCSI;
1520    mc->default_boot_order = "c";
1521    mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
1522    mc->default_display = "tcx";
1523}
1524
1525static const TypeInfo ss4_type = {
1526    .name = MACHINE_TYPE_NAME("SS-4"),
1527    .parent = TYPE_MACHINE,
1528    .class_init = ss4_class_init,
1529};
1530
1531static void scls_class_init(ObjectClass *oc, void *data)
1532{
1533    MachineClass *mc = MACHINE_CLASS(oc);
1534
1535    mc->desc = "Sun4m platform, SPARCClassic";
1536    mc->init = scls_init;
1537    mc->block_default_type = IF_SCSI;
1538    mc->default_boot_order = "c";
1539    mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
1540    mc->default_display = "tcx";
1541}
1542
1543static const TypeInfo scls_type = {
1544    .name = MACHINE_TYPE_NAME("SPARCClassic"),
1545    .parent = TYPE_MACHINE,
1546    .class_init = scls_class_init,
1547};
1548
1549static void sbook_class_init(ObjectClass *oc, void *data)
1550{
1551    MachineClass *mc = MACHINE_CLASS(oc);
1552
1553    mc->desc = "Sun4m platform, SPARCbook";
1554    mc->init = sbook_init;
1555    mc->block_default_type = IF_SCSI;
1556    mc->default_boot_order = "c";
1557    mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
1558    mc->default_display = "tcx";
1559}
1560
1561static const TypeInfo sbook_type = {
1562    .name = MACHINE_TYPE_NAME("SPARCbook"),
1563    .parent = TYPE_MACHINE,
1564    .class_init = sbook_class_init,
1565};
1566
1567static void sun4m_register_types(void)
1568{
1569    type_register_static(&idreg_info);
1570    type_register_static(&afx_info);
1571    type_register_static(&prom_info);
1572    type_register_static(&ram_info);
1573
1574    type_register_static(&ss5_type);
1575    type_register_static(&ss10_type);
1576    type_register_static(&ss600mp_type);
1577    type_register_static(&ss20_type);
1578    type_register_static(&voyager_type);
1579    type_register_static(&ss_lx_type);
1580    type_register_static(&ss4_type);
1581    type_register_static(&scls_type);
1582    type_register_static(&sbook_type);
1583}
1584
1585type_init(sun4m_register_types)
1586