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25#include "qemu/osdep.h"
26#include "qemu/units.h"
27#include "qemu/error-report.h"
28#include "qapi/error.h"
29#include "qemu-common.h"
30#include "qemu/datadir.h"
31#include "cpu.h"
32#include "hw/pci/pci.h"
33#include "hw/pci/pci_bridge.h"
34#include "hw/pci/pci_bus.h"
35#include "hw/pci/pci_host.h"
36#include "hw/qdev-properties.h"
37#include "hw/pci-host/sabre.h"
38#include "hw/char/serial.h"
39#include "hw/char/parallel.h"
40#include "hw/rtc/m48t59.h"
41#include "migration/vmstate.h"
42#include "hw/input/i8042.h"
43#include "hw/block/fdc.h"
44#include "net/net.h"
45#include "qemu/timer.h"
46#include "sysemu/runstate.h"
47#include "sysemu/sysemu.h"
48#include "hw/boards.h"
49#include "hw/nvram/sun_nvram.h"
50#include "hw/nvram/chrp_nvram.h"
51#include "hw/sparc/sparc64.h"
52#include "hw/nvram/fw_cfg.h"
53#include "hw/sysbus.h"
54#include "hw/ide/pci.h"
55#include "hw/loader.h"
56#include "hw/fw-path-provider.h"
57#include "elf.h"
58#include "trace.h"
59#include "qom/object.h"
60
61#define KERNEL_LOAD_ADDR 0x00404000
62#define CMDLINE_ADDR 0x003ff000
63#define PROM_SIZE_MAX (4 * MiB)
64#define PROM_VADDR 0x000ffd00000ULL
65#define PBM_SPECIAL_BASE 0x1fe00000000ULL
66#define PBM_MEM_BASE 0x1ff00000000ULL
67#define PBM_PCI_IO_BASE (PBM_SPECIAL_BASE + 0x02000000ULL)
68#define PROM_FILENAME "openbios-sparc64"
69#define NVRAM_SIZE 0x2000
70#define MAX_IDE_BUS 2
71#define BIOS_CFG_IOPORT 0x510
72#define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00)
73#define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01)
74#define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02)
75
76#define IVEC_MAX 0x40
77
78struct hwdef {
79 uint16_t machine_id;
80 uint64_t prom_addr;
81 uint64_t console_serial_base;
82};
83
84struct EbusState {
85
86 PCIDevice parent_obj;
87
88 ISABus *isa_bus;
89 qemu_irq isa_bus_irqs[ISA_NUM_IRQS];
90 uint64_t console_serial_base;
91 MemoryRegion bar0;
92 MemoryRegion bar1;
93};
94
95#define TYPE_EBUS "ebus"
96OBJECT_DECLARE_SIMPLE_TYPE(EbusState, EBUS)
97
98const char *fw_cfg_arch_key_name(uint16_t key)
99{
100 static const struct {
101 uint16_t key;
102 const char *name;
103 } fw_cfg_arch_wellknown_keys[] = {
104 {FW_CFG_SPARC64_WIDTH, "width"},
105 {FW_CFG_SPARC64_HEIGHT, "height"},
106 {FW_CFG_SPARC64_DEPTH, "depth"},
107 };
108
109 for (size_t i = 0; i < ARRAY_SIZE(fw_cfg_arch_wellknown_keys); i++) {
110 if (fw_cfg_arch_wellknown_keys[i].key == key) {
111 return fw_cfg_arch_wellknown_keys[i].name;
112 }
113 }
114 return NULL;
115}
116
117static void fw_cfg_boot_set(void *opaque, const char *boot_device,
118 Error **errp)
119{
120 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
121}
122
123static int sun4u_NVRAM_set_params(Nvram *nvram, uint16_t NVRAM_size,
124 const char *arch, ram_addr_t RAM_size,
125 const char *boot_devices,
126 uint32_t kernel_image, uint32_t kernel_size,
127 const char *cmdline,
128 uint32_t initrd_image, uint32_t initrd_size,
129 uint32_t NVRAM_image,
130 int width, int height, int depth,
131 const uint8_t *macaddr)
132{
133 unsigned int i;
134 int sysp_end;
135 uint8_t image[0x1ff0];
136 NvramClass *k = NVRAM_GET_CLASS(nvram);
137
138 memset(image, '\0', sizeof(image));
139
140
141 sysp_end = chrp_nvram_create_system_partition(image, 0, 0x1fd0);
142
143
144 chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end);
145
146 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80);
147
148 for (i = 0; i < sizeof(image); i++) {
149 (k->write)(nvram, i, image[i]);
150 }
151
152 return 0;
153}
154
155static uint64_t sun4u_load_kernel(const char *kernel_filename,
156 const char *initrd_filename,
157 ram_addr_t RAM_size, uint64_t *initrd_size,
158 uint64_t *initrd_addr, uint64_t *kernel_addr,
159 uint64_t *kernel_entry)
160{
161 int linux_boot;
162 unsigned int i;
163 long kernel_size;
164 uint8_t *ptr;
165 uint64_t kernel_top = 0;
166
167 linux_boot = (kernel_filename != NULL);
168
169 kernel_size = 0;
170 if (linux_boot) {
171 int bswap_needed;
172
173#ifdef BSWAP_NEEDED
174 bswap_needed = 1;
175#else
176 bswap_needed = 0;
177#endif
178 kernel_size = load_elf(kernel_filename, NULL, NULL, NULL, kernel_entry,
179 kernel_addr, &kernel_top, NULL, 1, EM_SPARCV9, 0,
180 0);
181 if (kernel_size < 0) {
182 *kernel_addr = KERNEL_LOAD_ADDR;
183 *kernel_entry = KERNEL_LOAD_ADDR;
184 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
185 RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
186 TARGET_PAGE_SIZE);
187 }
188 if (kernel_size < 0) {
189 kernel_size = load_image_targphys(kernel_filename,
190 KERNEL_LOAD_ADDR,
191 RAM_size - KERNEL_LOAD_ADDR);
192 }
193 if (kernel_size < 0) {
194 error_report("could not load kernel '%s'", kernel_filename);
195 exit(1);
196 }
197
198 *initrd_size = 0;
199 if (initrd_filename && kernel_top) {
200 *initrd_addr = TARGET_PAGE_ALIGN(kernel_top);
201
202 *initrd_size = load_image_targphys(initrd_filename,
203 *initrd_addr,
204 RAM_size - *initrd_addr);
205 if ((int)*initrd_size < 0) {
206 error_report("could not load initial ram disk '%s'",
207 initrd_filename);
208 exit(1);
209 }
210 }
211 if (*initrd_size > 0) {
212 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
213 ptr = rom_ptr(*kernel_addr + i, 32);
214 if (ptr && ldl_p(ptr + 8) == 0x48647253) {
215 stl_p(ptr + 24, *initrd_addr + *kernel_addr);
216 stl_p(ptr + 28, *initrd_size);
217 break;
218 }
219 }
220 }
221 }
222 return kernel_size;
223}
224
225typedef struct ResetData {
226 SPARCCPU *cpu;
227 uint64_t prom_addr;
228} ResetData;
229
230#define TYPE_SUN4U_POWER "power"
231OBJECT_DECLARE_SIMPLE_TYPE(PowerDevice, SUN4U_POWER)
232
233struct PowerDevice {
234 SysBusDevice parent_obj;
235
236 MemoryRegion power_mmio;
237};
238
239
240static uint64_t power_mem_read(void *opaque, hwaddr addr, unsigned size)
241{
242 return 0;
243}
244
245static void power_mem_write(void *opaque, hwaddr addr,
246 uint64_t val, unsigned size)
247{
248
249 if (val & 0x1000000) {
250 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
251 }
252}
253
254static const MemoryRegionOps power_mem_ops = {
255 .read = power_mem_read,
256 .write = power_mem_write,
257 .endianness = DEVICE_NATIVE_ENDIAN,
258 .valid = {
259 .min_access_size = 4,
260 .max_access_size = 4,
261 },
262};
263
264static void power_realize(DeviceState *dev, Error **errp)
265{
266 PowerDevice *d = SUN4U_POWER(dev);
267 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
268
269 memory_region_init_io(&d->power_mmio, OBJECT(dev), &power_mem_ops, d,
270 "power", sizeof(uint32_t));
271
272 sysbus_init_mmio(sbd, &d->power_mmio);
273}
274
275static void power_class_init(ObjectClass *klass, void *data)
276{
277 DeviceClass *dc = DEVICE_CLASS(klass);
278
279 dc->realize = power_realize;
280}
281
282static const TypeInfo power_info = {
283 .name = TYPE_SUN4U_POWER,
284 .parent = TYPE_SYS_BUS_DEVICE,
285 .instance_size = sizeof(PowerDevice),
286 .class_init = power_class_init,
287};
288
289static void ebus_isa_irq_handler(void *opaque, int n, int level)
290{
291 EbusState *s = EBUS(opaque);
292 qemu_irq irq = s->isa_bus_irqs[n];
293
294
295 trace_ebus_isa_irq_handler(n, level);
296 if (irq) {
297 qemu_set_irq(irq, level);
298 }
299}
300
301
302static void ebus_realize(PCIDevice *pci_dev, Error **errp)
303{
304 EbusState *s = EBUS(pci_dev);
305 ISADevice *isa_dev;
306 SysBusDevice *sbd;
307 DeviceState *dev;
308 qemu_irq *isa_irq;
309 DriveInfo *fd[MAX_FD];
310 int i;
311
312 s->isa_bus = isa_bus_new(DEVICE(pci_dev), get_system_memory(),
313 pci_address_space_io(pci_dev), errp);
314 if (!s->isa_bus) {
315 error_setg(errp, "unable to instantiate EBUS ISA bus");
316 return;
317 }
318
319
320 isa_irq = qemu_allocate_irqs(ebus_isa_irq_handler, s, ISA_NUM_IRQS);
321 isa_bus_irqs(s->isa_bus, isa_irq);
322 qdev_init_gpio_out_named(DEVICE(s), s->isa_bus_irqs, "isa-irq",
323 ISA_NUM_IRQS);
324
325
326 i = 0;
327 if (s->console_serial_base) {
328 serial_mm_init(pci_address_space(pci_dev), s->console_serial_base,
329 0, NULL, 115200, serial_hd(i), DEVICE_BIG_ENDIAN);
330 i++;
331 }
332 serial_hds_isa_init(s->isa_bus, i, MAX_ISA_SERIAL_PORTS);
333
334
335 parallel_hds_isa_init(s->isa_bus, MAX_PARALLEL_PORTS);
336
337
338 isa_create_simple(s->isa_bus, "i8042");
339
340
341 for (i = 0; i < MAX_FD; i++) {
342 fd[i] = drive_get(IF_FLOPPY, 0, i);
343 }
344 isa_dev = isa_new(TYPE_ISA_FDC);
345 dev = DEVICE(isa_dev);
346 qdev_prop_set_uint32(dev, "dma", -1);
347 isa_realize_and_unref(isa_dev, s->isa_bus, &error_fatal);
348 isa_fdc_init_drives(isa_dev, fd);
349
350
351 dev = qdev_new(TYPE_SUN4U_POWER);
352 sbd = SYS_BUS_DEVICE(dev);
353 sysbus_realize_and_unref(sbd, &error_fatal);
354 memory_region_add_subregion(pci_address_space_io(pci_dev), 0x7240,
355 sysbus_mmio_get_region(sbd, 0));
356
357
358 pci_dev->config[0x04] = 0x06;
359 pci_dev->config[0x05] = 0x00;
360 pci_dev->config[0x06] = 0xa0;
361 pci_dev->config[0x07] = 0x03;
362 pci_dev->config[0x09] = 0x00;
363 pci_dev->config[0x0D] = 0x0a;
364
365 memory_region_init_alias(&s->bar0, OBJECT(s), "bar0", get_system_io(),
366 0, 0x1000000);
367 pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0);
368 memory_region_init_alias(&s->bar1, OBJECT(s), "bar1", get_system_io(),
369 0, 0x8000);
370 pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->bar1);
371}
372
373static Property ebus_properties[] = {
374 DEFINE_PROP_UINT64("console-serial-base", EbusState,
375 console_serial_base, 0),
376 DEFINE_PROP_END_OF_LIST(),
377};
378
379static void ebus_class_init(ObjectClass *klass, void *data)
380{
381 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
382 DeviceClass *dc = DEVICE_CLASS(klass);
383
384 k->realize = ebus_realize;
385 k->vendor_id = PCI_VENDOR_ID_SUN;
386 k->device_id = PCI_DEVICE_ID_SUN_EBUS;
387 k->revision = 0x01;
388 k->class_id = PCI_CLASS_BRIDGE_OTHER;
389 device_class_set_props(dc, ebus_properties);
390}
391
392static const TypeInfo ebus_info = {
393 .name = TYPE_EBUS,
394 .parent = TYPE_PCI_DEVICE,
395 .class_init = ebus_class_init,
396 .instance_size = sizeof(EbusState),
397 .interfaces = (InterfaceInfo[]) {
398 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
399 { },
400 },
401};
402
403#define TYPE_OPENPROM "openprom"
404typedef struct PROMState PROMState;
405DECLARE_INSTANCE_CHECKER(PROMState, OPENPROM,
406 TYPE_OPENPROM)
407
408struct PROMState {
409 SysBusDevice parent_obj;
410
411 MemoryRegion prom;
412};
413
414static uint64_t translate_prom_address(void *opaque, uint64_t addr)
415{
416 hwaddr *base_addr = (hwaddr *)opaque;
417 return addr + *base_addr - PROM_VADDR;
418}
419
420
421static void prom_init(hwaddr addr, const char *bios_name)
422{
423 DeviceState *dev;
424 SysBusDevice *s;
425 char *filename;
426 int ret;
427
428 dev = qdev_new(TYPE_OPENPROM);
429 s = SYS_BUS_DEVICE(dev);
430 sysbus_realize_and_unref(s, &error_fatal);
431
432 sysbus_mmio_map(s, 0, addr);
433
434
435 if (bios_name == NULL) {
436 bios_name = PROM_FILENAME;
437 }
438 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
439 if (filename) {
440 ret = load_elf(filename, NULL, translate_prom_address, &addr,
441 NULL, NULL, NULL, NULL, 1, EM_SPARCV9, 0, 0);
442 if (ret < 0 || ret > PROM_SIZE_MAX) {
443 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
444 }
445 g_free(filename);
446 } else {
447 ret = -1;
448 }
449 if (ret < 0 || ret > PROM_SIZE_MAX) {
450 error_report("could not load prom '%s'", bios_name);
451 exit(1);
452 }
453}
454
455static void prom_realize(DeviceState *ds, Error **errp)
456{
457 PROMState *s = OPENPROM(ds);
458 SysBusDevice *dev = SYS_BUS_DEVICE(ds);
459 Error *local_err = NULL;
460
461 memory_region_init_ram_nomigrate(&s->prom, OBJECT(ds), "sun4u.prom",
462 PROM_SIZE_MAX, &local_err);
463 if (local_err) {
464 error_propagate(errp, local_err);
465 return;
466 }
467
468 vmstate_register_ram_global(&s->prom);
469 memory_region_set_readonly(&s->prom, true);
470 sysbus_init_mmio(dev, &s->prom);
471}
472
473static Property prom_properties[] = {
474 {},
475};
476
477static void prom_class_init(ObjectClass *klass, void *data)
478{
479 DeviceClass *dc = DEVICE_CLASS(klass);
480
481 device_class_set_props(dc, prom_properties);
482 dc->realize = prom_realize;
483}
484
485static const TypeInfo prom_info = {
486 .name = TYPE_OPENPROM,
487 .parent = TYPE_SYS_BUS_DEVICE,
488 .instance_size = sizeof(PROMState),
489 .class_init = prom_class_init,
490};
491
492
493#define TYPE_SUN4U_MEMORY "memory"
494typedef struct RamDevice RamDevice;
495DECLARE_INSTANCE_CHECKER(RamDevice, SUN4U_RAM,
496 TYPE_SUN4U_MEMORY)
497
498struct RamDevice {
499 SysBusDevice parent_obj;
500
501 MemoryRegion ram;
502 uint64_t size;
503};
504
505
506static void ram_realize(DeviceState *dev, Error **errp)
507{
508 RamDevice *d = SUN4U_RAM(dev);
509 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
510
511 memory_region_init_ram_nomigrate(&d->ram, OBJECT(d), "sun4u.ram", d->size,
512 &error_fatal);
513 vmstate_register_ram_global(&d->ram);
514 sysbus_init_mmio(sbd, &d->ram);
515}
516
517static void ram_init(hwaddr addr, ram_addr_t RAM_size)
518{
519 DeviceState *dev;
520 SysBusDevice *s;
521 RamDevice *d;
522
523
524 dev = qdev_new(TYPE_SUN4U_MEMORY);
525 s = SYS_BUS_DEVICE(dev);
526
527 d = SUN4U_RAM(dev);
528 d->size = RAM_size;
529 sysbus_realize_and_unref(s, &error_fatal);
530
531 sysbus_mmio_map(s, 0, addr);
532}
533
534static Property ram_properties[] = {
535 DEFINE_PROP_UINT64("size", RamDevice, size, 0),
536 DEFINE_PROP_END_OF_LIST(),
537};
538
539static void ram_class_init(ObjectClass *klass, void *data)
540{
541 DeviceClass *dc = DEVICE_CLASS(klass);
542
543 dc->realize = ram_realize;
544 device_class_set_props(dc, ram_properties);
545}
546
547static const TypeInfo ram_info = {
548 .name = TYPE_SUN4U_MEMORY,
549 .parent = TYPE_SYS_BUS_DEVICE,
550 .instance_size = sizeof(RamDevice),
551 .class_init = ram_class_init,
552};
553
554static void sun4uv_init(MemoryRegion *address_space_mem,
555 MachineState *machine,
556 const struct hwdef *hwdef)
557{
558 SPARCCPU *cpu;
559 Nvram *nvram;
560 unsigned int i;
561 uint64_t initrd_addr, initrd_size, kernel_addr, kernel_size, kernel_entry;
562 SabreState *sabre;
563 PCIBus *pci_bus, *pci_busA, *pci_busB;
564 PCIDevice *ebus, *pci_dev;
565 SysBusDevice *s;
566 DeviceState *iommu, *dev;
567 FWCfgState *fw_cfg;
568 NICInfo *nd;
569 MACAddr macaddr;
570 bool onboard_nic;
571
572
573 cpu = sparc64_cpu_devinit(machine->cpu_type, hwdef->prom_addr);
574
575
576 iommu = qdev_new(TYPE_SUN4U_IOMMU);
577 sysbus_realize_and_unref(SYS_BUS_DEVICE(iommu), &error_fatal);
578
579
580 ram_init(0, machine->ram_size);
581
582 prom_init(hwdef->prom_addr, machine->firmware);
583
584
585 sabre = SABRE(qdev_new(TYPE_SABRE));
586 qdev_prop_set_uint64(DEVICE(sabre), "special-base", PBM_SPECIAL_BASE);
587 qdev_prop_set_uint64(DEVICE(sabre), "mem-base", PBM_MEM_BASE);
588 object_property_set_link(OBJECT(sabre), "iommu", OBJECT(iommu),
589 &error_abort);
590 sysbus_realize_and_unref(SYS_BUS_DEVICE(sabre), &error_fatal);
591
592
593 sysbus_mmio_map(SYS_BUS_DEVICE(sabre), 0, PBM_SPECIAL_BASE);
594
595 sysbus_mmio_map(SYS_BUS_DEVICE(sabre), 1, PBM_SPECIAL_BASE + 0x1000000ULL);
596
597 sysbus_mmio_map(SYS_BUS_DEVICE(sabre), 2, PBM_SPECIAL_BASE + 0x2000000ULL);
598
599
600 for (i = 0; i < IVEC_MAX; i++) {
601 qdev_connect_gpio_out_named(DEVICE(sabre), "ivec-irq", i,
602 qdev_get_gpio_in_named(DEVICE(cpu), "ivec-irq", i));
603 }
604
605 pci_bus = PCI_HOST_BRIDGE(sabre)->bus;
606 pci_busA = pci_bridge_get_sec_bus(sabre->bridgeA);
607 pci_busB = pci_bridge_get_sec_bus(sabre->bridgeB);
608
609
610
611
612 pci_bus->slot_reserved_mask = 0xfffffffc;
613 pci_busA->slot_reserved_mask = 0xfffffff1;
614 pci_busB->slot_reserved_mask = 0xfffffff0;
615
616 ebus = pci_new_multifunction(PCI_DEVFN(1, 0), true, TYPE_EBUS);
617 qdev_prop_set_uint64(DEVICE(ebus), "console-serial-base",
618 hwdef->console_serial_base);
619 pci_realize_and_unref(ebus, pci_busA, &error_fatal);
620
621
622 qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 7,
623 qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_LPT_IRQ));
624 qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 6,
625 qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_FDD_IRQ));
626 qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 1,
627 qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_KBD_IRQ));
628 qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 12,
629 qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_MSE_IRQ));
630 qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 4,
631 qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_SER_IRQ));
632
633 switch (vga_interface_type) {
634 case VGA_STD:
635 pci_create_simple(pci_busA, PCI_DEVFN(2, 0), "VGA");
636 break;
637 case VGA_NONE:
638 break;
639 default:
640 abort();
641 }
642
643 memset(&macaddr, 0, sizeof(MACAddr));
644 onboard_nic = false;
645 for (i = 0; i < nb_nics; i++) {
646 PCIBus *bus;
647 nd = &nd_table[i];
648
649 if (!nd->model || strcmp(nd->model, "sunhme") == 0) {
650 if (!onboard_nic) {
651 pci_dev = pci_new_multifunction(PCI_DEVFN(1, 1),
652 true, "sunhme");
653 bus = pci_busA;
654 memcpy(&macaddr, &nd->macaddr.a, sizeof(MACAddr));
655 onboard_nic = true;
656 } else {
657 pci_dev = pci_new(-1, "sunhme");
658 bus = pci_busB;
659 }
660 } else {
661 pci_dev = pci_new(-1, nd->model);
662 bus = pci_busB;
663 }
664
665 dev = &pci_dev->qdev;
666 qdev_set_nic_properties(dev, nd);
667 pci_realize_and_unref(pci_dev, bus, &error_fatal);
668 }
669
670
671
672 if (!onboard_nic) {
673 qemu_macaddr_default_if_unset(&macaddr);
674 }
675
676 pci_dev = pci_new(PCI_DEVFN(3, 0), "cmd646-ide");
677 qdev_prop_set_uint32(&pci_dev->qdev, "secondary", 1);
678 pci_realize_and_unref(pci_dev, pci_busA, &error_fatal);
679 pci_ide_create_devs(pci_dev);
680
681
682 dev = qdev_new("sysbus-m48t59");
683 qdev_prop_set_int32(dev, "base-year", 1968);
684 s = SYS_BUS_DEVICE(dev);
685 sysbus_realize_and_unref(s, &error_fatal);
686 memory_region_add_subregion(pci_address_space_io(ebus), 0x2000,
687 sysbus_mmio_get_region(s, 0));
688 nvram = NVRAM(dev);
689
690 initrd_size = 0;
691 initrd_addr = 0;
692 kernel_size = sun4u_load_kernel(machine->kernel_filename,
693 machine->initrd_filename,
694 machine->ram_size, &initrd_size, &initrd_addr,
695 &kernel_addr, &kernel_entry);
696
697 sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", machine->ram_size,
698 machine->boot_order,
699 kernel_addr, kernel_size,
700 machine->kernel_cmdline,
701 initrd_addr, initrd_size,
702
703 0,
704 graphic_width, graphic_height, graphic_depth,
705 (uint8_t *)&macaddr);
706
707 dev = qdev_new(TYPE_FW_CFG_IO);
708 qdev_prop_set_bit(dev, "dma_enabled", false);
709 object_property_add_child(OBJECT(ebus), TYPE_FW_CFG, OBJECT(dev));
710 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
711 memory_region_add_subregion(pci_address_space_io(ebus), BIOS_CFG_IOPORT,
712 &FW_CFG_IO(dev)->comb_iomem);
713
714 fw_cfg = FW_CFG(dev);
715 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)machine->smp.cpus);
716 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)machine->smp.max_cpus);
717 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size);
718 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
719 fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_entry);
720 fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
721 if (machine->kernel_cmdline) {
722 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
723 strlen(machine->kernel_cmdline) + 1);
724 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline);
725 } else {
726 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
727 }
728 fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
729 fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
730 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]);
731
732 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width);
733 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height);
734 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth);
735
736 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
737}
738
739enum {
740 sun4u_id = 0,
741 sun4v_id = 64,
742};
743
744
745
746
747
748static char *sun4u_fw_dev_path(FWPathProvider *p, BusState *bus,
749 DeviceState *dev)
750{
751 PCIDevice *pci;
752
753 if (!strcmp(object_get_typename(OBJECT(dev)), "pbm-bridge")) {
754 pci = PCI_DEVICE(dev);
755
756 if (PCI_FUNC(pci->devfn)) {
757 return g_strdup_printf("pci@%x,%x", PCI_SLOT(pci->devfn),
758 PCI_FUNC(pci->devfn));
759 } else {
760 return g_strdup_printf("pci@%x", PCI_SLOT(pci->devfn));
761 }
762 }
763
764 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-hd")) {
765 return g_strdup("disk");
766 }
767
768 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-cd")) {
769 return g_strdup("cdrom");
770 }
771
772 if (!strcmp(object_get_typename(OBJECT(dev)), "virtio-blk-device")) {
773 return g_strdup("disk");
774 }
775
776 return NULL;
777}
778
779static const struct hwdef hwdefs[] = {
780
781 {
782 .machine_id = sun4u_id,
783 .prom_addr = 0x1fff0000000ULL,
784 .console_serial_base = 0,
785 },
786
787 {
788 .machine_id = sun4v_id,
789 .prom_addr = 0x1fff0000000ULL,
790 .console_serial_base = 0,
791 },
792};
793
794
795static void sun4u_init(MachineState *machine)
796{
797 sun4uv_init(get_system_memory(), machine, &hwdefs[0]);
798}
799
800
801static void sun4v_init(MachineState *machine)
802{
803 sun4uv_init(get_system_memory(), machine, &hwdefs[1]);
804}
805
806static void sun4u_class_init(ObjectClass *oc, void *data)
807{
808 MachineClass *mc = MACHINE_CLASS(oc);
809 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc);
810
811 mc->desc = "Sun4u platform";
812 mc->init = sun4u_init;
813 mc->block_default_type = IF_IDE;
814 mc->max_cpus = 1;
815 mc->is_default = true;
816 mc->default_boot_order = "c";
817 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-UltraSparc-IIi");
818 mc->ignore_boot_device_suffixes = true;
819 mc->default_display = "std";
820 fwc->get_dev_path = sun4u_fw_dev_path;
821}
822
823static const TypeInfo sun4u_type = {
824 .name = MACHINE_TYPE_NAME("sun4u"),
825 .parent = TYPE_MACHINE,
826 .class_init = sun4u_class_init,
827 .interfaces = (InterfaceInfo[]) {
828 { TYPE_FW_PATH_PROVIDER },
829 { }
830 },
831};
832
833static void sun4v_class_init(ObjectClass *oc, void *data)
834{
835 MachineClass *mc = MACHINE_CLASS(oc);
836
837 mc->desc = "Sun4v platform";
838 mc->init = sun4v_init;
839 mc->block_default_type = IF_IDE;
840 mc->max_cpus = 1;
841 mc->default_boot_order = "c";
842 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Sun-UltraSparc-T1");
843 mc->default_display = "std";
844}
845
846static const TypeInfo sun4v_type = {
847 .name = MACHINE_TYPE_NAME("sun4v"),
848 .parent = TYPE_MACHINE,
849 .class_init = sun4v_class_init,
850};
851
852static void sun4u_register_types(void)
853{
854 type_register_static(&power_info);
855 type_register_static(&ebus_info);
856 type_register_static(&prom_info);
857 type_register_static(&ram_info);
858
859 type_register_static(&sun4u_type);
860 type_register_static(&sun4v_type);
861}
862
863type_init(sun4u_register_types)
864
