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25#include "qemu/osdep.h"
26#include "hw/sysbus.h"
27#include "migration/vmstate.h"
28#include "qemu/log.h"
29#include "qemu/module.h"
30#include "qemu/error-report.h"
31#include "qapi/error.h"
32#include "qemu/units.h"
33#include "trace.h"
34
35#include "hw/irq.h"
36#include "hw/qdev-properties.h"
37#include "hw/ssi/aspeed_smc.h"
38
39
40#define R_CONF (0x00 / 4)
41#define CONF_LEGACY_DISABLE (1 << 31)
42#define CONF_ENABLE_W4 20
43#define CONF_ENABLE_W3 19
44#define CONF_ENABLE_W2 18
45#define CONF_ENABLE_W1 17
46#define CONF_ENABLE_W0 16
47#define CONF_FLASH_TYPE4 8
48#define CONF_FLASH_TYPE3 6
49#define CONF_FLASH_TYPE2 4
50#define CONF_FLASH_TYPE1 2
51#define CONF_FLASH_TYPE0 0
52#define CONF_FLASH_TYPE_NOR 0x0
53#define CONF_FLASH_TYPE_NAND 0x1
54#define CONF_FLASH_TYPE_SPI 0x2
55
56
57#define R_CE_CTRL (0x04 / 4)
58#define CTRL_EXTENDED4 4
59#define CTRL_EXTENDED3 3
60#define CTRL_EXTENDED2 2
61#define CTRL_EXTENDED1 1
62#define CTRL_EXTENDED0 0
63
64
65#define R_INTR_CTRL (0x08 / 4)
66#define INTR_CTRL_DMA_STATUS (1 << 11)
67#define INTR_CTRL_CMD_ABORT_STATUS (1 << 10)
68#define INTR_CTRL_WRITE_PROTECT_STATUS (1 << 9)
69#define INTR_CTRL_DMA_EN (1 << 3)
70#define INTR_CTRL_CMD_ABORT_EN (1 << 2)
71#define INTR_CTRL_WRITE_PROTECT_EN (1 << 1)
72
73
74#define R_CE_CMD_CTRL (0x0C / 4)
75#define CTRL_ADDR_BYTE0_DISABLE_SHIFT 4
76#define CTRL_DATA_BYTE0_DISABLE_SHIFT 0
77
78#define aspeed_smc_addr_byte_enabled(s, i) \
79 (!((s)->regs[R_CE_CMD_CTRL] & (1 << (CTRL_ADDR_BYTE0_DISABLE_SHIFT + (i)))))
80#define aspeed_smc_data_byte_enabled(s, i) \
81 (!((s)->regs[R_CE_CMD_CTRL] & (1 << (CTRL_DATA_BYTE0_DISABLE_SHIFT + (i)))))
82
83
84#define R_CTRL0 (0x10 / 4)
85#define CTRL_IO_QPI (1 << 31)
86#define CTRL_IO_QUAD_DATA (1 << 30)
87#define CTRL_IO_DUAL_DATA (1 << 29)
88#define CTRL_IO_DUAL_ADDR_DATA (1 << 28)
89#define CTRL_IO_QUAD_ADDR_DATA (1 << 28)
90#define CTRL_CMD_SHIFT 16
91#define CTRL_CMD_MASK 0xff
92#define CTRL_DUMMY_HIGH_SHIFT 14
93#define CTRL_AST2400_SPI_4BYTE (1 << 13)
94#define CE_CTRL_CLOCK_FREQ_SHIFT 8
95#define CE_CTRL_CLOCK_FREQ_MASK 0xf
96#define CE_CTRL_CLOCK_FREQ(div) \
97 (((div) & CE_CTRL_CLOCK_FREQ_MASK) << CE_CTRL_CLOCK_FREQ_SHIFT)
98#define CTRL_DUMMY_LOW_SHIFT 6
99#define CTRL_CE_STOP_ACTIVE (1 << 2)
100#define CTRL_CMD_MODE_MASK 0x3
101#define CTRL_READMODE 0x0
102#define CTRL_FREADMODE 0x1
103#define CTRL_WRITEMODE 0x2
104#define CTRL_USERMODE 0x3
105#define R_CTRL1 (0x14 / 4)
106#define R_CTRL2 (0x18 / 4)
107#define R_CTRL3 (0x1C / 4)
108#define R_CTRL4 (0x20 / 4)
109
110
111#define R_SEG_ADDR0 (0x30 / 4)
112#define SEG_END_SHIFT 24
113#define SEG_END_MASK 0xff
114#define SEG_START_SHIFT 16
115#define SEG_START_MASK 0xff
116#define R_SEG_ADDR1 (0x34 / 4)
117#define R_SEG_ADDR2 (0x38 / 4)
118#define R_SEG_ADDR3 (0x3C / 4)
119#define R_SEG_ADDR4 (0x40 / 4)
120
121
122#define R_MISC_CTRL1 (0x50 / 4)
123
124
125#define R_DUMMY_DATA (0x54 / 4)
126
127
128#define R_FMC_WDT2_CTRL (0x64 / 4)
129#define FMC_WDT2_CTRL_ALT_BOOT_MODE BIT(6)
130#define FMC_WDT2_CTRL_SINGLE_BOOT_MODE BIT(5)
131#define FMC_WDT2_CTRL_BOOT_SOURCE BIT(4)
132#define FMC_WDT2_CTRL_EN BIT(0)
133
134
135#define R_DMA_CTRL (0x80 / 4)
136#define DMA_CTRL_REQUEST (1 << 31)
137#define DMA_CTRL_GRANT (1 << 30)
138#define DMA_CTRL_DELAY_MASK 0xf
139#define DMA_CTRL_DELAY_SHIFT 8
140#define DMA_CTRL_FREQ_MASK 0xf
141#define DMA_CTRL_FREQ_SHIFT 4
142#define DMA_CTRL_CALIB (1 << 3)
143#define DMA_CTRL_CKSUM (1 << 2)
144#define DMA_CTRL_WRITE (1 << 1)
145#define DMA_CTRL_ENABLE (1 << 0)
146
147
148#define R_DMA_FLASH_ADDR (0x84 / 4)
149
150
151#define R_DMA_DRAM_ADDR (0x88 / 4)
152
153
154#define R_DMA_LEN (0x8C / 4)
155
156
157#define R_DMA_CHECKSUM (0x90 / 4)
158
159
160#define R_TIMINGS (0x94 / 4)
161
162
163#define R_SPI_CONF (0x00 / 4)
164#define SPI_CONF_ENABLE_W0 0
165#define R_SPI_CTRL0 (0x4 / 4)
166#define R_SPI_MISC_CTRL (0x10 / 4)
167#define R_SPI_TIMINGS (0x14 / 4)
168
169#define ASPEED_SMC_R_SPI_MAX (0x20 / 4)
170#define ASPEED_SMC_R_SMC_MAX (0x20 / 4)
171
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183
184#define DMA_DRAM_ADDR(asc, val) ((val) & (asc)->dma_dram_mask)
185#define DMA_FLASH_ADDR(asc, val) ((val) & (asc)->dma_flash_mask)
186#define DMA_LENGTH(val) ((val) & 0x01FFFFFC)
187
188
189#define SPI_OP_READ 0x03
190
191#define SNOOP_OFF 0xFF
192#define SNOOP_START 0x0
193
194
195
196
197
198
199static const AspeedSegments aspeed_2500_spi1_segments[];
200static const AspeedSegments aspeed_2500_spi2_segments[];
201
202#define ASPEED_SMC_FEATURE_DMA 0x1
203#define ASPEED_SMC_FEATURE_DMA_GRANT 0x2
204#define ASPEED_SMC_FEATURE_WDT_CONTROL 0x4
205
206static inline bool aspeed_smc_has_dma(const AspeedSMCClass *asc)
207{
208 return !!(asc->features & ASPEED_SMC_FEATURE_DMA);
209}
210
211static inline bool aspeed_smc_has_wdt_control(const AspeedSMCClass *asc)
212{
213 return !!(asc->features & ASPEED_SMC_FEATURE_WDT_CONTROL);
214}
215
216#define aspeed_smc_error(fmt, ...) \
217 qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt "\n", __func__, ## __VA_ARGS__)
218
219static bool aspeed_smc_flash_overlap(const AspeedSMCState *s,
220 const AspeedSegments *new,
221 int cs)
222{
223 AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s);
224 AspeedSegments seg;
225 int i;
226
227 for (i = 0; i < asc->max_peripherals; i++) {
228 if (i == cs) {
229 continue;
230 }
231
232 asc->reg_to_segment(s, s->regs[R_SEG_ADDR0 + i], &seg);
233
234 if (new->addr + new->size > seg.addr &&
235 new->addr < seg.addr + seg.size) {
236 aspeed_smc_error("new segment CS%d [ 0x%"
237 HWADDR_PRIx" - 0x%"HWADDR_PRIx" ] overlaps with "
238 "CS%d [ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]",
239 cs, new->addr, new->addr + new->size,
240 i, seg.addr, seg.addr + seg.size);
241 return true;
242 }
243 }
244 return false;
245}
246
247static void aspeed_smc_flash_set_segment_region(AspeedSMCState *s, int cs,
248 uint64_t regval)
249{
250 AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s);
251 AspeedSMCFlash *fl = &s->flashes[cs];
252 AspeedSegments seg;
253
254 asc->reg_to_segment(s, regval, &seg);
255
256 memory_region_transaction_begin();
257 memory_region_set_size(&fl->mmio, seg.size);
258 memory_region_set_address(&fl->mmio, seg.addr - asc->flash_window_base);
259 memory_region_set_enabled(&fl->mmio, !!seg.size);
260 memory_region_transaction_commit();
261
262 s->regs[R_SEG_ADDR0 + cs] = regval;
263}
264
265static void aspeed_smc_flash_set_segment(AspeedSMCState *s, int cs,
266 uint64_t new)
267{
268 AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s);
269 AspeedSegments seg;
270
271 asc->reg_to_segment(s, new, &seg);
272
273 trace_aspeed_smc_flash_set_segment(cs, new, seg.addr, seg.addr + seg.size);
274
275
276 if (cs == 0 && seg.addr != asc->flash_window_base) {
277 aspeed_smc_error("Tried to change CS0 start address to 0x%"
278 HWADDR_PRIx, seg.addr);
279 seg.addr = asc->flash_window_base;
280 new = asc->segment_to_reg(s, &seg);
281 }
282
283
284
285
286
287 if ((asc->segments == aspeed_2500_spi1_segments ||
288 asc->segments == aspeed_2500_spi2_segments) &&
289 cs == asc->max_peripherals &&
290 seg.addr + seg.size != asc->segments[cs].addr +
291 asc->segments[cs].size) {
292 aspeed_smc_error("Tried to change CS%d end address to 0x%"
293 HWADDR_PRIx, cs, seg.addr + seg.size);
294 seg.size = asc->segments[cs].addr + asc->segments[cs].size -
295 seg.addr;
296 new = asc->segment_to_reg(s, &seg);
297 }
298
299
300 if (seg.size &&
301 (seg.addr + seg.size <= asc->flash_window_base ||
302 seg.addr > asc->flash_window_base + asc->flash_window_size)) {
303 aspeed_smc_error("new segment for CS%d is invalid : "
304 "[ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]",
305 cs, seg.addr, seg.addr + seg.size);
306 return;
307 }
308
309
310 if (seg.size && !QEMU_IS_ALIGNED(seg.addr, seg.size)) {
311 aspeed_smc_error("new segment for CS%d is not "
312 "aligned : [ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]",
313 cs, seg.addr, seg.addr + seg.size);
314 }
315
316
317 aspeed_smc_flash_overlap(s, &seg, cs);
318
319
320 aspeed_smc_flash_set_segment_region(s, cs, new);
321}
322
323static uint64_t aspeed_smc_flash_default_read(void *opaque, hwaddr addr,
324 unsigned size)
325{
326 aspeed_smc_error("To 0x%" HWADDR_PRIx " of size %u" PRIx64, addr, size);
327 return 0;
328}
329
330static void aspeed_smc_flash_default_write(void *opaque, hwaddr addr,
331 uint64_t data, unsigned size)
332{
333 aspeed_smc_error("To 0x%" HWADDR_PRIx " of size %u: 0x%" PRIx64,
334 addr, size, data);
335}
336
337static const MemoryRegionOps aspeed_smc_flash_default_ops = {
338 .read = aspeed_smc_flash_default_read,
339 .write = aspeed_smc_flash_default_write,
340 .endianness = DEVICE_LITTLE_ENDIAN,
341 .valid = {
342 .min_access_size = 1,
343 .max_access_size = 4,
344 },
345};
346
347static inline int aspeed_smc_flash_mode(const AspeedSMCFlash *fl)
348{
349 const AspeedSMCState *s = fl->controller;
350
351 return s->regs[s->r_ctrl0 + fl->cs] & CTRL_CMD_MODE_MASK;
352}
353
354static inline bool aspeed_smc_is_writable(const AspeedSMCFlash *fl)
355{
356 const AspeedSMCState *s = fl->controller;
357
358 return s->regs[s->r_conf] & (1 << (s->conf_enable_w0 + fl->cs));
359}
360
361static inline int aspeed_smc_flash_cmd(const AspeedSMCFlash *fl)
362{
363 const AspeedSMCState *s = fl->controller;
364 int cmd = (s->regs[s->r_ctrl0 + fl->cs] >> CTRL_CMD_SHIFT) & CTRL_CMD_MASK;
365
366
367
368
369
370
371
372 if (aspeed_smc_flash_mode(fl) == CTRL_READMODE) {
373 cmd = SPI_OP_READ;
374 }
375
376 if (!cmd) {
377 aspeed_smc_error("no command defined for mode %d",
378 aspeed_smc_flash_mode(fl));
379 }
380
381 return cmd;
382}
383
384static inline int aspeed_smc_flash_addr_width(const AspeedSMCFlash *fl)
385{
386 const AspeedSMCState *s = fl->controller;
387 AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s);
388
389 if (asc->addr_width) {
390 return asc->addr_width(s);
391 } else {
392 return s->regs[s->r_ce_ctrl] & (1 << (CTRL_EXTENDED0 + fl->cs)) ? 4 : 3;
393 }
394}
395
396static void aspeed_smc_flash_do_select(AspeedSMCFlash *fl, bool unselect)
397{
398 AspeedSMCState *s = fl->controller;
399
400 trace_aspeed_smc_flash_select(fl->cs, unselect ? "un" : "");
401
402 qemu_set_irq(s->cs_lines[fl->cs], unselect);
403}
404
405static void aspeed_smc_flash_select(AspeedSMCFlash *fl)
406{
407 aspeed_smc_flash_do_select(fl, false);
408}
409
410static void aspeed_smc_flash_unselect(AspeedSMCFlash *fl)
411{
412 aspeed_smc_flash_do_select(fl, true);
413}
414
415static uint32_t aspeed_smc_check_segment_addr(const AspeedSMCFlash *fl,
416 uint32_t addr)
417{
418 const AspeedSMCState *s = fl->controller;
419 AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s);
420 AspeedSegments seg;
421
422 asc->reg_to_segment(s, s->regs[R_SEG_ADDR0 + fl->cs], &seg);
423 if ((addr % seg.size) != addr) {
424 aspeed_smc_error("invalid address 0x%08x for CS%d segment : "
425 "[ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]",
426 addr, fl->cs, seg.addr, seg.addr + seg.size);
427 addr %= seg.size;
428 }
429
430 return addr;
431}
432
433static int aspeed_smc_flash_dummies(const AspeedSMCFlash *fl)
434{
435 const AspeedSMCState *s = fl->controller;
436 uint32_t r_ctrl0 = s->regs[s->r_ctrl0 + fl->cs];
437 uint32_t dummy_high = (r_ctrl0 >> CTRL_DUMMY_HIGH_SHIFT) & 0x1;
438 uint32_t dummy_low = (r_ctrl0 >> CTRL_DUMMY_LOW_SHIFT) & 0x3;
439 uint32_t dummies = ((dummy_high << 2) | dummy_low) * 8;
440
441 if (r_ctrl0 & CTRL_IO_DUAL_ADDR_DATA) {
442 dummies /= 2;
443 }
444
445 return dummies;
446}
447
448static void aspeed_smc_flash_setup(AspeedSMCFlash *fl, uint32_t addr)
449{
450 const AspeedSMCState *s = fl->controller;
451 uint8_t cmd = aspeed_smc_flash_cmd(fl);
452 int i = aspeed_smc_flash_addr_width(fl);
453
454
455 addr = aspeed_smc_check_segment_addr(fl, addr);
456
457 ssi_transfer(s->spi, cmd);
458 while (i--) {
459 if (aspeed_smc_addr_byte_enabled(s, i)) {
460 ssi_transfer(s->spi, (addr >> (i * 8)) & 0xff);
461 }
462 }
463
464
465
466
467
468
469
470 if (aspeed_smc_flash_mode(fl) == CTRL_FREADMODE) {
471 for (i = 0; i < aspeed_smc_flash_dummies(fl); i++) {
472 ssi_transfer(fl->controller->spi, s->regs[R_DUMMY_DATA] & 0xff);
473 }
474 }
475}
476
477static uint64_t aspeed_smc_flash_read(void *opaque, hwaddr addr, unsigned size)
478{
479 AspeedSMCFlash *fl = opaque;
480 AspeedSMCState *s = fl->controller;
481 uint64_t ret = 0;
482 int i;
483
484 switch (aspeed_smc_flash_mode(fl)) {
485 case CTRL_USERMODE:
486 for (i = 0; i < size; i++) {
487 ret |= ssi_transfer(s->spi, 0x0) << (8 * i);
488 }
489 break;
490 case CTRL_READMODE:
491 case CTRL_FREADMODE:
492 aspeed_smc_flash_select(fl);
493 aspeed_smc_flash_setup(fl, addr);
494
495 for (i = 0; i < size; i++) {
496 ret |= ssi_transfer(s->spi, 0x0) << (8 * i);
497 }
498
499 aspeed_smc_flash_unselect(fl);
500 break;
501 default:
502 aspeed_smc_error("invalid flash mode %d", aspeed_smc_flash_mode(fl));
503 }
504
505 trace_aspeed_smc_flash_read(fl->cs, addr, size, ret,
506 aspeed_smc_flash_mode(fl));
507 return ret;
508}
509
510
511
512
513
514typedef enum {
515 READ = 0x3, READ_4 = 0x13,
516 FAST_READ = 0xb, FAST_READ_4 = 0x0c,
517 DOR = 0x3b, DOR_4 = 0x3c,
518 QOR = 0x6b, QOR_4 = 0x6c,
519 DIOR = 0xbb, DIOR_4 = 0xbc,
520 QIOR = 0xeb, QIOR_4 = 0xec,
521
522 PP = 0x2, PP_4 = 0x12,
523 DPP = 0xa2,
524 QPP = 0x32, QPP_4 = 0x34,
525} FlashCMD;
526
527static int aspeed_smc_num_dummies(uint8_t command)
528{
529 switch (command) {
530 case READ:
531 case PP:
532 case DPP:
533 case QPP:
534 case READ_4:
535 case PP_4:
536 case QPP_4:
537 return 0;
538 case FAST_READ:
539 case DOR:
540 case QOR:
541 case FAST_READ_4:
542 case DOR_4:
543 case QOR_4:
544 return 1;
545 case DIOR:
546 case DIOR_4:
547 return 2;
548 case QIOR:
549 case QIOR_4:
550 return 4;
551 default:
552 return -1;
553 }
554}
555
556static bool aspeed_smc_do_snoop(AspeedSMCFlash *fl, uint64_t data,
557 unsigned size)
558{
559 AspeedSMCState *s = fl->controller;
560 uint8_t addr_width = aspeed_smc_flash_addr_width(fl);
561
562 trace_aspeed_smc_do_snoop(fl->cs, s->snoop_index, s->snoop_dummies,
563 (uint8_t) data & 0xff);
564
565 if (s->snoop_index == SNOOP_OFF) {
566 return false;
567
568 } else if (s->snoop_index == SNOOP_START) {
569 uint8_t cmd = data & 0xff;
570 int ndummies = aspeed_smc_num_dummies(cmd);
571
572
573
574
575
576 if (ndummies <= 0) {
577 s->snoop_index = SNOOP_OFF;
578 return false;
579 }
580
581 s->snoop_dummies = ndummies * 8;
582
583 } else if (s->snoop_index >= addr_width + 1) {
584
585
586 for (; s->snoop_dummies; s->snoop_dummies--) {
587 ssi_transfer(s->spi, s->regs[R_DUMMY_DATA] & 0xff);
588 }
589
590
591 if (!s->snoop_dummies) {
592 s->snoop_index = SNOOP_OFF;
593 } else {
594 s->snoop_index += size;
595 }
596
597
598
599
600
601 return true;
602 }
603
604 s->snoop_index += size;
605 return false;
606}
607
608static void aspeed_smc_flash_write(void *opaque, hwaddr addr, uint64_t data,
609 unsigned size)
610{
611 AspeedSMCFlash *fl = opaque;
612 AspeedSMCState *s = fl->controller;
613 int i;
614
615 trace_aspeed_smc_flash_write(fl->cs, addr, size, data,
616 aspeed_smc_flash_mode(fl));
617
618 if (!aspeed_smc_is_writable(fl)) {
619 aspeed_smc_error("flash is not writable at 0x%" HWADDR_PRIx, addr);
620 return;
621 }
622
623 switch (aspeed_smc_flash_mode(fl)) {
624 case CTRL_USERMODE:
625 if (aspeed_smc_do_snoop(fl, data, size)) {
626 break;
627 }
628
629 for (i = 0; i < size; i++) {
630 ssi_transfer(s->spi, (data >> (8 * i)) & 0xff);
631 }
632 break;
633 case CTRL_WRITEMODE:
634 aspeed_smc_flash_select(fl);
635 aspeed_smc_flash_setup(fl, addr);
636
637 for (i = 0; i < size; i++) {
638 ssi_transfer(s->spi, (data >> (8 * i)) & 0xff);
639 }
640
641 aspeed_smc_flash_unselect(fl);
642 break;
643 default:
644 aspeed_smc_error("invalid flash mode %d", aspeed_smc_flash_mode(fl));
645 }
646}
647
648static const MemoryRegionOps aspeed_smc_flash_ops = {
649 .read = aspeed_smc_flash_read,
650 .write = aspeed_smc_flash_write,
651 .endianness = DEVICE_LITTLE_ENDIAN,
652 .valid = {
653 .min_access_size = 1,
654 .max_access_size = 4,
655 },
656};
657
658static void aspeed_smc_flash_update_ctrl(AspeedSMCFlash *fl, uint32_t value)
659{
660 AspeedSMCState *s = fl->controller;
661 bool unselect;
662
663
664 unselect = (value & CTRL_CMD_MODE_MASK) != CTRL_USERMODE;
665
666
667 if (!(s->regs[s->r_ctrl0 + fl->cs] & CTRL_CE_STOP_ACTIVE) &&
668 value & CTRL_CE_STOP_ACTIVE) {
669 unselect = true;
670 }
671
672 s->regs[s->r_ctrl0 + fl->cs] = value;
673
674 s->snoop_index = unselect ? SNOOP_OFF : SNOOP_START;
675
676 aspeed_smc_flash_do_select(fl, unselect);
677}
678
679static void aspeed_smc_reset(DeviceState *d)
680{
681 AspeedSMCState *s = ASPEED_SMC(d);
682 AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s);
683 int i;
684
685 if (asc->resets) {
686 memcpy(s->regs, asc->resets, sizeof s->regs);
687 } else {
688 memset(s->regs, 0, sizeof s->regs);
689 }
690
691
692 for (i = 0; i < s->num_cs; ++i) {
693 s->regs[s->r_ctrl0 + i] |= CTRL_CE_STOP_ACTIVE;
694 qemu_set_irq(s->cs_lines[i], true);
695 }
696
697
698 for (i = 0; i < asc->max_peripherals; ++i) {
699 aspeed_smc_flash_set_segment_region(s, i,
700 asc->segment_to_reg(s, &asc->segments[i]));
701 }
702
703 s->snoop_index = SNOOP_OFF;
704 s->snoop_dummies = 0;
705}
706
707static uint64_t aspeed_smc_read(void *opaque, hwaddr addr, unsigned int size)
708{
709 AspeedSMCState *s = ASPEED_SMC(opaque);
710 AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(opaque);
711
712 addr >>= 2;
713
714 if (addr == s->r_conf ||
715 (addr >= s->r_timings &&
716 addr < s->r_timings + asc->nregs_timings) ||
717 addr == s->r_ce_ctrl ||
718 addr == R_CE_CMD_CTRL ||
719 addr == R_INTR_CTRL ||
720 addr == R_DUMMY_DATA ||
721 (aspeed_smc_has_wdt_control(asc) && addr == R_FMC_WDT2_CTRL) ||
722 (aspeed_smc_has_dma(asc) && addr == R_DMA_CTRL) ||
723 (aspeed_smc_has_dma(asc) && addr == R_DMA_FLASH_ADDR) ||
724 (aspeed_smc_has_dma(asc) && addr == R_DMA_DRAM_ADDR) ||
725 (aspeed_smc_has_dma(asc) && addr == R_DMA_LEN) ||
726 (aspeed_smc_has_dma(asc) && addr == R_DMA_CHECKSUM) ||
727 (addr >= R_SEG_ADDR0 &&
728 addr < R_SEG_ADDR0 + asc->max_peripherals) ||
729 (addr >= s->r_ctrl0 && addr < s->r_ctrl0 + asc->max_peripherals)) {
730
731 trace_aspeed_smc_read(addr << 2, size, s->regs[addr]);
732
733 return s->regs[addr];
734 } else {
735 qemu_log_mask(LOG_UNIMP, "%s: not implemented: 0x%" HWADDR_PRIx "\n",
736 __func__, addr);
737 return -1;
738 }
739}
740
741static uint8_t aspeed_smc_hclk_divisor(uint8_t hclk_mask)
742{
743
744 const uint8_t hclk_divisors[] = {
745 15, 7, 14, 6, 13, 5, 12, 4, 11, 3, 10, 2, 9, 1, 8, 0
746 };
747 int i;
748
749 for (i = 0; i < ARRAY_SIZE(hclk_divisors); i++) {
750 if (hclk_mask == hclk_divisors[i]) {
751 return i + 1;
752 }
753 }
754
755 aspeed_smc_error("invalid HCLK mask %x", hclk_mask);
756 return 0;
757}
758
759
760
761
762
763
764static void aspeed_smc_dma_calibration(AspeedSMCState *s)
765{
766 uint8_t delay =
767 (s->regs[R_DMA_CTRL] >> DMA_CTRL_DELAY_SHIFT) & DMA_CTRL_DELAY_MASK;
768 uint8_t hclk_mask =
769 (s->regs[R_DMA_CTRL] >> DMA_CTRL_FREQ_SHIFT) & DMA_CTRL_FREQ_MASK;
770 uint8_t hclk_div = aspeed_smc_hclk_divisor(hclk_mask);
771 uint32_t hclk_shift = (hclk_div - 1) << 2;
772 uint8_t cs;
773
774
775
776
777
778 if (hclk_div && hclk_div < 6) {
779 s->regs[s->r_timings] &= ~(0xf << hclk_shift);
780 s->regs[s->r_timings] |= delay << hclk_shift;
781 }
782
783
784
785
786
787
788
789 cs = 0;
790 s->regs[s->r_ctrl0 + cs] &=
791 ~(CE_CTRL_CLOCK_FREQ_MASK << CE_CTRL_CLOCK_FREQ_SHIFT);
792 s->regs[s->r_ctrl0 + cs] |= CE_CTRL_CLOCK_FREQ(hclk_div);
793}
794
795
796
797
798
799
800
801static bool aspeed_smc_inject_read_failure(AspeedSMCState *s)
802{
803 uint8_t delay =
804 (s->regs[R_DMA_CTRL] >> DMA_CTRL_DELAY_SHIFT) & DMA_CTRL_DELAY_MASK;
805 uint8_t hclk_mask =
806 (s->regs[R_DMA_CTRL] >> DMA_CTRL_FREQ_SHIFT) & DMA_CTRL_FREQ_MASK;
807
808
809
810
811 switch (aspeed_smc_hclk_divisor(hclk_mask)) {
812 case 4 ... 16:
813 return false;
814 case 3:
815 return (delay & 0x7) < 1;
816 case 2:
817 return (delay & 0x7) < 2;
818 case 1:
819 return true;
820 default:
821 g_assert_not_reached();
822 }
823}
824
825
826
827
828
829static void aspeed_smc_dma_checksum(AspeedSMCState *s)
830{
831 MemTxResult result;
832 uint32_t data;
833
834 if (s->regs[R_DMA_CTRL] & DMA_CTRL_WRITE) {
835 aspeed_smc_error("invalid direction for DMA checksum");
836 return;
837 }
838
839 if (s->regs[R_DMA_CTRL] & DMA_CTRL_CALIB) {
840 aspeed_smc_dma_calibration(s);
841 }
842
843 while (s->regs[R_DMA_LEN]) {
844 data = address_space_ldl_le(&s->flash_as, s->regs[R_DMA_FLASH_ADDR],
845 MEMTXATTRS_UNSPECIFIED, &result);
846 if (result != MEMTX_OK) {
847 aspeed_smc_error("Flash read failed @%08x",
848 s->regs[R_DMA_FLASH_ADDR]);
849 return;
850 }
851 trace_aspeed_smc_dma_checksum(s->regs[R_DMA_FLASH_ADDR], data);
852
853
854
855
856
857 s->regs[R_DMA_CHECKSUM] += data;
858 s->regs[R_DMA_FLASH_ADDR] += 4;
859 s->regs[R_DMA_LEN] -= 4;
860 }
861
862 if (s->inject_failure && aspeed_smc_inject_read_failure(s)) {
863 s->regs[R_DMA_CHECKSUM] = 0xbadc0de;
864 }
865
866}
867
868static void aspeed_smc_dma_rw(AspeedSMCState *s)
869{
870 MemTxResult result;
871 uint32_t data;
872
873 trace_aspeed_smc_dma_rw(s->regs[R_DMA_CTRL] & DMA_CTRL_WRITE ?
874 "write" : "read",
875 s->regs[R_DMA_FLASH_ADDR],
876 s->regs[R_DMA_DRAM_ADDR],
877 s->regs[R_DMA_LEN]);
878 while (s->regs[R_DMA_LEN]) {
879 if (s->regs[R_DMA_CTRL] & DMA_CTRL_WRITE) {
880 data = address_space_ldl_le(&s->dram_as, s->regs[R_DMA_DRAM_ADDR],
881 MEMTXATTRS_UNSPECIFIED, &result);
882 if (result != MEMTX_OK) {
883 aspeed_smc_error("DRAM read failed @%08x",
884 s->regs[R_DMA_DRAM_ADDR]);
885 return;
886 }
887
888 address_space_stl_le(&s->flash_as, s->regs[R_DMA_FLASH_ADDR],
889 data, MEMTXATTRS_UNSPECIFIED, &result);
890 if (result != MEMTX_OK) {
891 aspeed_smc_error("Flash write failed @%08x",
892 s->regs[R_DMA_FLASH_ADDR]);
893 return;
894 }
895 } else {
896 data = address_space_ldl_le(&s->flash_as, s->regs[R_DMA_FLASH_ADDR],
897 MEMTXATTRS_UNSPECIFIED, &result);
898 if (result != MEMTX_OK) {
899 aspeed_smc_error("Flash read failed @%08x",
900 s->regs[R_DMA_FLASH_ADDR]);
901 return;
902 }
903
904 address_space_stl_le(&s->dram_as, s->regs[R_DMA_DRAM_ADDR],
905 data, MEMTXATTRS_UNSPECIFIED, &result);
906 if (result != MEMTX_OK) {
907 aspeed_smc_error("DRAM write failed @%08x",
908 s->regs[R_DMA_DRAM_ADDR]);
909 return;
910 }
911 }
912
913
914
915
916
917 s->regs[R_DMA_FLASH_ADDR] += 4;
918 s->regs[R_DMA_DRAM_ADDR] += 4;
919 s->regs[R_DMA_LEN] -= 4;
920 s->regs[R_DMA_CHECKSUM] += data;
921 }
922}
923
924static void aspeed_smc_dma_stop(AspeedSMCState *s)
925{
926
927
928
929
930 s->regs[R_INTR_CTRL] &= ~INTR_CTRL_DMA_STATUS;
931 s->regs[R_DMA_CHECKSUM] = 0;
932
933
934
935
936
937 qemu_irq_lower(s->irq);
938}
939
940
941
942
943
944static bool aspeed_smc_dma_in_progress(AspeedSMCState *s)
945{
946 return s->regs[R_DMA_CTRL] & DMA_CTRL_ENABLE &&
947 !(s->regs[R_INTR_CTRL] & INTR_CTRL_DMA_STATUS);
948}
949
950static void aspeed_smc_dma_done(AspeedSMCState *s)
951{
952 s->regs[R_INTR_CTRL] |= INTR_CTRL_DMA_STATUS;
953 if (s->regs[R_INTR_CTRL] & INTR_CTRL_DMA_EN) {
954 qemu_irq_raise(s->irq);
955 }
956}
957
958static void aspeed_smc_dma_ctrl(AspeedSMCState *s, uint32_t dma_ctrl)
959{
960 if (!(dma_ctrl & DMA_CTRL_ENABLE)) {
961 s->regs[R_DMA_CTRL] = dma_ctrl;
962
963 aspeed_smc_dma_stop(s);
964 return;
965 }
966
967 if (aspeed_smc_dma_in_progress(s)) {
968 aspeed_smc_error("DMA in progress !");
969 return;
970 }
971
972 s->regs[R_DMA_CTRL] = dma_ctrl;
973
974 if (s->regs[R_DMA_CTRL] & DMA_CTRL_CKSUM) {
975 aspeed_smc_dma_checksum(s);
976 } else {
977 aspeed_smc_dma_rw(s);
978 }
979
980 aspeed_smc_dma_done(s);
981}
982
983static inline bool aspeed_smc_dma_granted(AspeedSMCState *s)
984{
985 AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s);
986
987 if (!(asc->features & ASPEED_SMC_FEATURE_DMA_GRANT)) {
988 return true;
989 }
990
991 if (!(s->regs[R_DMA_CTRL] & DMA_CTRL_GRANT)) {
992 aspeed_smc_error("DMA not granted");
993 return false;
994 }
995
996 return true;
997}
998
999static void aspeed_2600_smc_dma_ctrl(AspeedSMCState *s, uint32_t dma_ctrl)
1000{
1001
1002 dma_ctrl |= s->regs[R_DMA_CTRL] & (DMA_CTRL_REQUEST | DMA_CTRL_GRANT);
1003
1004 if (dma_ctrl == 0xAEED0000) {
1005
1006 s->regs[R_DMA_CTRL] |= (DMA_CTRL_REQUEST | DMA_CTRL_GRANT);
1007 return;
1008 }
1009
1010
1011 if (dma_ctrl == 0xDEEA0000) {
1012 s->regs[R_DMA_CTRL] &= ~(DMA_CTRL_REQUEST | DMA_CTRL_GRANT);
1013 return;
1014 }
1015
1016 if (!aspeed_smc_dma_granted(s)) {
1017 aspeed_smc_error("DMA not granted");
1018 return;
1019 }
1020
1021 aspeed_smc_dma_ctrl(s, dma_ctrl);
1022 s->regs[R_DMA_CTRL] &= ~(DMA_CTRL_REQUEST | DMA_CTRL_GRANT);
1023}
1024
1025static void aspeed_smc_write(void *opaque, hwaddr addr, uint64_t data,
1026 unsigned int size)
1027{
1028 AspeedSMCState *s = ASPEED_SMC(opaque);
1029 AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s);
1030 uint32_t value = data;
1031
1032 trace_aspeed_smc_write(addr, size, data);
1033
1034 addr >>= 2;
1035
1036 if (addr == s->r_conf ||
1037 (addr >= s->r_timings &&
1038 addr < s->r_timings + asc->nregs_timings) ||
1039 addr == s->r_ce_ctrl) {
1040 s->regs[addr] = value;
1041 } else if (addr >= s->r_ctrl0 && addr < s->r_ctrl0 + s->num_cs) {
1042 int cs = addr - s->r_ctrl0;
1043 aspeed_smc_flash_update_ctrl(&s->flashes[cs], value);
1044 } else if (addr >= R_SEG_ADDR0 &&
1045 addr < R_SEG_ADDR0 + asc->max_peripherals) {
1046 int cs = addr - R_SEG_ADDR0;
1047
1048 if (value != s->regs[R_SEG_ADDR0 + cs]) {
1049 aspeed_smc_flash_set_segment(s, cs, value);
1050 }
1051 } else if (addr == R_CE_CMD_CTRL) {
1052 s->regs[addr] = value & 0xff;
1053 } else if (addr == R_DUMMY_DATA) {
1054 s->regs[addr] = value & 0xff;
1055 } else if (aspeed_smc_has_wdt_control(asc) && addr == R_FMC_WDT2_CTRL) {
1056 s->regs[addr] = value & FMC_WDT2_CTRL_EN;
1057 } else if (addr == R_INTR_CTRL) {
1058 s->regs[addr] = value;
1059 } else if (aspeed_smc_has_dma(asc) && addr == R_DMA_CTRL) {
1060 asc->dma_ctrl(s, value);
1061 } else if (aspeed_smc_has_dma(asc) && addr == R_DMA_DRAM_ADDR &&
1062 aspeed_smc_dma_granted(s)) {
1063 s->regs[addr] = DMA_DRAM_ADDR(asc, value);
1064 } else if (aspeed_smc_has_dma(asc) && addr == R_DMA_FLASH_ADDR &&
1065 aspeed_smc_dma_granted(s)) {
1066 s->regs[addr] = DMA_FLASH_ADDR(asc, value);
1067 } else if (aspeed_smc_has_dma(asc) && addr == R_DMA_LEN &&
1068 aspeed_smc_dma_granted(s)) {
1069 s->regs[addr] = DMA_LENGTH(value);
1070 } else {
1071 qemu_log_mask(LOG_UNIMP, "%s: not implemented: 0x%" HWADDR_PRIx "\n",
1072 __func__, addr);
1073 return;
1074 }
1075}
1076
1077static const MemoryRegionOps aspeed_smc_ops = {
1078 .read = aspeed_smc_read,
1079 .write = aspeed_smc_write,
1080 .endianness = DEVICE_LITTLE_ENDIAN,
1081};
1082
1083static void aspeed_smc_instance_init(Object *obj)
1084{
1085 AspeedSMCState *s = ASPEED_SMC(obj);
1086 AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s);
1087 int i;
1088
1089 for (i = 0; i < asc->max_peripherals; i++) {
1090 object_initialize_child(obj, "flash[*]", &s->flashes[i],
1091 TYPE_ASPEED_SMC_FLASH);
1092 }
1093}
1094
1095
1096
1097
1098static void aspeed_smc_dma_setup(AspeedSMCState *s, Error **errp)
1099{
1100 if (!s->dram_mr) {
1101 error_setg(errp, TYPE_ASPEED_SMC ": 'dram' link not set");
1102 return;
1103 }
1104
1105 address_space_init(&s->flash_as, &s->mmio_flash,
1106 TYPE_ASPEED_SMC ".dma-flash");
1107 address_space_init(&s->dram_as, s->dram_mr,
1108 TYPE_ASPEED_SMC ".dma-dram");
1109}
1110
1111static void aspeed_smc_realize(DeviceState *dev, Error **errp)
1112{
1113 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
1114 AspeedSMCState *s = ASPEED_SMC(dev);
1115 AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s);
1116 int i;
1117 hwaddr offset = 0;
1118
1119
1120 s->r_conf = asc->r_conf;
1121 s->r_ce_ctrl = asc->r_ce_ctrl;
1122 s->r_ctrl0 = asc->r_ctrl0;
1123 s->r_timings = asc->r_timings;
1124 s->conf_enable_w0 = asc->conf_enable_w0;
1125
1126
1127 if (s->num_cs > asc->max_peripherals) {
1128 aspeed_smc_error("num_cs cannot exceed: %d", asc->max_peripherals);
1129 s->num_cs = asc->max_peripherals;
1130 }
1131
1132
1133 sysbus_init_irq(sbd, &s->irq);
1134
1135 s->spi = ssi_create_bus(dev, "spi");
1136
1137
1138 s->cs_lines = g_new0(qemu_irq, s->num_cs);
1139
1140 for (i = 0; i < s->num_cs; ++i) {
1141 sysbus_init_irq(sbd, &s->cs_lines[i]);
1142 }
1143
1144
1145 memory_region_init_io(&s->mmio, OBJECT(s), &aspeed_smc_ops, s,
1146 TYPE_ASPEED_SMC, asc->nregs * 4);
1147 sysbus_init_mmio(sbd, &s->mmio);
1148
1149
1150
1151
1152
1153
1154 memory_region_init(&s->mmio_flash_container, OBJECT(s),
1155 TYPE_ASPEED_SMC ".container",
1156 asc->flash_window_size);
1157 sysbus_init_mmio(sbd, &s->mmio_flash_container);
1158
1159 memory_region_init_io(&s->mmio_flash, OBJECT(s),
1160 &aspeed_smc_flash_default_ops, s,
1161 TYPE_ASPEED_SMC ".flash",
1162 asc->flash_window_size);
1163 memory_region_add_subregion(&s->mmio_flash_container, 0x0,
1164 &s->mmio_flash);
1165
1166
1167
1168
1169
1170
1171
1172
1173 for (i = 0; i < asc->max_peripherals; ++i) {
1174 AspeedSMCFlash *fl = &s->flashes[i];
1175
1176 if (!object_property_set_link(OBJECT(fl), "controller", OBJECT(s),
1177 errp)) {
1178 return;
1179 }
1180 if (!object_property_set_uint(OBJECT(fl), "cs", i, errp)) {
1181 return;
1182 }
1183 if (!sysbus_realize(SYS_BUS_DEVICE(fl), errp)) {
1184 return;
1185 }
1186
1187 memory_region_add_subregion(&s->mmio_flash, offset, &fl->mmio);
1188 offset += asc->segments[i].size;
1189 }
1190
1191
1192 if (aspeed_smc_has_dma(asc)) {
1193 aspeed_smc_dma_setup(s, errp);
1194 }
1195}
1196
1197static const VMStateDescription vmstate_aspeed_smc = {
1198 .name = "aspeed.smc",
1199 .version_id = 2,
1200 .minimum_version_id = 2,
1201 .fields = (VMStateField[]) {
1202 VMSTATE_UINT32_ARRAY(regs, AspeedSMCState, ASPEED_SMC_R_MAX),
1203 VMSTATE_UINT8(snoop_index, AspeedSMCState),
1204 VMSTATE_UINT8(snoop_dummies, AspeedSMCState),
1205 VMSTATE_END_OF_LIST()
1206 }
1207};
1208
1209static Property aspeed_smc_properties[] = {
1210 DEFINE_PROP_UINT32("num-cs", AspeedSMCState, num_cs, 1),
1211 DEFINE_PROP_BOOL("inject-failure", AspeedSMCState, inject_failure, false),
1212 DEFINE_PROP_LINK("dram", AspeedSMCState, dram_mr,
1213 TYPE_MEMORY_REGION, MemoryRegion *),
1214 DEFINE_PROP_END_OF_LIST(),
1215};
1216
1217static void aspeed_smc_class_init(ObjectClass *klass, void *data)
1218{
1219 DeviceClass *dc = DEVICE_CLASS(klass);
1220
1221 dc->realize = aspeed_smc_realize;
1222 dc->reset = aspeed_smc_reset;
1223 device_class_set_props(dc, aspeed_smc_properties);
1224 dc->vmsd = &vmstate_aspeed_smc;
1225}
1226
1227static const TypeInfo aspeed_smc_info = {
1228 .name = TYPE_ASPEED_SMC,
1229 .parent = TYPE_SYS_BUS_DEVICE,
1230 .instance_init = aspeed_smc_instance_init,
1231 .instance_size = sizeof(AspeedSMCState),
1232 .class_size = sizeof(AspeedSMCClass),
1233 .class_init = aspeed_smc_class_init,
1234 .abstract = true,
1235};
1236
1237static void aspeed_smc_flash_realize(DeviceState *dev, Error **errp)
1238{
1239 AspeedSMCFlash *s = ASPEED_SMC_FLASH(dev);
1240 AspeedSMCClass *asc;
1241 g_autofree char *name = g_strdup_printf(TYPE_ASPEED_SMC_FLASH ".%d", s->cs);
1242
1243 if (!s->controller) {
1244 error_setg(errp, TYPE_ASPEED_SMC_FLASH ": 'controller' link not set");
1245 return;
1246 }
1247
1248 asc = ASPEED_SMC_GET_CLASS(s->controller);
1249
1250
1251
1252
1253
1254 memory_region_init_io(&s->mmio, OBJECT(s), &aspeed_smc_flash_ops,
1255 s, name, asc->segments[s->cs].size);
1256 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio);
1257}
1258
1259static Property aspeed_smc_flash_properties[] = {
1260 DEFINE_PROP_UINT8("cs", AspeedSMCFlash, cs, 0),
1261 DEFINE_PROP_LINK("controller", AspeedSMCFlash, controller, TYPE_ASPEED_SMC,
1262 AspeedSMCState *),
1263 DEFINE_PROP_END_OF_LIST(),
1264};
1265
1266static void aspeed_smc_flash_class_init(ObjectClass *klass, void *data)
1267{
1268 DeviceClass *dc = DEVICE_CLASS(klass);
1269
1270 dc->desc = "Aspeed SMC Flash device region";
1271 dc->realize = aspeed_smc_flash_realize;
1272 device_class_set_props(dc, aspeed_smc_flash_properties);
1273}
1274
1275static const TypeInfo aspeed_smc_flash_info = {
1276 .name = TYPE_ASPEED_SMC_FLASH,
1277 .parent = TYPE_SYS_BUS_DEVICE,
1278 .instance_size = sizeof(AspeedSMCFlash),
1279 .class_init = aspeed_smc_flash_class_init,
1280};
1281
1282
1283
1284
1285
1286
1287
1288static uint32_t aspeed_smc_segment_to_reg(const AspeedSMCState *s,
1289 const AspeedSegments *seg)
1290{
1291 uint32_t reg = 0;
1292 reg |= ((seg->addr >> 23) & SEG_START_MASK) << SEG_START_SHIFT;
1293 reg |= (((seg->addr + seg->size) >> 23) & SEG_END_MASK) << SEG_END_SHIFT;
1294 return reg;
1295}
1296
1297static void aspeed_smc_reg_to_segment(const AspeedSMCState *s,
1298 uint32_t reg, AspeedSegments *seg)
1299{
1300 seg->addr = ((reg >> SEG_START_SHIFT) & SEG_START_MASK) << 23;
1301 seg->size = (((reg >> SEG_END_SHIFT) & SEG_END_MASK) << 23) - seg->addr;
1302}
1303
1304static const AspeedSegments aspeed_2400_smc_segments[] = {
1305 { 0x10000000, 32 * MiB },
1306};
1307
1308static void aspeed_2400_smc_class_init(ObjectClass *klass, void *data)
1309{
1310 DeviceClass *dc = DEVICE_CLASS(klass);
1311 AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass);
1312
1313 dc->desc = "Aspeed 2400 SMC Controller";
1314 asc->r_conf = R_CONF;
1315 asc->r_ce_ctrl = R_CE_CTRL;
1316 asc->r_ctrl0 = R_CTRL0;
1317 asc->r_timings = R_TIMINGS;
1318 asc->nregs_timings = 1;
1319 asc->conf_enable_w0 = CONF_ENABLE_W0;
1320 asc->max_peripherals = 1;
1321 asc->segments = aspeed_2400_smc_segments;
1322 asc->flash_window_base = 0x10000000;
1323 asc->flash_window_size = 0x6000000;
1324 asc->features = 0x0;
1325 asc->nregs = ASPEED_SMC_R_SMC_MAX;
1326 asc->segment_to_reg = aspeed_smc_segment_to_reg;
1327 asc->reg_to_segment = aspeed_smc_reg_to_segment;
1328 asc->dma_ctrl = aspeed_smc_dma_ctrl;
1329}
1330
1331static const TypeInfo aspeed_2400_smc_info = {
1332 .name = "aspeed.smc-ast2400",
1333 .parent = TYPE_ASPEED_SMC,
1334 .class_init = aspeed_2400_smc_class_init,
1335};
1336
1337static const uint32_t aspeed_2400_fmc_resets[ASPEED_SMC_R_MAX] = {
1338
1339
1340
1341
1342 [R_CONF] = CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE0,
1343};
1344
1345static const AspeedSegments aspeed_2400_fmc_segments[] = {
1346 { 0x20000000, 64 * MiB },
1347 { 0x24000000, 32 * MiB },
1348 { 0x26000000, 32 * MiB },
1349 { 0x28000000, 32 * MiB },
1350 { 0x2A000000, 32 * MiB }
1351};
1352
1353static void aspeed_2400_fmc_class_init(ObjectClass *klass, void *data)
1354{
1355 DeviceClass *dc = DEVICE_CLASS(klass);
1356 AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass);
1357
1358 dc->desc = "Aspeed 2400 FMC Controller";
1359 asc->r_conf = R_CONF;
1360 asc->r_ce_ctrl = R_CE_CTRL;
1361 asc->r_ctrl0 = R_CTRL0;
1362 asc->r_timings = R_TIMINGS;
1363 asc->nregs_timings = 1;
1364 asc->conf_enable_w0 = CONF_ENABLE_W0;
1365 asc->max_peripherals = 5;
1366 asc->segments = aspeed_2400_fmc_segments;
1367 asc->resets = aspeed_2400_fmc_resets;
1368 asc->flash_window_base = 0x20000000;
1369 asc->flash_window_size = 0x10000000;
1370 asc->features = ASPEED_SMC_FEATURE_DMA;
1371 asc->dma_flash_mask = 0x0FFFFFFC;
1372 asc->dma_dram_mask = 0x1FFFFFFC;
1373 asc->nregs = ASPEED_SMC_R_MAX;
1374 asc->segment_to_reg = aspeed_smc_segment_to_reg;
1375 asc->reg_to_segment = aspeed_smc_reg_to_segment;
1376 asc->dma_ctrl = aspeed_smc_dma_ctrl;
1377}
1378
1379static const TypeInfo aspeed_2400_fmc_info = {
1380 .name = "aspeed.fmc-ast2400",
1381 .parent = TYPE_ASPEED_SMC,
1382 .class_init = aspeed_2400_fmc_class_init,
1383};
1384
1385static const AspeedSegments aspeed_2400_spi1_segments[] = {
1386 { 0x30000000, 64 * MiB },
1387};
1388
1389static int aspeed_2400_spi1_addr_width(const AspeedSMCState *s)
1390{
1391 return s->regs[R_SPI_CTRL0] & CTRL_AST2400_SPI_4BYTE ? 4 : 3;
1392}
1393
1394static void aspeed_2400_spi1_class_init(ObjectClass *klass, void *data)
1395{
1396 DeviceClass *dc = DEVICE_CLASS(klass);
1397 AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass);
1398
1399 dc->desc = "Aspeed 2400 SPI1 Controller";
1400 asc->r_conf = R_SPI_CONF;
1401 asc->r_ce_ctrl = 0xff;
1402 asc->r_ctrl0 = R_SPI_CTRL0;
1403 asc->r_timings = R_SPI_TIMINGS;
1404 asc->nregs_timings = 1;
1405 asc->conf_enable_w0 = SPI_CONF_ENABLE_W0;
1406 asc->max_peripherals = 1;
1407 asc->segments = aspeed_2400_spi1_segments;
1408 asc->flash_window_base = 0x30000000;
1409 asc->flash_window_size = 0x10000000;
1410 asc->features = 0x0;
1411 asc->nregs = ASPEED_SMC_R_SPI_MAX;
1412 asc->segment_to_reg = aspeed_smc_segment_to_reg;
1413 asc->reg_to_segment = aspeed_smc_reg_to_segment;
1414 asc->dma_ctrl = aspeed_smc_dma_ctrl;
1415 asc->addr_width = aspeed_2400_spi1_addr_width;
1416}
1417
1418static const TypeInfo aspeed_2400_spi1_info = {
1419 .name = "aspeed.spi1-ast2400",
1420 .parent = TYPE_ASPEED_SMC,
1421 .class_init = aspeed_2400_spi1_class_init,
1422};
1423
1424static const uint32_t aspeed_2500_fmc_resets[ASPEED_SMC_R_MAX] = {
1425 [R_CONF] = (CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE0 |
1426 CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE1),
1427};
1428
1429static const AspeedSegments aspeed_2500_fmc_segments[] = {
1430 { 0x20000000, 128 * MiB },
1431 { 0x28000000, 32 * MiB },
1432 { 0x2A000000, 32 * MiB },
1433};
1434
1435static void aspeed_2500_fmc_class_init(ObjectClass *klass, void *data)
1436{
1437 DeviceClass *dc = DEVICE_CLASS(klass);
1438 AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass);
1439
1440 dc->desc = "Aspeed 2600 FMC Controller";
1441 asc->r_conf = R_CONF;
1442 asc->r_ce_ctrl = R_CE_CTRL;
1443 asc->r_ctrl0 = R_CTRL0;
1444 asc->r_timings = R_TIMINGS;
1445 asc->nregs_timings = 1;
1446 asc->conf_enable_w0 = CONF_ENABLE_W0;
1447 asc->max_peripherals = 3;
1448 asc->segments = aspeed_2500_fmc_segments;
1449 asc->resets = aspeed_2500_fmc_resets;
1450 asc->flash_window_base = 0x20000000;
1451 asc->flash_window_size = 0x10000000;
1452 asc->features = ASPEED_SMC_FEATURE_DMA;
1453 asc->dma_flash_mask = 0x0FFFFFFC;
1454 asc->dma_dram_mask = 0x3FFFFFFC;
1455 asc->nregs = ASPEED_SMC_R_MAX;
1456 asc->segment_to_reg = aspeed_smc_segment_to_reg;
1457 asc->reg_to_segment = aspeed_smc_reg_to_segment;
1458 asc->dma_ctrl = aspeed_smc_dma_ctrl;
1459}
1460
1461static const TypeInfo aspeed_2500_fmc_info = {
1462 .name = "aspeed.fmc-ast2500",
1463 .parent = TYPE_ASPEED_SMC,
1464 .class_init = aspeed_2500_fmc_class_init,
1465};
1466
1467static const AspeedSegments aspeed_2500_spi1_segments[] = {
1468 { 0x30000000, 32 * MiB },
1469 { 0x32000000, 96 * MiB },
1470};
1471
1472static void aspeed_2500_spi1_class_init(ObjectClass *klass, void *data)
1473{
1474 DeviceClass *dc = DEVICE_CLASS(klass);
1475 AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass);
1476
1477 dc->desc = "Aspeed 2600 SPI1 Controller";
1478 asc->r_conf = R_CONF;
1479 asc->r_ce_ctrl = R_CE_CTRL;
1480 asc->r_ctrl0 = R_CTRL0;
1481 asc->r_timings = R_TIMINGS;
1482 asc->nregs_timings = 1;
1483 asc->conf_enable_w0 = CONF_ENABLE_W0;
1484 asc->max_peripherals = 2;
1485 asc->segments = aspeed_2500_spi1_segments;
1486 asc->flash_window_base = 0x30000000;
1487 asc->flash_window_size = 0x8000000;
1488 asc->features = 0x0;
1489 asc->nregs = ASPEED_SMC_R_MAX;
1490 asc->segment_to_reg = aspeed_smc_segment_to_reg;
1491 asc->reg_to_segment = aspeed_smc_reg_to_segment;
1492 asc->dma_ctrl = aspeed_smc_dma_ctrl;
1493}
1494
1495static const TypeInfo aspeed_2500_spi1_info = {
1496 .name = "aspeed.spi1-ast2500",
1497 .parent = TYPE_ASPEED_SMC,
1498 .class_init = aspeed_2500_spi1_class_init,
1499};
1500
1501static const AspeedSegments aspeed_2500_spi2_segments[] = {
1502 { 0x38000000, 32 * MiB },
1503 { 0x3A000000, 96 * MiB },
1504};
1505
1506static void aspeed_2500_spi2_class_init(ObjectClass *klass, void *data)
1507{
1508 DeviceClass *dc = DEVICE_CLASS(klass);
1509 AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass);
1510
1511 dc->desc = "Aspeed 2600 SPI2 Controller";
1512 asc->r_conf = R_CONF;
1513 asc->r_ce_ctrl = R_CE_CTRL;
1514 asc->r_ctrl0 = R_CTRL0;
1515 asc->r_timings = R_TIMINGS;
1516 asc->nregs_timings = 1;
1517 asc->conf_enable_w0 = CONF_ENABLE_W0;
1518 asc->max_peripherals = 2;
1519 asc->segments = aspeed_2500_spi2_segments;
1520 asc->flash_window_base = 0x38000000;
1521 asc->flash_window_size = 0x8000000;
1522 asc->features = 0x0;
1523 asc->nregs = ASPEED_SMC_R_MAX;
1524 asc->segment_to_reg = aspeed_smc_segment_to_reg;
1525 asc->reg_to_segment = aspeed_smc_reg_to_segment;
1526 asc->dma_ctrl = aspeed_smc_dma_ctrl;
1527}
1528
1529static const TypeInfo aspeed_2500_spi2_info = {
1530 .name = "aspeed.spi2-ast2500",
1531 .parent = TYPE_ASPEED_SMC,
1532 .class_init = aspeed_2500_spi2_class_init,
1533};
1534
1535
1536
1537
1538
1539
1540
1541
1542#define AST2600_SEG_ADDR_MASK 0x0ff00000
1543
1544static uint32_t aspeed_2600_smc_segment_to_reg(const AspeedSMCState *s,
1545 const AspeedSegments *seg)
1546{
1547 uint32_t reg = 0;
1548
1549
1550 if (!seg->size) {
1551 return 0;
1552 }
1553
1554 reg |= (seg->addr & AST2600_SEG_ADDR_MASK) >> 16;
1555 reg |= (seg->addr + seg->size - 1) & AST2600_SEG_ADDR_MASK;
1556 return reg;
1557}
1558
1559static void aspeed_2600_smc_reg_to_segment(const AspeedSMCState *s,
1560 uint32_t reg, AspeedSegments *seg)
1561{
1562 uint32_t start_offset = (reg << 16) & AST2600_SEG_ADDR_MASK;
1563 uint32_t end_offset = reg & AST2600_SEG_ADDR_MASK;
1564 AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s);
1565
1566 if (reg) {
1567 seg->addr = asc->flash_window_base + start_offset;
1568 seg->size = end_offset + MiB - start_offset;
1569 } else {
1570 seg->addr = asc->flash_window_base;
1571 seg->size = 0;
1572 }
1573}
1574
1575static const uint32_t aspeed_2600_fmc_resets[ASPEED_SMC_R_MAX] = {
1576 [R_CONF] = (CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE0 |
1577 CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE1 |
1578 CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE2),
1579};
1580
1581static const AspeedSegments aspeed_2600_fmc_segments[] = {
1582 { 0x0, 128 * MiB },
1583 { 128 * MiB, 128 * MiB },
1584 { 0x0, 0 },
1585};
1586
1587static void aspeed_2600_fmc_class_init(ObjectClass *klass, void *data)
1588{
1589 DeviceClass *dc = DEVICE_CLASS(klass);
1590 AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass);
1591
1592 dc->desc = "Aspeed 2600 FMC Controller";
1593 asc->r_conf = R_CONF;
1594 asc->r_ce_ctrl = R_CE_CTRL;
1595 asc->r_ctrl0 = R_CTRL0;
1596 asc->r_timings = R_TIMINGS;
1597 asc->nregs_timings = 1;
1598 asc->conf_enable_w0 = CONF_ENABLE_W0;
1599 asc->max_peripherals = 3;
1600 asc->segments = aspeed_2600_fmc_segments;
1601 asc->resets = aspeed_2600_fmc_resets;
1602 asc->flash_window_base = 0x20000000;
1603 asc->flash_window_size = 0x10000000;
1604 asc->features = ASPEED_SMC_FEATURE_DMA |
1605 ASPEED_SMC_FEATURE_WDT_CONTROL;
1606 asc->dma_flash_mask = 0x0FFFFFFC;
1607 asc->dma_dram_mask = 0x3FFFFFFC;
1608 asc->nregs = ASPEED_SMC_R_MAX;
1609 asc->segment_to_reg = aspeed_2600_smc_segment_to_reg;
1610 asc->reg_to_segment = aspeed_2600_smc_reg_to_segment;
1611 asc->dma_ctrl = aspeed_2600_smc_dma_ctrl;
1612}
1613
1614static const TypeInfo aspeed_2600_fmc_info = {
1615 .name = "aspeed.fmc-ast2600",
1616 .parent = TYPE_ASPEED_SMC,
1617 .class_init = aspeed_2600_fmc_class_init,
1618};
1619
1620static const AspeedSegments aspeed_2600_spi1_segments[] = {
1621 { 0x0, 128 * MiB },
1622 { 0x0, 0 },
1623};
1624
1625static void aspeed_2600_spi1_class_init(ObjectClass *klass, void *data)
1626{
1627 DeviceClass *dc = DEVICE_CLASS(klass);
1628 AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass);
1629
1630 dc->desc = "Aspeed 2600 SPI1 Controller";
1631 asc->r_conf = R_CONF;
1632 asc->r_ce_ctrl = R_CE_CTRL;
1633 asc->r_ctrl0 = R_CTRL0;
1634 asc->r_timings = R_TIMINGS;
1635 asc->nregs_timings = 2;
1636 asc->conf_enable_w0 = CONF_ENABLE_W0;
1637 asc->max_peripherals = 2;
1638 asc->segments = aspeed_2600_spi1_segments;
1639 asc->flash_window_base = 0x30000000;
1640 asc->flash_window_size = 0x10000000;
1641 asc->features = ASPEED_SMC_FEATURE_DMA |
1642 ASPEED_SMC_FEATURE_DMA_GRANT;
1643 asc->dma_flash_mask = 0x0FFFFFFC;
1644 asc->dma_dram_mask = 0x3FFFFFFC;
1645 asc->nregs = ASPEED_SMC_R_MAX;
1646 asc->segment_to_reg = aspeed_2600_smc_segment_to_reg;
1647 asc->reg_to_segment = aspeed_2600_smc_reg_to_segment;
1648 asc->dma_ctrl = aspeed_2600_smc_dma_ctrl;
1649}
1650
1651static const TypeInfo aspeed_2600_spi1_info = {
1652 .name = "aspeed.spi1-ast2600",
1653 .parent = TYPE_ASPEED_SMC,
1654 .class_init = aspeed_2600_spi1_class_init,
1655};
1656
1657static const AspeedSegments aspeed_2600_spi2_segments[] = {
1658 { 0x0, 128 * MiB },
1659 { 0x0, 0 },
1660 { 0x0, 0 },
1661};
1662
1663static void aspeed_2600_spi2_class_init(ObjectClass *klass, void *data)
1664{
1665 DeviceClass *dc = DEVICE_CLASS(klass);
1666 AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass);
1667
1668 dc->desc = "Aspeed 2600 SPI2 Controller";
1669 asc->r_conf = R_CONF;
1670 asc->r_ce_ctrl = R_CE_CTRL;
1671 asc->r_ctrl0 = R_CTRL0;
1672 asc->r_timings = R_TIMINGS;
1673 asc->nregs_timings = 3;
1674 asc->conf_enable_w0 = CONF_ENABLE_W0;
1675 asc->max_peripherals = 3;
1676 asc->segments = aspeed_2600_spi2_segments;
1677 asc->flash_window_base = 0x50000000;
1678 asc->flash_window_size = 0x10000000;
1679 asc->features = ASPEED_SMC_FEATURE_DMA |
1680 ASPEED_SMC_FEATURE_DMA_GRANT;
1681 asc->dma_flash_mask = 0x0FFFFFFC;
1682 asc->dma_dram_mask = 0x3FFFFFFC;
1683 asc->nregs = ASPEED_SMC_R_MAX;
1684 asc->segment_to_reg = aspeed_2600_smc_segment_to_reg;
1685 asc->reg_to_segment = aspeed_2600_smc_reg_to_segment;
1686 asc->dma_ctrl = aspeed_2600_smc_dma_ctrl;
1687}
1688
1689static const TypeInfo aspeed_2600_spi2_info = {
1690 .name = "aspeed.spi2-ast2600",
1691 .parent = TYPE_ASPEED_SMC,
1692 .class_init = aspeed_2600_spi2_class_init,
1693};
1694
1695static void aspeed_smc_register_types(void)
1696{
1697 type_register_static(&aspeed_smc_flash_info);
1698 type_register_static(&aspeed_smc_info);
1699 type_register_static(&aspeed_2400_smc_info);
1700 type_register_static(&aspeed_2400_fmc_info);
1701 type_register_static(&aspeed_2400_spi1_info);
1702 type_register_static(&aspeed_2500_fmc_info);
1703 type_register_static(&aspeed_2500_spi1_info);
1704 type_register_static(&aspeed_2500_spi2_info);
1705 type_register_static(&aspeed_2600_fmc_info);
1706 type_register_static(&aspeed_2600_spi1_info);
1707 type_register_static(&aspeed_2600_spi2_info);
1708}
1709
1710type_init(aspeed_smc_register_types)
1711