qemu/hw/usb/hcd-xhci-pci.c
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   1/*
   2 * USB xHCI controller with PCI bus emulation
   3 *
   4 * SPDX-FileCopyrightText: 2011 Securiforest
   5 * SPDX-FileContributor: Hector Martin <hector@marcansoft.com>
   6 * SPDX-sourceInfo: Based on usb-ohci.c, emulates Renesas NEC USB 3.0
   7 * SPDX-FileCopyrightText: 2020 Xilinx
   8 * SPDX-FileContributor: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
   9 * SPDX-sourceInfo: Moved the pci specific content for hcd-xhci.c to
  10 *                  hcd-xhci-pci.c
  11 *
  12 * This library is free software; you can redistribute it and/or
  13 * modify it under the terms of the GNU Lesser General Public
  14 * License as published by the Free Software Foundation; either
  15 * version 2.1 of the License, or (at your option) any later version.
  16 *
  17 * This library is distributed in the hope that it will be useful,
  18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  20 * Lesser General Public License for more details.
  21 *
  22 * You should have received a copy of the GNU Lesser General Public
  23 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  24 */
  25#include "qemu/osdep.h"
  26#include "hw/pci/pci.h"
  27#include "hw/qdev-properties.h"
  28#include "migration/vmstate.h"
  29#include "hw/pci/msi.h"
  30#include "hw/pci/msix.h"
  31#include "hcd-xhci-pci.h"
  32#include "trace.h"
  33#include "qapi/error.h"
  34
  35#define OFF_MSIX_TABLE  0x3000
  36#define OFF_MSIX_PBA    0x3800
  37
  38static void xhci_pci_intr_update(XHCIState *xhci, int n, bool enable)
  39{
  40    XHCIPciState *s = container_of(xhci, XHCIPciState, xhci);
  41    PCIDevice *pci_dev = PCI_DEVICE(s);
  42
  43    if (!msix_enabled(pci_dev)) {
  44        return;
  45    }
  46    if (enable == !!xhci->intr[n].msix_used) {
  47        return;
  48    }
  49    if (enable) {
  50        trace_usb_xhci_irq_msix_use(n);
  51        msix_vector_use(pci_dev, n);
  52        xhci->intr[n].msix_used = true;
  53    } else {
  54        trace_usb_xhci_irq_msix_unuse(n);
  55        msix_vector_unuse(pci_dev, n);
  56        xhci->intr[n].msix_used = false;
  57    }
  58}
  59
  60static bool xhci_pci_intr_raise(XHCIState *xhci, int n, bool level)
  61{
  62    XHCIPciState *s = container_of(xhci, XHCIPciState, xhci);
  63    PCIDevice *pci_dev = PCI_DEVICE(s);
  64
  65    if (n == 0 &&
  66        !(msix_enabled(pci_dev) ||
  67         msi_enabled(pci_dev))) {
  68        pci_set_irq(pci_dev, level);
  69    }
  70
  71    if (msix_enabled(pci_dev) && level) {
  72        msix_notify(pci_dev, n);
  73        return true;
  74    }
  75
  76    if (msi_enabled(pci_dev) && level) {
  77        msi_notify(pci_dev, n);
  78        return true;
  79    }
  80
  81    return false;
  82}
  83
  84static void xhci_pci_reset(DeviceState *dev)
  85{
  86    XHCIPciState *s = XHCI_PCI(dev);
  87
  88    device_legacy_reset(DEVICE(&s->xhci));
  89}
  90
  91static int xhci_pci_vmstate_post_load(void *opaque, int version_id)
  92{
  93    XHCIPciState *s = XHCI_PCI(opaque);
  94    PCIDevice *pci_dev = PCI_DEVICE(s);
  95    int intr;
  96
  97   for (intr = 0; intr < s->xhci.numintrs; intr++) {
  98        if (s->xhci.intr[intr].msix_used) {
  99            msix_vector_use(pci_dev, intr);
 100        } else {
 101            msix_vector_unuse(pci_dev, intr);
 102        }
 103    }
 104   return 0;
 105}
 106
 107static void usb_xhci_pci_realize(struct PCIDevice *dev, Error **errp)
 108{
 109    int ret;
 110    Error *err = NULL;
 111    XHCIPciState *s = XHCI_PCI(dev);
 112
 113    dev->config[PCI_CLASS_PROG] = 0x30;    /* xHCI */
 114    dev->config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */
 115    dev->config[PCI_CACHE_LINE_SIZE] = 0x10;
 116    dev->config[0x60] = 0x30; /* release number */
 117
 118    object_property_set_link(OBJECT(&s->xhci), "host", OBJECT(s), NULL);
 119    s->xhci.intr_update = xhci_pci_intr_update;
 120    s->xhci.intr_raise = xhci_pci_intr_raise;
 121    if (!qdev_realize(DEVICE(&s->xhci), NULL, errp)) {
 122        return;
 123    }
 124    if (strcmp(object_get_typename(OBJECT(dev)), TYPE_NEC_XHCI) == 0) {
 125        s->xhci.nec_quirks = true;
 126    }
 127
 128    if (s->msi != ON_OFF_AUTO_OFF) {
 129        ret = msi_init(dev, 0x70, s->xhci.numintrs, true, false, &err);
 130        /*
 131         * Any error other than -ENOTSUP(board's MSI support is broken)
 132         * is a programming error
 133         */
 134        assert(!ret || ret == -ENOTSUP);
 135        if (ret && s->msi == ON_OFF_AUTO_ON) {
 136            /* Can't satisfy user's explicit msi=on request, fail */
 137            error_append_hint(&err, "You have to use msi=auto (default) or "
 138                    "msi=off with this machine type.\n");
 139            error_propagate(errp, err);
 140            return;
 141        }
 142        assert(!err || s->msi == ON_OFF_AUTO_AUTO);
 143        /* With msi=auto, we fall back to MSI off silently */
 144        error_free(err);
 145    }
 146    pci_register_bar(dev, 0,
 147                     PCI_BASE_ADDRESS_SPACE_MEMORY |
 148                     PCI_BASE_ADDRESS_MEM_TYPE_64,
 149                     &s->xhci.mem);
 150
 151    if (pci_bus_is_express(pci_get_bus(dev)) ||
 152        xhci_get_flag(&s->xhci, XHCI_FLAG_FORCE_PCIE_ENDCAP)) {
 153        ret = pcie_endpoint_cap_init(dev, 0xa0);
 154        assert(ret > 0);
 155    }
 156
 157    if (s->msix != ON_OFF_AUTO_OFF) {
 158        /* TODO check for errors, and should fail when msix=on */
 159        msix_init(dev, s->xhci.numintrs,
 160                  &s->xhci.mem, 0, OFF_MSIX_TABLE,
 161                  &s->xhci.mem, 0, OFF_MSIX_PBA,
 162                  0x90, NULL);
 163    }
 164    s->xhci.as = pci_get_address_space(dev);
 165}
 166
 167static void usb_xhci_pci_exit(PCIDevice *dev)
 168{
 169    XHCIPciState *s = XHCI_PCI(dev);
 170    /* destroy msix memory region */
 171    if (dev->msix_table && dev->msix_pba
 172        && dev->msix_entry_used) {
 173        msix_uninit(dev, &s->xhci.mem, &s->xhci.mem);
 174    }
 175}
 176
 177static const VMStateDescription vmstate_xhci_pci = {
 178    .name = "xhci",
 179    .version_id = 1,
 180    .post_load = xhci_pci_vmstate_post_load,
 181    .fields = (VMStateField[]) {
 182        VMSTATE_PCI_DEVICE(parent_obj, XHCIPciState),
 183        VMSTATE_MSIX(parent_obj, XHCIPciState),
 184        VMSTATE_STRUCT(xhci, XHCIPciState, 1, vmstate_xhci, XHCIState),
 185        VMSTATE_END_OF_LIST()
 186    }
 187};
 188
 189static void xhci_instance_init(Object *obj)
 190{
 191    XHCIPciState *s = XHCI_PCI(obj);
 192    /*
 193     * QEMU_PCI_CAP_EXPRESS initialization does not depend on QEMU command
 194     * line, therefore, no need to wait to realize like other devices
 195     */
 196    PCI_DEVICE(obj)->cap_present |= QEMU_PCI_CAP_EXPRESS;
 197    object_initialize_child(obj, "xhci-core", &s->xhci, TYPE_XHCI);
 198    qdev_alias_all_properties(DEVICE(&s->xhci), obj);
 199}
 200
 201static void xhci_class_init(ObjectClass *klass, void *data)
 202{
 203    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 204    DeviceClass *dc = DEVICE_CLASS(klass);
 205
 206    dc->reset   = xhci_pci_reset;
 207    dc->vmsd    = &vmstate_xhci_pci;
 208    set_bit(DEVICE_CATEGORY_USB, dc->categories);
 209    k->realize      = usb_xhci_pci_realize;
 210    k->exit         = usb_xhci_pci_exit;
 211    k->class_id     = PCI_CLASS_SERIAL_USB;
 212}
 213
 214static const TypeInfo xhci_pci_info = {
 215    .name          = TYPE_XHCI_PCI,
 216    .parent        = TYPE_PCI_DEVICE,
 217    .instance_size = sizeof(XHCIPciState),
 218    .class_init    = xhci_class_init,
 219    .instance_init = xhci_instance_init,
 220    .abstract      = true,
 221    .interfaces = (InterfaceInfo[]) {
 222        { INTERFACE_PCIE_DEVICE },
 223        { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 224        { }
 225    },
 226};
 227
 228static void qemu_xhci_class_init(ObjectClass *klass, void *data)
 229{
 230    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 231
 232    k->vendor_id    = PCI_VENDOR_ID_REDHAT;
 233    k->device_id    = PCI_DEVICE_ID_REDHAT_XHCI;
 234    k->revision     = 0x01;
 235}
 236
 237static void qemu_xhci_instance_init(Object *obj)
 238{
 239    XHCIPciState *s = XHCI_PCI(obj);
 240    XHCIState *xhci = &s->xhci;
 241
 242    s->msi      = ON_OFF_AUTO_OFF;
 243    s->msix     = ON_OFF_AUTO_AUTO;
 244    xhci->numintrs = XHCI_MAXINTRS;
 245    xhci->numslots = XHCI_MAXSLOTS;
 246    xhci_set_flag(xhci, XHCI_FLAG_SS_FIRST);
 247}
 248
 249static const TypeInfo qemu_xhci_info = {
 250    .name          = TYPE_QEMU_XHCI,
 251    .parent        = TYPE_XHCI_PCI,
 252    .class_init    = qemu_xhci_class_init,
 253    .instance_init = qemu_xhci_instance_init,
 254};
 255
 256static void xhci_register_types(void)
 257{
 258    type_register_static(&xhci_pci_info);
 259    type_register_static(&qemu_xhci_info);
 260}
 261
 262type_init(xhci_register_types)
 263