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22#include "qemu/osdep.h"
23
24#include "qemu/module.h"
25#include "qemu/timer.h"
26#include "sysemu/watchdog.h"
27#include "hw/pci/pci.h"
28#include "migration/vmstate.h"
29#include "qom/object.h"
30
31
32
33#ifdef I6300ESB_DEBUG
34#define i6300esb_debug(fs,...) \
35 fprintf(stderr,"i6300esb: %s: "fs,__func__,##__VA_ARGS__)
36#else
37#define i6300esb_debug(fs,...)
38#endif
39
40
41#define ESB_CONFIG_REG 0x60
42#define ESB_LOCK_REG 0x68
43
44
45#define ESB_TIMER1_REG 0x00
46#define ESB_TIMER2_REG 0x04
47#define ESB_GINTSR_REG 0x08
48#define ESB_RELOAD_REG 0x0c
49
50
51#define ESB_WDT_FUNC (0x01 << 2)
52#define ESB_WDT_ENABLE (0x01 << 1)
53#define ESB_WDT_LOCK (0x01 << 0)
54
55
56#define ESB_WDT_REBOOT (0x01 << 5)
57#define ESB_WDT_FREQ (0x01 << 2)
58#define ESB_WDT_INTTYPE (0x11 << 0)
59
60
61#define ESB_WDT_RELOAD (0x01 << 8)
62
63
64#define ESB_UNLOCK1 0x80
65#define ESB_UNLOCK2 0x86
66
67
68struct I6300State {
69 PCIDevice dev;
70 MemoryRegion io_mem;
71
72 int reboot_enabled;
73
74
75
76 int clock_scale;
77#define CLOCK_SCALE_1KHZ 0
78#define CLOCK_SCALE_1MHZ 1
79
80 int int_type;
81#define INT_TYPE_IRQ 0
82#define INT_TYPE_SMI 2
83#define INT_TYPE_DISABLED 3
84
85 int free_run;
86 int locked;
87 int enabled;
88
89 QEMUTimer *timer;
90
91 uint32_t timer1_preload;
92 uint32_t timer2_preload;
93 int stage;
94
95 int unlock_state;
96
97
98
99
100 int previous_reboot_flag;
101
102
103};
104
105
106#define TYPE_WATCHDOG_I6300ESB_DEVICE "i6300esb"
107OBJECT_DECLARE_SIMPLE_TYPE(I6300State, WATCHDOG_I6300ESB_DEVICE)
108
109
110
111
112static void i6300esb_restart_timer(I6300State *d, int stage)
113{
114 int64_t timeout;
115
116 if (!d->enabled)
117 return;
118
119 d->stage = stage;
120
121 if (d->stage <= 1)
122 timeout = d->timer1_preload;
123 else
124 timeout = d->timer2_preload;
125
126 if (d->clock_scale == CLOCK_SCALE_1KHZ)
127 timeout <<= 15;
128 else
129 timeout <<= 5;
130
131
132
133 timeout = timeout * 30;
134
135 i6300esb_debug("stage %d, timeout %" PRIi64 "\n", d->stage, timeout);
136
137 timer_mod(d->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + timeout);
138}
139
140
141static void i6300esb_disable_timer(I6300State *d)
142{
143 i6300esb_debug("timer disabled\n");
144
145 timer_del(d->timer);
146}
147
148static void i6300esb_reset(DeviceState *dev)
149{
150 PCIDevice *pdev = PCI_DEVICE(dev);
151 I6300State *d = WATCHDOG_I6300ESB_DEVICE(pdev);
152
153 i6300esb_debug("I6300State = %p\n", d);
154
155 i6300esb_disable_timer(d);
156
157
158
159 d->reboot_enabled = 1;
160 d->clock_scale = CLOCK_SCALE_1KHZ;
161 d->int_type = INT_TYPE_IRQ;
162 d->free_run = 0;
163 d->locked = 0;
164 d->enabled = 0;
165 d->timer1_preload = 0xfffff;
166 d->timer2_preload = 0xfffff;
167 d->stage = 1;
168 d->unlock_state = 0;
169}
170
171
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173
174
175
176
177
178static void i6300esb_timer_expired(void *vp)
179{
180 I6300State *d = vp;
181
182 i6300esb_debug("stage %d\n", d->stage);
183
184 if (d->stage == 1) {
185
186 switch (d->int_type) {
187 case INT_TYPE_IRQ:
188 fprintf(stderr, "i6300esb_timer_expired: I would send APIC 1 INT 10 here if I knew how (XXX)\n");
189 break;
190 case INT_TYPE_SMI:
191 fprintf(stderr, "i6300esb_timer_expired: I would send SMI here if I knew how (XXX)\n");
192 break;
193 }
194
195
196 i6300esb_restart_timer(d, 2);
197 } else {
198
199 if (d->reboot_enabled) {
200 d->previous_reboot_flag = 1;
201 watchdog_perform_action();
202 i6300esb_reset(DEVICE(d));
203 }
204
205
206 if (d->free_run)
207 i6300esb_restart_timer(d, 1);
208 }
209}
210
211static void i6300esb_config_write(PCIDevice *dev, uint32_t addr,
212 uint32_t data, int len)
213{
214 I6300State *d = WATCHDOG_I6300ESB_DEVICE(dev);
215 int old;
216
217 i6300esb_debug("addr = %x, data = %x, len = %d\n", addr, data, len);
218
219 if (addr == ESB_CONFIG_REG && len == 2) {
220 d->reboot_enabled = (data & ESB_WDT_REBOOT) == 0;
221 d->clock_scale =
222 (data & ESB_WDT_FREQ) != 0 ? CLOCK_SCALE_1MHZ : CLOCK_SCALE_1KHZ;
223 d->int_type = (data & ESB_WDT_INTTYPE);
224 } else if (addr == ESB_LOCK_REG && len == 1) {
225 if (!d->locked) {
226 d->locked = (data & ESB_WDT_LOCK) != 0;
227 d->free_run = (data & ESB_WDT_FUNC) != 0;
228 old = d->enabled;
229 d->enabled = (data & ESB_WDT_ENABLE) != 0;
230 if (!old && d->enabled)
231 i6300esb_restart_timer(d, 1);
232 else if (!d->enabled)
233 i6300esb_disable_timer(d);
234 }
235 } else {
236 pci_default_write_config(dev, addr, data, len);
237 }
238}
239
240static uint32_t i6300esb_config_read(PCIDevice *dev, uint32_t addr, int len)
241{
242 I6300State *d = WATCHDOG_I6300ESB_DEVICE(dev);
243 uint32_t data;
244
245 i6300esb_debug ("addr = %x, len = %d\n", addr, len);
246
247 if (addr == ESB_CONFIG_REG && len == 2) {
248 data =
249 (d->reboot_enabled ? 0 : ESB_WDT_REBOOT) |
250 (d->clock_scale == CLOCK_SCALE_1MHZ ? ESB_WDT_FREQ : 0) |
251 d->int_type;
252 return data;
253 } else if (addr == ESB_LOCK_REG && len == 1) {
254 data =
255 (d->free_run ? ESB_WDT_FUNC : 0) |
256 (d->locked ? ESB_WDT_LOCK : 0) |
257 (d->enabled ? ESB_WDT_ENABLE : 0);
258 return data;
259 } else {
260 return pci_default_read_config(dev, addr, len);
261 }
262}
263
264static uint32_t i6300esb_mem_readb(void *vp, hwaddr addr)
265{
266 i6300esb_debug ("addr = %x\n", (int) addr);
267
268 return 0;
269}
270
271static uint32_t i6300esb_mem_readw(void *vp, hwaddr addr)
272{
273 uint32_t data = 0;
274 I6300State *d = vp;
275
276 i6300esb_debug("addr = %x\n", (int) addr);
277
278 if (addr == 0xc) {
279
280
281
282
283 data = d->previous_reboot_flag ? 0x1200 : 0;
284 }
285
286 return data;
287}
288
289static uint32_t i6300esb_mem_readl(void *vp, hwaddr addr)
290{
291 i6300esb_debug("addr = %x\n", (int) addr);
292
293 return 0;
294}
295
296static void i6300esb_mem_writeb(void *vp, hwaddr addr, uint32_t val)
297{
298 I6300State *d = vp;
299
300 i6300esb_debug("addr = %x, val = %x\n", (int) addr, val);
301
302 if (addr == 0xc && val == 0x80)
303 d->unlock_state = 1;
304 else if (addr == 0xc && val == 0x86 && d->unlock_state == 1)
305 d->unlock_state = 2;
306}
307
308static void i6300esb_mem_writew(void *vp, hwaddr addr, uint32_t val)
309{
310 I6300State *d = vp;
311
312 i6300esb_debug("addr = %x, val = %x\n", (int) addr, val);
313
314 if (addr == 0xc && val == 0x80)
315 d->unlock_state = 1;
316 else if (addr == 0xc && val == 0x86 && d->unlock_state == 1)
317 d->unlock_state = 2;
318 else {
319 if (d->unlock_state == 2) {
320 if (addr == 0xc) {
321 if ((val & 0x100) != 0)
322
323
324
325 i6300esb_restart_timer(d, 1);
326
327
328
329
330
331 if ((val & 0x200) != 0 || (val & 0x1000) != 0) {
332 d->previous_reboot_flag = 0;
333 }
334 }
335
336 d->unlock_state = 0;
337 }
338 }
339}
340
341static void i6300esb_mem_writel(void *vp, hwaddr addr, uint32_t val)
342{
343 I6300State *d = vp;
344
345 i6300esb_debug ("addr = %x, val = %x\n", (int) addr, val);
346
347 if (addr == 0xc && val == 0x80)
348 d->unlock_state = 1;
349 else if (addr == 0xc && val == 0x86 && d->unlock_state == 1)
350 d->unlock_state = 2;
351 else {
352 if (d->unlock_state == 2) {
353 if (addr == 0)
354 d->timer1_preload = val & 0xfffff;
355 else if (addr == 4)
356 d->timer2_preload = val & 0xfffff;
357
358 d->unlock_state = 0;
359 }
360 }
361}
362
363static uint64_t i6300esb_mem_readfn(void *opaque, hwaddr addr, unsigned size)
364{
365 switch (size) {
366 case 1:
367 return i6300esb_mem_readb(opaque, addr);
368 case 2:
369 return i6300esb_mem_readw(opaque, addr);
370 case 4:
371 return i6300esb_mem_readl(opaque, addr);
372 default:
373 g_assert_not_reached();
374 }
375}
376
377static void i6300esb_mem_writefn(void *opaque, hwaddr addr,
378 uint64_t value, unsigned size)
379{
380 switch (size) {
381 case 1:
382 i6300esb_mem_writeb(opaque, addr, value);
383 break;
384 case 2:
385 i6300esb_mem_writew(opaque, addr, value);
386 break;
387 case 4:
388 i6300esb_mem_writel(opaque, addr, value);
389 break;
390 default:
391 g_assert_not_reached();
392 }
393}
394
395static const MemoryRegionOps i6300esb_ops = {
396 .read = i6300esb_mem_readfn,
397 .write = i6300esb_mem_writefn,
398 .valid.min_access_size = 1,
399 .valid.max_access_size = 4,
400 .endianness = DEVICE_LITTLE_ENDIAN,
401};
402
403static const VMStateDescription vmstate_i6300esb = {
404 .name = "i6300esb_wdt",
405
406
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410
411
412
413
414
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416
417
418
419 .version_id = 10000,
420 .minimum_version_id = 1,
421 .fields = (VMStateField[]) {
422 VMSTATE_PCI_DEVICE(dev, I6300State),
423 VMSTATE_INT32(reboot_enabled, I6300State),
424 VMSTATE_INT32(clock_scale, I6300State),
425 VMSTATE_INT32(int_type, I6300State),
426 VMSTATE_INT32(free_run, I6300State),
427 VMSTATE_INT32(locked, I6300State),
428 VMSTATE_INT32(enabled, I6300State),
429 VMSTATE_TIMER_PTR(timer, I6300State),
430 VMSTATE_UINT32(timer1_preload, I6300State),
431 VMSTATE_UINT32(timer2_preload, I6300State),
432 VMSTATE_INT32(stage, I6300State),
433 VMSTATE_INT32(unlock_state, I6300State),
434 VMSTATE_INT32(previous_reboot_flag, I6300State),
435 VMSTATE_END_OF_LIST()
436 }
437};
438
439static void i6300esb_realize(PCIDevice *dev, Error **errp)
440{
441 I6300State *d = WATCHDOG_I6300ESB_DEVICE(dev);
442
443 i6300esb_debug("I6300State = %p\n", d);
444
445 d->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, i6300esb_timer_expired, d);
446 d->previous_reboot_flag = 0;
447
448 memory_region_init_io(&d->io_mem, OBJECT(d), &i6300esb_ops, d,
449 "i6300esb", 0x10);
450 pci_register_bar(&d->dev, 0, 0, &d->io_mem);
451}
452
453static void i6300esb_exit(PCIDevice *dev)
454{
455 I6300State *d = WATCHDOG_I6300ESB_DEVICE(dev);
456
457 timer_free(d->timer);
458}
459
460static WatchdogTimerModel model = {
461 .wdt_name = "i6300esb",
462 .wdt_description = "Intel 6300ESB",
463};
464
465static void i6300esb_class_init(ObjectClass *klass, void *data)
466{
467 DeviceClass *dc = DEVICE_CLASS(klass);
468 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
469
470 k->config_read = i6300esb_config_read;
471 k->config_write = i6300esb_config_write;
472 k->realize = i6300esb_realize;
473 k->exit = i6300esb_exit;
474 k->vendor_id = PCI_VENDOR_ID_INTEL;
475 k->device_id = PCI_DEVICE_ID_INTEL_ESB_9;
476 k->class_id = PCI_CLASS_SYSTEM_OTHER;
477 dc->reset = i6300esb_reset;
478 dc->vmsd = &vmstate_i6300esb;
479 set_bit(DEVICE_CATEGORY_WATCHDOG, dc->categories);
480 dc->desc = "Intel 6300ESB";
481}
482
483static const TypeInfo i6300esb_info = {
484 .name = TYPE_WATCHDOG_I6300ESB_DEVICE,
485 .parent = TYPE_PCI_DEVICE,
486 .instance_size = sizeof(I6300State),
487 .class_init = i6300esb_class_init,
488 .interfaces = (InterfaceInfo[]) {
489 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
490 { },
491 },
492};
493
494static void i6300esb_register_types(void)
495{
496 watchdog_add_model(&model);
497 type_register_static(&i6300esb_info);
498}
499
500type_init(i6300esb_register_types)
501