LXR qemu/include/hw/adc/aspeed

   1/*
   2 * Aspeed ADC
   3 *
   4 * Copyright 2017-2021 IBM Corp.
   5 *
   6 * Andrew Jeffery <andrew@aj.id.au>
   7 *
   8 * SPDX-License-Identifier: GPL-2.0-or-later
   9 */
  10
  11#ifndef HW_ADC_ASPEED_ADC_H
  12#define HW_ADC_ASPEED_ADC_H
  13
  14#include "hw/sysbus.h"
  15
  16#define TYPE_ASPEED_ADC "aspeed.adc"
  17#define TYPE_ASPEED_2400_ADC TYPE_ASPEED_ADC "-ast2400"
  18#define TYPE_ASPEED_2500_ADC TYPE_ASPEED_ADC "-ast2500"
  19#define TYPE_ASPEED_2600_ADC TYPE_ASPEED_ADC "-ast2600"
  20OBJECT_DECLARE_TYPE(AspeedADCState, AspeedADCClass, ASPEED_ADC)
  21
  22#define TYPE_ASPEED_ADC_ENGINE "aspeed.adc.engine"
  23OBJECT_DECLARE_SIMPLE_TYPE(AspeedADCEngineState, ASPEED_ADC_ENGINE)
  24
  25#define ASPEED_ADC_NR_CHANNELS 16
  26#define ASPEED_ADC_NR_REGS     (0xD0 >> 2)
  27
  28struct AspeedADCEngineState {
  29    /* <private> */
  30    SysBusDevice parent;
  31
  32    MemoryRegion mmio;
  33    qemu_irq irq;
  34    uint32_t engine_id;
  35    uint32_t nr_channels;
  36    uint32_t regs[ASPEED_ADC_NR_REGS];
  37};
  38
  39struct AspeedADCState {
  40    /* <private> */
  41    SysBusDevice parent;
  42
  43    MemoryRegion mmio;
  44    qemu_irq irq;
  45
  46    AspeedADCEngineState engines[2];
  47};
  48
  49struct AspeedADCClass {
  50    SysBusDeviceClass parent_class;
  51
  52    uint32_t nr_engines;
  53};
  54
  55#endif /* HW_ADC_ASPEED_ADC_H */
  56