LXR qemu/include/hw/arm/aspeed

   1/*
   2 * ASPEED SoC family
   3 *
   4 * Andrew Jeffery <andrew@aj.id.au>
   5 *
   6 * Copyright 2016 IBM Corp.
   7 *
   8 * This code is licensed under the GPL version 2 or later.  See
   9 * the COPYING file in the top-level directory.
  10 */
  11
  12#ifndef ASPEED_SOC_H
  13#define ASPEED_SOC_H
  14
  15#include "hw/cpu/a15mpcore.h"
  16#include "hw/intc/aspeed_vic.h"
  17#include "hw/misc/aspeed_scu.h"
  18#include "hw/adc/aspeed_adc.h"
  19#include "hw/misc/aspeed_sdmc.h"
  20#include "hw/misc/aspeed_xdma.h"
  21#include "hw/timer/aspeed_timer.h"
  22#include "hw/rtc/aspeed_rtc.h"
  23#include "hw/i2c/aspeed_i2c.h"
  24#include "hw/ssi/aspeed_smc.h"
  25#include "hw/misc/aspeed_hace.h"
  26#include "hw/watchdog/wdt_aspeed.h"
  27#include "hw/net/ftgmac100.h"
  28#include "target/arm/cpu.h"
  29#include "hw/gpio/aspeed_gpio.h"
  30#include "hw/sd/aspeed_sdhci.h"
  31#include "hw/usb/hcd-ehci.h"
  32#include "qom/object.h"
  33#include "hw/misc/aspeed_lpc.h"
  34
  35#define ASPEED_SPIS_NUM  2
  36#define ASPEED_EHCIS_NUM 2
  37#define ASPEED_WDTS_NUM  4
  38#define ASPEED_CPUS_NUM  2
  39#define ASPEED_MACS_NUM  4
  40
  41struct AspeedSoCState {
  42    /*< private >*/
  43    DeviceState parent;
  44
  45    /*< public >*/
  46    ARMCPU cpu[ASPEED_CPUS_NUM];
  47    A15MPPrivState     a7mpcore;
  48    MemoryRegion *dram_mr;
  49    MemoryRegion sram;
  50    AspeedVICState vic;
  51    AspeedRtcState rtc;
  52    AspeedTimerCtrlState timerctrl;
  53    AspeedI2CState i2c;
  54    AspeedSCUState scu;
  55    AspeedHACEState hace;
  56    AspeedXDMAState xdma;
  57    AspeedADCState adc;
  58    AspeedSMCState fmc;
  59    AspeedSMCState spi[ASPEED_SPIS_NUM];
  60    EHCISysBusState ehci[ASPEED_EHCIS_NUM];
  61    AspeedSDMCState sdmc;
  62    AspeedWDTState wdt[ASPEED_WDTS_NUM];
  63    FTGMAC100State ftgmac100[ASPEED_MACS_NUM];
  64    AspeedMiiState mii[ASPEED_MACS_NUM];
  65    AspeedGPIOState gpio;
  66    AspeedGPIOState gpio_1_8v;
  67    AspeedSDHCIState sdhci;
  68    AspeedSDHCIState emmc;
  69    AspeedLPCState lpc;
  70    uint32_t uart_default;
  71};
  72
  73#define TYPE_ASPEED_SOC "aspeed-soc"
  74OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC)
  75
  76struct AspeedSoCClass {
  77    DeviceClass parent_class;
  78
  79    const char *name;
  80    const char *cpu_type;
  81    uint32_t silicon_rev;
  82    uint64_t sram_size;
  83    int spis_num;
  84    int ehcis_num;
  85    int wdts_num;
  86    int macs_num;
  87    const int *irqmap;
  88    const hwaddr *memmap;
  89    uint32_t num_cpus;
  90};
  91
  92
  93enum {
  94    ASPEED_DEV_IOMEM,
  95    ASPEED_DEV_UART1,
  96    ASPEED_DEV_UART2,
  97    ASPEED_DEV_UART3,
  98    ASPEED_DEV_UART4,
  99    ASPEED_DEV_UART5,
 100    ASPEED_DEV_VUART,
 101    ASPEED_DEV_FMC,
 102    ASPEED_DEV_SPI1,
 103    ASPEED_DEV_SPI2,
 104    ASPEED_DEV_EHCI1,
 105    ASPEED_DEV_EHCI2,
 106    ASPEED_DEV_VIC,
 107    ASPEED_DEV_SDMC,
 108    ASPEED_DEV_SCU,
 109    ASPEED_DEV_ADC,
 110    ASPEED_DEV_VIDEO,
 111    ASPEED_DEV_SRAM,
 112    ASPEED_DEV_SDHCI,
 113    ASPEED_DEV_GPIO,
 114    ASPEED_DEV_GPIO_1_8V,
 115    ASPEED_DEV_RTC,
 116    ASPEED_DEV_TIMER1,
 117    ASPEED_DEV_TIMER2,
 118    ASPEED_DEV_TIMER3,
 119    ASPEED_DEV_TIMER4,
 120    ASPEED_DEV_TIMER5,
 121    ASPEED_DEV_TIMER6,
 122    ASPEED_DEV_TIMER7,
 123    ASPEED_DEV_TIMER8,
 124    ASPEED_DEV_WDT,
 125    ASPEED_DEV_PWM,
 126    ASPEED_DEV_LPC,
 127    ASPEED_DEV_IBT,
 128    ASPEED_DEV_I2C,
 129    ASPEED_DEV_ETH1,
 130    ASPEED_DEV_ETH2,
 131    ASPEED_DEV_ETH3,
 132    ASPEED_DEV_ETH4,
 133    ASPEED_DEV_MII1,
 134    ASPEED_DEV_MII2,
 135    ASPEED_DEV_MII3,
 136    ASPEED_DEV_MII4,
 137    ASPEED_DEV_SDRAM,
 138    ASPEED_DEV_XDMA,
 139    ASPEED_DEV_EMMC,
 140    ASPEED_DEV_KCS,
 141    ASPEED_DEV_HACE,
 142};
 143
 144#endif /* ASPEED_SOC_H */
 145