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24#ifndef EXYNOS4210_H
25#define EXYNOS4210_H
26
27#include "hw/or-irq.h"
28#include "hw/sysbus.h"
29#include "target/arm/cpu-qom.h"
30#include "qom/object.h"
31
32#define EXYNOS4210_NCPUS 2
33
34#define EXYNOS4210_DRAM0_BASE_ADDR 0x40000000
35#define EXYNOS4210_DRAM1_BASE_ADDR 0xa0000000
36#define EXYNOS4210_DRAM_MAX_SIZE 0x60000000
37
38#define EXYNOS4210_IROM_BASE_ADDR 0x00000000
39#define EXYNOS4210_IROM_SIZE 0x00010000
40#define EXYNOS4210_IROM_MIRROR_BASE_ADDR 0x02000000
41#define EXYNOS4210_IROM_MIRROR_SIZE 0x00010000
42
43#define EXYNOS4210_IRAM_BASE_ADDR 0x02020000
44#define EXYNOS4210_IRAM_SIZE 0x00020000
45
46
47#define EXYNOS4210_SMP_BOOT_ADDR EXYNOS4210_IROM_BASE_ADDR
48#define EXYNOS4210_SMP_BOOT_SIZE 0x1000
49#define EXYNOS4210_BASE_BOOT_ADDR EXYNOS4210_DRAM0_BASE_ADDR
50
51#define EXYNOS4210_SECOND_CPU_BOOTREG 0x10020814
52
53#define EXYNOS4210_SMP_PRIVATE_BASE_ADDR 0x10500000
54#define EXYNOS4210_L2X0_BASE_ADDR 0x10502000
55
56
57
58
59#define EXYNOS4210_IRQ_GATE_NINPUTS 2
60
61#define EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ 64
62#define EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ 16
63#define EXYNOS4210_MAX_INT_COMBINER_IN_IRQ \
64 (EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ * 8)
65#define EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ \
66 (EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ * 8)
67
68#define EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit) ((grp)*8 + (bit))
69#define EXYNOS4210_COMBINER_GET_GRP_NUM(irq) ((irq) / 8)
70#define EXYNOS4210_COMBINER_GET_BIT_NUM(irq) \
71 ((irq) - 8 * EXYNOS4210_COMBINER_GET_GRP_NUM(irq))
72
73
74#define EXYNOS4210_EXT_GIC_NIRQ (160-32)
75#define EXYNOS4210_INT_GIC_NIRQ 64
76
77#define EXYNOS4210_I2C_NUMBER 9
78
79#define EXYNOS4210_NUM_DMA 3
80
81typedef struct Exynos4210Irq {
82 qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
83 qemu_irq ext_combiner_irq[EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ];
84 qemu_irq int_gic_irq[EXYNOS4210_INT_GIC_NIRQ];
85 qemu_irq ext_gic_irq[EXYNOS4210_EXT_GIC_NIRQ];
86 qemu_irq board_irqs[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
87} Exynos4210Irq;
88
89struct Exynos4210State {
90
91 SysBusDevice parent_obj;
92
93 ARMCPU *cpu[EXYNOS4210_NCPUS];
94 Exynos4210Irq irqs;
95 qemu_irq *irq_table;
96
97 MemoryRegion chipid_mem;
98 MemoryRegion iram_mem;
99 MemoryRegion irom_mem;
100 MemoryRegion irom_alias_mem;
101 MemoryRegion boot_secondary;
102 MemoryRegion bootreg_mem;
103 I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER];
104 qemu_or_irq pl330_irq_orgate[EXYNOS4210_NUM_DMA];
105};
106
107#define TYPE_EXYNOS4210_SOC "exynos4210"
108OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210State, EXYNOS4210_SOC)
109
110void exynos4210_write_secondary(ARMCPU *cpu,
111 const struct arm_boot_info *info);
112
113
114qemu_irq *exynos4210_init_irq(Exynos4210Irq *env);
115
116
117
118void exynos4210_init_board_irqs(Exynos4210Irq *s);
119
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123
124uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit);
125
126
127
128
129void exynos4210_combiner_get_gpioin(Exynos4210Irq *irqs, DeviceState *dev,
130 int ext);
131
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133
134
135DeviceState *exynos4210_uart_create(hwaddr addr,
136 int fifo_size,
137 int channel,
138 Chardev *chr,
139 qemu_irq irq);
140
141#endif
142