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10#ifndef PXA_H
11#define PXA_H
12
13#include "exec/memory.h"
14#include "target/arm/cpu-qom.h"
15#include "hw/pcmcia.h"
16#include "qom/object.h"
17
18
19# define PXA2XX_PIC_SSP3 0
20# define PXA2XX_PIC_USBH2 2
21# define PXA2XX_PIC_USBH1 3
22# define PXA2XX_PIC_KEYPAD 4
23# define PXA2XX_PIC_PWRI2C 6
24# define PXA25X_PIC_HWUART 7
25# define PXA27X_PIC_OST_4_11 7
26# define PXA2XX_PIC_GPIO_0 8
27# define PXA2XX_PIC_GPIO_1 9
28# define PXA2XX_PIC_GPIO_X 10
29# define PXA2XX_PIC_I2S 13
30# define PXA26X_PIC_ASSP 15
31# define PXA25X_PIC_NSSP 16
32# define PXA27X_PIC_SSP2 16
33# define PXA2XX_PIC_LCD 17
34# define PXA2XX_PIC_I2C 18
35# define PXA2XX_PIC_ICP 19
36# define PXA2XX_PIC_STUART 20
37# define PXA2XX_PIC_BTUART 21
38# define PXA2XX_PIC_FFUART 22
39# define PXA2XX_PIC_MMC 23
40# define PXA2XX_PIC_SSP 24
41# define PXA2XX_PIC_DMA 25
42# define PXA2XX_PIC_OST_0 26
43# define PXA2XX_PIC_RTC1HZ 30
44# define PXA2XX_PIC_RTCALARM 31
45
46
47# define PXA2XX_RX_RQ_I2S 2
48# define PXA2XX_TX_RQ_I2S 3
49# define PXA2XX_RX_RQ_BTUART 4
50# define PXA2XX_TX_RQ_BTUART 5
51# define PXA2XX_RX_RQ_FFUART 6
52# define PXA2XX_TX_RQ_FFUART 7
53# define PXA2XX_RX_RQ_SSP1 13
54# define PXA2XX_TX_RQ_SSP1 14
55# define PXA2XX_RX_RQ_SSP2 15
56# define PXA2XX_TX_RQ_SSP2 16
57# define PXA2XX_RX_RQ_ICP 17
58# define PXA2XX_TX_RQ_ICP 18
59# define PXA2XX_RX_RQ_STUART 19
60# define PXA2XX_TX_RQ_STUART 20
61# define PXA2XX_RX_RQ_MMCI 21
62# define PXA2XX_TX_RQ_MMCI 22
63# define PXA2XX_USB_RQ(x) ((x) + 24)
64# define PXA2XX_RX_RQ_SSP3 66
65# define PXA2XX_TX_RQ_SSP3 67
66
67# define PXA2XX_SDRAM_BASE 0xa0000000
68# define PXA2XX_INTERNAL_BASE 0x5c000000
69# define PXA2XX_INTERNAL_SIZE 0x40000
70
71
72DeviceState *pxa2xx_pic_init(hwaddr base, ARMCPU *cpu);
73
74
75DeviceState *pxa2xx_gpio_init(hwaddr base,
76 ARMCPU *cpu, DeviceState *pic, int lines);
77void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler);
78
79
80DeviceState *pxa255_dma_init(hwaddr base, qemu_irq irq);
81DeviceState *pxa27x_dma_init(hwaddr base, qemu_irq irq);
82
83
84typedef struct PXA2xxLCDState PXA2xxLCDState;
85PXA2xxLCDState *pxa2xx_lcdc_init(MemoryRegion *sysmem,
86 hwaddr base, qemu_irq irq);
87void pxa2xx_lcd_vsync_notifier(PXA2xxLCDState *s, qemu_irq handler);
88
89
90#define TYPE_PXA2XX_MMCI "pxa2xx-mmci"
91OBJECT_DECLARE_SIMPLE_TYPE(PXA2xxMMCIState, PXA2XX_MMCI)
92
93PXA2xxMMCIState *pxa2xx_mmci_init(MemoryRegion *sysmem,
94 hwaddr base,
95 qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma);
96void pxa2xx_mmci_handlers(PXA2xxMMCIState *s, qemu_irq readonly,
97 qemu_irq coverswitch);
98
99
100#define TYPE_PXA2XX_PCMCIA "pxa2xx-pcmcia"
101OBJECT_DECLARE_SIMPLE_TYPE(PXA2xxPCMCIAState, PXA2XX_PCMCIA)
102
103PXA2xxPCMCIAState *pxa2xx_pcmcia_init(MemoryRegion *sysmem,
104 hwaddr base);
105int pxa2xx_pcmcia_attach(void *opaque, PCMCIACardState *card);
106int pxa2xx_pcmcia_detach(void *opaque);
107void pxa2xx_pcmcia_set_irq_cb(void *opaque, qemu_irq irq, qemu_irq cd_irq);
108
109
110struct keymap {
111 int8_t column;
112 int8_t row;
113};
114typedef struct PXA2xxKeyPadState PXA2xxKeyPadState;
115PXA2xxKeyPadState *pxa27x_keypad_init(MemoryRegion *sysmem,
116 hwaddr base,
117 qemu_irq irq);
118void pxa27x_register_keypad(PXA2xxKeyPadState *kp,
119 const struct keymap *map, int size);
120
121
122typedef struct PXA2xxI2CState PXA2xxI2CState;
123PXA2xxI2CState *pxa2xx_i2c_init(hwaddr base,
124 qemu_irq irq, uint32_t page_size);
125I2CBus *pxa2xx_i2c_bus(PXA2xxI2CState *s);
126
127#define TYPE_PXA2XX_I2C "pxa2xx_i2c"
128typedef struct PXA2xxI2SState PXA2xxI2SState;
129OBJECT_DECLARE_SIMPLE_TYPE(PXA2xxI2CState, PXA2XX_I2C)
130
131#define TYPE_PXA2XX_FIR "pxa2xx-fir"
132OBJECT_DECLARE_SIMPLE_TYPE(PXA2xxFIrState, PXA2XX_FIR)
133
134typedef struct {
135 ARMCPU *cpu;
136 DeviceState *pic;
137 qemu_irq reset;
138 MemoryRegion sdram;
139 MemoryRegion internal;
140 MemoryRegion cm_iomem;
141 MemoryRegion mm_iomem;
142 MemoryRegion pm_iomem;
143 DeviceState *dma;
144 DeviceState *gpio;
145 PXA2xxLCDState *lcd;
146 SSIBus **ssp;
147 PXA2xxI2CState *i2c[2];
148 PXA2xxMMCIState *mmc;
149 PXA2xxPCMCIAState *pcmcia[2];
150 PXA2xxI2SState *i2s;
151 PXA2xxFIrState *fir;
152 PXA2xxKeyPadState *kp;
153
154
155 hwaddr pm_base;
156 uint32_t pm_regs[0x40];
157
158
159 hwaddr cm_base;
160 uint32_t cm_regs[4];
161 uint32_t clkcfg;
162
163
164 hwaddr mm_base;
165 uint32_t mm_regs[0x1a];
166
167
168 uint32_t pmnc;
169} PXA2xxState;
170
171struct PXA2xxI2SState {
172 MemoryRegion iomem;
173 qemu_irq irq;
174 qemu_irq rx_dma;
175 qemu_irq tx_dma;
176 void (*data_req)(void *, int, int);
177
178 uint32_t control[2];
179 uint32_t status;
180 uint32_t mask;
181 uint32_t clk;
182
183 int enable;
184 int rx_len;
185 int tx_len;
186 void (*codec_out)(void *, uint32_t);
187 uint32_t (*codec_in)(void *);
188 void *opaque;
189
190 int fifo_len;
191 uint32_t fifo[16];
192};
193
194# define PA_FMT "0x%08lx"
195
196PXA2xxState *pxa270_init(MemoryRegion *address_space, unsigned int sdram_size,
197 const char *revision);
198PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size);
199
200#endif
201
