1/* 2 * Model of the Xilinx Versal 3 * 4 * Copyright (c) 2018 Xilinx Inc. 5 * Written by Edgar E. Iglesias 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 or 9 * (at your option) any later version. 10 */ 11 12#ifndef XLNX_VERSAL_H 13#define XLNX_VERSAL_H 14 15#include "hw/sysbus.h" 16#include "hw/arm/boot.h" 17#include "hw/or-irq.h" 18#include "hw/sd/sdhci.h" 19#include "hw/intc/arm_gicv3.h" 20#include "hw/char/pl011.h" 21#include "hw/dma/xlnx-zdma.h" 22#include "hw/net/cadence_gem.h" 23#include "hw/rtc/xlnx-zynqmp-rtc.h" 24#include "qom/object.h" 25#include "hw/usb/xlnx-usb-subsystem.h" 26#include "hw/misc/xlnx-versal-xramc.h" 27#include "hw/nvram/xlnx-bbram.h" 28#include "hw/nvram/xlnx-versal-efuse.h" 29 30#define TYPE_XLNX_VERSAL "xlnx-versal" 31OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL) 32 33#define XLNX_VERSAL_NR_ACPUS 2 34#define XLNX_VERSAL_NR_UARTS 2 35#define XLNX_VERSAL_NR_GEMS 2 36#define XLNX_VERSAL_NR_ADMAS 8 37#define XLNX_VERSAL_NR_SDS 2 38#define XLNX_VERSAL_NR_XRAM 4 39#define XLNX_VERSAL_NR_IRQS 192 40 41struct Versal { 42 /*< private >*/ 43 SysBusDevice parent_obj; 44 45 /*< public >*/ 46 struct { 47 struct { 48 MemoryRegion mr; 49 ARMCPU cpu[XLNX_VERSAL_NR_ACPUS]; 50 GICv3State gic; 51 } apu; 52 } fpd; 53 54 MemoryRegion mr_ps; 55 56 struct { 57 /* 4 ranges to access DDR. */ 58 MemoryRegion mr_ddr_ranges[4]; 59 } noc; 60 61 struct { 62 MemoryRegion mr_ocm; 63 64 struct { 65 PL011State uart[XLNX_VERSAL_NR_UARTS]; 66 CadenceGEMState gem[XLNX_VERSAL_NR_GEMS]; 67 XlnxZDMA adma[XLNX_VERSAL_NR_ADMAS]; 68 VersalUsb2 usb; 69 } iou; 70 71 struct { 72 qemu_or_irq irq_orgate; 73 XlnxXramCtrl ctrl[XLNX_VERSAL_NR_XRAM]; 74 } xram; 75 } lpd; 76 77 /* The Platform Management Controller subsystem. */ 78 struct { 79 struct { 80 SDHCIState sd[XLNX_VERSAL_NR_SDS]; 81 } iou; 82 83 XlnxZynqMPRTC rtc; 84 XlnxBBRam bbram; 85 XlnxEFuse efuse; 86 XlnxVersalEFuseCtrl efuse_ctrl; 87 XlnxVersalEFuseCache efuse_cache; 88 } pmc; 89 90 struct { 91 MemoryRegion *mr_ddr; 92 uint32_t psci_conduit; 93 } cfg; 94}; 95 96/* Memory-map and IRQ definitions. Copied a subset from 97 * auto-generated files. */ 98 99#define VERSAL_GIC_MAINT_IRQ 9 100#define VERSAL_TIMER_VIRT_IRQ 11 101#define VERSAL_TIMER_S_EL1_IRQ 13 102#define VERSAL_TIMER_NS_EL1_IRQ 14 103#define VERSAL_TIMER_NS_EL2_IRQ 10 104 105#define VERSAL_UART0_IRQ_0 18 106#define VERSAL_UART1_IRQ_0 19 107#define VERSAL_USB0_IRQ_0 22 108#define VERSAL_GEM0_IRQ_0 56 109#define VERSAL_GEM0_WAKE_IRQ_0 57 110#define VERSAL_GEM1_IRQ_0 58 111#define VERSAL_GEM1_WAKE_IRQ_0 59 112#define VERSAL_ADMA_IRQ_0 60 113#define VERSAL_XRAM_IRQ_0 79 114#define VERSAL_BBRAM_APB_IRQ_0 121 115#define VERSAL_RTC_APB_ERR_IRQ 121 116#define VERSAL_SD0_IRQ_0 126 117#define VERSAL_EFUSE_IRQ 139 118#define VERSAL_RTC_ALARM_IRQ 142 119#define VERSAL_RTC_SECONDS_IRQ 143 120 121/* Architecturally reserved IRQs suitable for virtualization. */ 122#define VERSAL_RSVD_IRQ_FIRST 111 123#define VERSAL_RSVD_IRQ_LAST 118 124 125#define MM_TOP_RSVD 0xa0000000U 126#define MM_TOP_RSVD_SIZE 0x4000000 127#define MM_GIC_APU_DIST_MAIN 0xf9000000U 128#define MM_GIC_APU_DIST_MAIN_SIZE 0x10000 129#define MM_GIC_APU_REDIST_0 0xf9080000U 130#define MM_GIC_APU_REDIST_0_SIZE 0x80000 131 132#define MM_UART0 0xff000000U 133#define MM_UART0_SIZE 0x10000 134#define MM_UART1 0xff010000U 135#define MM_UART1_SIZE 0x10000 136 137#define MM_GEM0 0xff0c0000U 138#define MM_GEM0_SIZE 0x10000 139#define MM_GEM1 0xff0d0000U 140#define MM_GEM1_SIZE 0x10000 141 142#define MM_ADMA_CH0 0xffa80000U 143#define MM_ADMA_CH0_SIZE 0x10000 144 145#define MM_OCM 0xfffc0000U 146#define MM_OCM_SIZE 0x40000 147 148#define MM_XRAM 0xfe800000 149#define MM_XRAMC 0xff8e0000 150#define MM_XRAMC_SIZE 0x10000 151 152#define MM_USB2_CTRL_REGS 0xFF9D0000 153#define MM_USB2_CTRL_REGS_SIZE 0x10000 154 155#define MM_USB_0 0xFE200000 156#define MM_USB_0_SIZE 0x10000 157 158#define MM_TOP_DDR 0x0 159#define MM_TOP_DDR_SIZE 0x80000000U 160#define MM_TOP_DDR_2 0x800000000ULL 161#define MM_TOP_DDR_2_SIZE 0x800000000ULL 162#define MM_TOP_DDR_3 0xc000000000ULL 163#define MM_TOP_DDR_3_SIZE 0x4000000000ULL 164#define MM_TOP_DDR_4 0x10000000000ULL 165#define MM_TOP_DDR_4_SIZE 0xb780000000ULL 166 167#define MM_PSM_START 0xffc80000U 168#define MM_PSM_END 0xffcf0000U 169 170#define MM_CRL 0xff5e0000U 171#define MM_CRL_SIZE 0x300000 172#define MM_IOU_SCNTR 0xff130000U 173#define MM_IOU_SCNTR_SIZE 0x10000 174#define MM_IOU_SCNTRS 0xff140000U 175#define MM_IOU_SCNTRS_SIZE 0x10000 176#define MM_FPD_CRF 0xfd1a0000U 177#define MM_FPD_CRF_SIZE 0x140000 178#define MM_FPD_FPD_APU 0xfd5c0000 179#define MM_FPD_FPD_APU_SIZE 0x100 180 181#define MM_PMC_SD0 0xf1040000U 182#define MM_PMC_SD0_SIZE 0x10000 183#define MM_PMC_BBRAM_CTRL 0xf11f0000 184#define MM_PMC_BBRAM_CTRL_SIZE 0x00050 185#define MM_PMC_EFUSE_CTRL 0xf1240000 186#define MM_PMC_EFUSE_CTRL_SIZE 0x00104 187#define MM_PMC_EFUSE_CACHE 0xf1250000 188#define MM_PMC_EFUSE_CACHE_SIZE 0x00C00 189 190#define MM_PMC_CRP 0xf1260000U 191#define MM_PMC_CRP_SIZE 0x10000 192#define MM_PMC_RTC 0xf12a0000 193#define MM_PMC_RTC_SIZE 0x10000 194#endif 195