LXR qemu/include/hw/block/flash.h

   1#ifndef HW_FLASH_H
   2#define HW_FLASH_H
   3
   4/* NOR flash devices */
   5
   6#include "exec/hwaddr.h"
   7#include "qom/object.h"
   8
   9/* pflash_cfi01.c */
  10
  11#define TYPE_PFLASH_CFI01 "cfi.pflash01"
  12OBJECT_DECLARE_SIMPLE_TYPE(PFlashCFI01, PFLASH_CFI01)
  13
  14
  15PFlashCFI01 *pflash_cfi01_register(hwaddr base,
  16                                   const char *name,
  17                                   hwaddr size,
  18                                   BlockBackend *blk,
  19                                   uint32_t sector_len,
  20                                   int width,
  21                                   uint16_t id0, uint16_t id1,
  22                                   uint16_t id2, uint16_t id3,
  23                                   int be);
  24BlockBackend *pflash_cfi01_get_blk(PFlashCFI01 *fl);
  25MemoryRegion *pflash_cfi01_get_memory(PFlashCFI01 *fl);
  26void pflash_cfi01_legacy_drive(PFlashCFI01 *dev, DriveInfo *dinfo);
  27
  28/* pflash_cfi02.c */
  29
  30#define TYPE_PFLASH_CFI02 "cfi.pflash02"
  31OBJECT_DECLARE_SIMPLE_TYPE(PFlashCFI02, PFLASH_CFI02)
  32
  33
  34PFlashCFI02 *pflash_cfi02_register(hwaddr base,
  35                                   const char *name,
  36                                   hwaddr size,
  37                                   BlockBackend *blk,
  38                                   uint32_t sector_len,
  39                                   int nb_mappings,
  40                                   int width,
  41                                   uint16_t id0, uint16_t id1,
  42                                   uint16_t id2, uint16_t id3,
  43                                   uint16_t unlock_addr0,
  44                                   uint16_t unlock_addr1,
  45                                   int be);
  46
  47/* nand.c */
  48DeviceState *nand_init(BlockBackend *blk, int manf_id, int chip_id);
  49void nand_setpins(DeviceState *dev, uint8_t cle, uint8_t ale,
  50                  uint8_t ce, uint8_t wp, uint8_t gnd);
  51void nand_getpins(DeviceState *dev, int *rb);
  52void nand_setio(DeviceState *dev, uint32_t value);
  53uint32_t nand_getio(DeviceState *dev);
  54uint32_t nand_getbuswidth(DeviceState *dev);
  55
  56#define NAND_MFR_TOSHIBA        0x98
  57#define NAND_MFR_SAMSUNG        0xec
  58#define NAND_MFR_FUJITSU        0x04
  59#define NAND_MFR_NATIONAL       0x8f
  60#define NAND_MFR_RENESAS        0x07
  61#define NAND_MFR_STMICRO        0x20
  62#define NAND_MFR_HYNIX          0xad
  63#define NAND_MFR_MICRON         0x2c
  64
  65/* onenand.c */
  66void *onenand_raw_otp(DeviceState *onenand_device);
  67
  68/* ecc.c */
  69typedef struct {
  70    uint8_t cp;         /* Column parity */
  71    uint16_t lp[2];     /* Line parity */
  72    uint16_t count;
  73} ECCState;
  74
  75uint8_t ecc_digest(ECCState *s, uint8_t sample);
  76void ecc_reset(ECCState *s);
  77extern const VMStateDescription vmstate_ecc_state;
  78
  79#endif
  80