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17#ifndef HW_I386_X86_H
18#define HW_I386_X86_H
19
20#include "qemu-common.h"
21#include "exec/hwaddr.h"
22#include "qemu/notify.h"
23
24#include "hw/i386/topology.h"
25#include "hw/boards.h"
26#include "hw/nmi.h"
27#include "hw/isa/isa.h"
28#include "hw/i386/ioapic.h"
29#include "qom/object.h"
30
31struct X86MachineClass {
32
33 MachineClass parent;
34
35
36
37
38 bool save_tsc_khz;
39
40 bool compat_apic_id_mode;
41
42 bool fwcfg_dma_enabled;
43};
44
45struct X86MachineState {
46
47 MachineState parent;
48
49
50
51
52 ISADevice *rtc;
53 FWCfgState *fw_cfg;
54 qemu_irq *gsi;
55 DeviceState *ioapic2;
56 GMappedFile *initrd_mapped_file;
57 HotplugHandler *acpi_dev;
58
59
60 ram_addr_t below_4g_mem_size, above_4g_mem_size;
61
62
63 bool apic_xrupt_override;
64 unsigned pci_irq_mask;
65 unsigned apic_id_limit;
66 uint16_t boot_cpus;
67 SgxEPCList *sgx_epc_list;
68
69 OnOffAuto smm;
70 OnOffAuto acpi;
71
72 char *oem_id;
73 char *oem_table_id;
74
75
76
77
78 AddressSpace *ioapic_as;
79
80
81
82
83
84
85 uint64_t bus_lock_ratelimit;
86};
87
88#define X86_MACHINE_SMM "smm"
89#define X86_MACHINE_ACPI "acpi"
90#define X86_MACHINE_OEM_ID "x-oem-id"
91#define X86_MACHINE_OEM_TABLE_ID "x-oem-table-id"
92#define X86_MACHINE_BUS_LOCK_RATELIMIT "bus-lock-ratelimit"
93
94#define TYPE_X86_MACHINE MACHINE_TYPE_NAME("x86")
95OBJECT_DECLARE_TYPE(X86MachineState, X86MachineClass, X86_MACHINE)
96
97void init_topo_info(X86CPUTopoInfo *topo_info, const X86MachineState *x86ms);
98
99uint32_t x86_cpu_apic_id_from_index(X86MachineState *pcms,
100 unsigned int cpu_index);
101
102void x86_cpu_new(X86MachineState *pcms, int64_t apic_id, Error **errp);
103void x86_cpus_init(X86MachineState *pcms, int default_cpu_version);
104CpuInstanceProperties x86_cpu_index_to_props(MachineState *ms,
105 unsigned cpu_index);
106int64_t x86_get_default_cpu_node_id(const MachineState *ms, int idx);
107const CPUArchIdList *x86_possible_cpu_arch_ids(MachineState *ms);
108CPUArchId *x86_find_cpu_slot(MachineState *ms, uint32_t id, int *idx);
109void x86_rtc_set_cpus_count(ISADevice *rtc, uint16_t cpus_count);
110void x86_cpu_pre_plug(HotplugHandler *hotplug_dev,
111 DeviceState *dev, Error **errp);
112void x86_cpu_plug(HotplugHandler *hotplug_dev,
113 DeviceState *dev, Error **errp);
114void x86_cpu_unplug_request_cb(HotplugHandler *hotplug_dev,
115 DeviceState *dev, Error **errp);
116void x86_cpu_unplug_cb(HotplugHandler *hotplug_dev,
117 DeviceState *dev, Error **errp);
118
119void x86_bios_rom_init(MachineState *ms, const char *default_firmware,
120 MemoryRegion *rom_memory, bool isapc_ram_fw);
121
122void x86_load_linux(X86MachineState *x86ms,
123 FWCfgState *fw_cfg,
124 int acpi_data_size,
125 bool pvh_enabled);
126
127bool x86_machine_is_smm_enabled(const X86MachineState *x86ms);
128bool x86_machine_is_acpi_enabled(const X86MachineState *x86ms);
129
130
131
132#define GSI_NUM_PINS IOAPIC_NUM_PINS
133#define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11))
134
135typedef struct GSIState {
136 qemu_irq i8259_irq[ISA_NUM_IRQS];
137 qemu_irq ioapic_irq[IOAPIC_NUM_PINS];
138 qemu_irq ioapic2_irq[IOAPIC_NUM_PINS];
139} GSIState;
140
141qemu_irq x86_allocate_cpu_irq(void);
142void gsi_handler(void *opaque, int n, int level);
143void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name);
144DeviceState *ioapic_init_secondary(GSIState *gsi_state);
145
146#endif
147