LXR qemu/include/hw/ide/ahci.h

   1/*
   2 * QEMU AHCI Emulation
   3 *
   4 * Copyright (c) 2010 qiaochong@loongson.cn
   5 * Copyright (c) 2010 Roland Elek <elek.roland@gmail.com>
   6 * Copyright (c) 2010 Sebastian Herbszt <herbszt@gmx.de>
   7 * Copyright (c) 2010 Alexander Graf <agraf@suse.de>
   8 *
   9 * This library is free software; you can redistribute it and/or
  10 * modify it under the terms of the GNU Lesser General Public
  11 * License as published by the Free Software Foundation; either
  12 * version 2.1 of the License, or (at your option) any later version.
  13 *
  14 * This library is distributed in the hope that it will be useful,
  15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17 * Lesser General Public License for more details.
  18 *
  19 * You should have received a copy of the GNU Lesser General Public
  20 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  21 *
  22 */
  23
  24#ifndef HW_IDE_AHCI_H
  25#define HW_IDE_AHCI_H
  26
  27#include "hw/sysbus.h"
  28#include "qom/object.h"
  29
  30typedef struct AHCIDevice AHCIDevice;
  31
  32typedef struct AHCIControlRegs {
  33    uint32_t    cap;
  34    uint32_t    ghc;
  35    uint32_t    irqstatus;
  36    uint32_t    impl;
  37    uint32_t    version;
  38} AHCIControlRegs;
  39
  40typedef struct AHCIState {
  41    DeviceState *container;
  42
  43    AHCIDevice *dev;
  44    AHCIControlRegs control_regs;
  45    MemoryRegion mem;
  46    MemoryRegion idp;       /* Index-Data Pair I/O port space */
  47    unsigned idp_offset;    /* Offset of index in I/O port space */
  48    uint32_t idp_index;     /* Current IDP index */
  49    int32_t ports;
  50    qemu_irq irq;
  51    AddressSpace *as;
  52} AHCIState;
  53
  54
  55#define TYPE_ICH9_AHCI "ich9-ahci"
  56OBJECT_DECLARE_SIMPLE_TYPE(AHCIPCIState, ICH9_AHCI)
  57
  58int32_t ahci_get_num_ports(PCIDevice *dev);
  59void ahci_ide_create_devs(PCIDevice *dev, DriveInfo **hd);
  60
  61#define TYPE_SYSBUS_AHCI "sysbus-ahci"
  62OBJECT_DECLARE_SIMPLE_TYPE(SysbusAHCIState, SYSBUS_AHCI)
  63
  64struct SysbusAHCIState {
  65    /*< private >*/
  66    SysBusDevice parent_obj;
  67    /*< public >*/
  68
  69    AHCIState ahci;
  70    uint32_t num_ports;
  71};
  72
  73#define TYPE_ALLWINNER_AHCI "allwinner-ahci"
  74OBJECT_DECLARE_SIMPLE_TYPE(AllwinnerAHCIState, ALLWINNER_AHCI)
  75
  76#define ALLWINNER_AHCI_MMIO_OFF  0x80
  77#define ALLWINNER_AHCI_MMIO_SIZE 0x80
  78
  79struct AllwinnerAHCIState {
  80    /*< private >*/
  81    SysbusAHCIState parent_obj;
  82    /*< public >*/
  83
  84    MemoryRegion mmio;
  85    uint32_t regs[ALLWINNER_AHCI_MMIO_SIZE/4];
  86};
  87
  88#endif /* HW_IDE_AHCI_H */
  89