LXR qemu/include/hw/misc/aspeed

   1/*
   2 * ASPEED SDRAM Memory Controller
   3 *
   4 * Copyright (C) 2016 IBM Corp.
   5 *
   6 * This code is licensed under the GPL version 2 or later. See the
   7 * COPYING file in the top-level directory.
   8 */
   9#ifndef ASPEED_SDMC_H
  10#define ASPEED_SDMC_H
  11
  12#include "hw/sysbus.h"
  13#include "qom/object.h"
  14
  15#define TYPE_ASPEED_SDMC "aspeed.sdmc"
  16OBJECT_DECLARE_TYPE(AspeedSDMCState, AspeedSDMCClass, ASPEED_SDMC)
  17#define TYPE_ASPEED_2400_SDMC TYPE_ASPEED_SDMC "-ast2400"
  18#define TYPE_ASPEED_2500_SDMC TYPE_ASPEED_SDMC "-ast2500"
  19#define TYPE_ASPEED_2600_SDMC TYPE_ASPEED_SDMC "-ast2600"
  20
  21/*
  22 * SDMC has 174 documented registers. In addition the u-boot device tree
  23 * describes the following regions:
  24 *  - PHY status regs at offset 0x400, length 0x200
  25 *  - PHY setting regs at offset 0x100, length 0x300
  26 *
  27 * There are two sets of MRS (Mode Registers) configuration in ast2600 memory
  28 * system: one is in the SDRAM MC (memory controller) which is used in run
  29 * time, and the other is in the DDR-PHY IP which is used during DDR-PHY
  30 * training.
  31 */
  32#define ASPEED_SDMC_NR_REGS (0x500 >> 2)
  33
  34struct AspeedSDMCState {
  35    /*< private >*/
  36    SysBusDevice parent_obj;
  37
  38    /*< public >*/
  39    MemoryRegion iomem;
  40
  41    uint32_t regs[ASPEED_SDMC_NR_REGS];
  42    uint64_t ram_size;
  43    uint64_t max_ram_size;
  44};
  45
  46
  47struct AspeedSDMCClass {
  48    SysBusDeviceClass parent_class;
  49
  50    uint64_t max_ram_size;
  51    const uint64_t *valid_ram_sizes;
  52    uint32_t (*compute_conf)(AspeedSDMCState *s, uint32_t data);
  53    void (*write)(AspeedSDMCState *s, uint32_t reg, uint32_t data);
  54};
  55
  56#endif /* ASPEED_SDMC_H */
  57